JP2009529296A5 - - Google Patents

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Publication number
JP2009529296A5
JP2009529296A5 JP2008558443A JP2008558443A JP2009529296A5 JP 2009529296 A5 JP2009529296 A5 JP 2009529296A5 JP 2008558443 A JP2008558443 A JP 2008558443A JP 2008558443 A JP2008558443 A JP 2008558443A JP 2009529296 A5 JP2009529296 A5 JP 2009529296A5
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JP
Japan
Prior art keywords
clock signal
latency
latch
signal
adjusting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008558443A
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English (en)
Japanese (ja)
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JP2009529296A (ja
JP4827932B2 (ja
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Publication date
Priority claimed from US11/371,142 external-priority patent/US7716511B2/en
Application filed filed Critical
Publication of JP2009529296A publication Critical patent/JP2009529296A/ja
Publication of JP2009529296A5 publication Critical patent/JP2009529296A5/ja
Application granted granted Critical
Publication of JP4827932B2 publication Critical patent/JP4827932B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2008558443A 2006-03-08 2007-01-29 回路装置における動的なタイミング調整 Active JP4827932B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/371,142 2006-03-08
US11/371,142 US7716511B2 (en) 2006-03-08 2006-03-08 Dynamic timing adjustment in a circuit device
PCT/US2007/061188 WO2007120957A2 (en) 2006-03-08 2007-01-29 Dynamic timing adjustment in a circuit device

Publications (3)

Publication Number Publication Date
JP2009529296A JP2009529296A (ja) 2009-08-13
JP2009529296A5 true JP2009529296A5 (enExample) 2010-03-11
JP4827932B2 JP4827932B2 (ja) 2011-11-30

Family

ID=38480317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008558443A Active JP4827932B2 (ja) 2006-03-08 2007-01-29 回路装置における動的なタイミング調整

Country Status (7)

Country Link
US (1) US7716511B2 (enExample)
EP (1) EP1999538B1 (enExample)
JP (1) JP4827932B2 (enExample)
KR (1) KR101334630B1 (enExample)
CN (1) CN101535917A (enExample)
TW (1) TWI442213B (enExample)
WO (1) WO2007120957A2 (enExample)

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US8050781B2 (en) * 2007-06-29 2011-11-01 Emulex Design & Manufacturing Corporation Systems and methods for ASIC power consumption reduction
US8161431B2 (en) * 2008-10-30 2012-04-17 Agere Systems Inc. Integrated circuit performance enhancement using on-chip adaptive voltage scaling
US8560875B2 (en) * 2009-09-17 2013-10-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode
US8575993B2 (en) 2011-08-17 2013-11-05 Broadcom Corporation Integrated circuit with pre-heating for reduced subthreshold leakage
KR20130048650A (ko) * 2011-11-02 2013-05-10 에스케이하이닉스 주식회사 집적회로 시스템 및 메모리 시스템
US20140136177A1 (en) * 2012-11-09 2014-05-15 Mediatek Inc. Critical path emulating apparatus using hybrid architecture
US9207693B1 (en) * 2014-05-29 2015-12-08 Infineon Technologies Ag Method and apparatus for compensating PVT variations
FR3024619B1 (fr) * 2014-08-01 2016-07-29 Pyxalis Circuit integre photorepete avec compensation des retards de propagation de signaux, notamment de signaux d'horloge
US9664737B2 (en) * 2014-08-19 2017-05-30 Mediatek Inc. Method for providing an on-chip variation determination and integrated circuit utilizing the same
US9413344B2 (en) * 2014-09-08 2016-08-09 Qualcomm Incorporated Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
CN105718402B (zh) * 2016-01-13 2021-04-20 福州瑞芯微电子股份有限公司 可编程时序发生器
KR102565184B1 (ko) * 2018-07-09 2023-08-08 에스케이하이닉스 주식회사 디지털 회로를 모델링하는 회로 모듈 및 이를 포함하는 시뮬레이션 장치
JP7422066B2 (ja) * 2020-12-28 2024-01-25 ルネサスエレクトロニクス株式会社 半導体装置
JP2023122380A (ja) * 2022-02-22 2023-09-01 キオクシア株式会社 半導体装置及びメモリシステム
TWI890312B (zh) * 2023-06-20 2025-07-11 宏達國際電子股份有限公司 同步信號產生電路以及多個裝置間的同步方法
US12407352B2 (en) 2023-06-20 2025-09-02 Htc Corporation Synchronization signal generation circuit and synchronization method between multiple devices

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US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US5498977A (en) * 1995-03-03 1996-03-12 Hewlett-Packard Company Output driver having process, voltage and temperature compensation for delay and risetime
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6535988B1 (en) * 1999-09-29 2003-03-18 Intel Corporation System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6829715B2 (en) * 2000-05-31 2004-12-07 Broadcom Corporation Multiprotocol computer bus interface adapter and method
US6668346B1 (en) * 2000-11-10 2003-12-23 Sun Microsystems, Inc. Digital process monitor
US6566924B2 (en) * 2001-07-25 2003-05-20 Hewlett-Packard Development Company L.P. Parallel push algorithm detecting constraints to minimize clock skew
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
US7483508B2 (en) * 2001-11-27 2009-01-27 Texas Instruments Incorporated All-digital frequency synthesis with non-linear differential term for handling frequency perturbations
WO2003069452A2 (en) * 2002-02-15 2003-08-21 Multigig Limited Electronic circuits
US6943610B2 (en) * 2002-04-19 2005-09-13 Intel Corporation Clock distribution network using feedback for skew compensation and jitter filtering
KR100470995B1 (ko) * 2002-04-23 2005-03-08 삼성전자주식회사 클럭수신 동기회로를 갖는 멀티클럭 도메인 데이터 입력처리장치 및 그에 따른 클럭신호 인가방법
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host
US6985400B2 (en) * 2002-09-30 2006-01-10 Infineon Technologies Ag On-die detection of the system operation frequency in a DRAM to adjust DRAM operations

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