JP4827932B2 - 回路装置における動的なタイミング調整 - Google Patents

回路装置における動的なタイミング調整 Download PDF

Info

Publication number
JP4827932B2
JP4827932B2 JP2008558443A JP2008558443A JP4827932B2 JP 4827932 B2 JP4827932 B2 JP 4827932B2 JP 2008558443 A JP2008558443 A JP 2008558443A JP 2008558443 A JP2008558443 A JP 2008558443A JP 4827932 B2 JP4827932 B2 JP 4827932B2
Authority
JP
Japan
Prior art keywords
clock signal
signal
latency
input
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008558443A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009529296A (ja
JP2009529296A5 (enExample
Inventor
ジャラー，エイニス，エム
マクドナルド，コリン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2009529296A publication Critical patent/JP2009529296A/ja
Publication of JP2009529296A5 publication Critical patent/JP2009529296A5/ja
Application granted granted Critical
Publication of JP4827932B2 publication Critical patent/JP4827932B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2008558443A 2006-03-08 2007-01-29 回路装置における動的なタイミング調整 Active JP4827932B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/371,142 2006-03-08
US11/371,142 US7716511B2 (en) 2006-03-08 2006-03-08 Dynamic timing adjustment in a circuit device
PCT/US2007/061188 WO2007120957A2 (en) 2006-03-08 2007-01-29 Dynamic timing adjustment in a circuit device

Publications (3)

Publication Number Publication Date
JP2009529296A JP2009529296A (ja) 2009-08-13
JP2009529296A5 JP2009529296A5 (enExample) 2010-03-11
JP4827932B2 true JP4827932B2 (ja) 2011-11-30

Family

ID=38480317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008558443A Active JP4827932B2 (ja) 2006-03-08 2007-01-29 回路装置における動的なタイミング調整

Country Status (7)

Country Link
US (1) US7716511B2 (enExample)
EP (1) EP1999538B1 (enExample)
JP (1) JP4827932B2 (enExample)
KR (1) KR101334630B1 (enExample)
CN (1) CN101535917A (enExample)
TW (1) TWI442213B (enExample)
WO (1) WO2007120957A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8050781B2 (en) * 2007-06-29 2011-11-01 Emulex Design & Manufacturing Corporation Systems and methods for ASIC power consumption reduction
US8161431B2 (en) * 2008-10-30 2012-04-17 Agere Systems Inc. Integrated circuit performance enhancement using on-chip adaptive voltage scaling
US8560875B2 (en) * 2009-09-17 2013-10-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode
US8575993B2 (en) 2011-08-17 2013-11-05 Broadcom Corporation Integrated circuit with pre-heating for reduced subthreshold leakage
KR20130048650A (ko) * 2011-11-02 2013-05-10 에스케이하이닉스 주식회사 집적회로 시스템 및 메모리 시스템
US20140136177A1 (en) * 2012-11-09 2014-05-15 Mediatek Inc. Critical path emulating apparatus using hybrid architecture
US9207693B1 (en) * 2014-05-29 2015-12-08 Infineon Technologies Ag Method and apparatus for compensating PVT variations
FR3024619B1 (fr) * 2014-08-01 2016-07-29 Pyxalis Circuit integre photorepete avec compensation des retards de propagation de signaux, notamment de signaux d'horloge
US9664737B2 (en) * 2014-08-19 2017-05-30 Mediatek Inc. Method for providing an on-chip variation determination and integrated circuit utilizing the same
US9413344B2 (en) * 2014-09-08 2016-08-09 Qualcomm Incorporated Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
CN105718402B (zh) * 2016-01-13 2021-04-20 福州瑞芯微电子股份有限公司 可编程时序发生器
KR102565184B1 (ko) * 2018-07-09 2023-08-08 에스케이하이닉스 주식회사 디지털 회로를 모델링하는 회로 모듈 및 이를 포함하는 시뮬레이션 장치
JP7422066B2 (ja) * 2020-12-28 2024-01-25 ルネサスエレクトロニクス株式会社 半導体装置
JP2023122380A (ja) * 2022-02-22 2023-09-01 キオクシア株式会社 半導体装置及びメモリシステム
TWI890312B (zh) * 2023-06-20 2025-07-11 宏達國際電子股份有限公司 同步信號產生電路以及多個裝置間的同步方法
US12407352B2 (en) 2023-06-20 2025-09-02 Htc Corporation Synchronization signal generation circuit and synchronization method between multiple devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141936A1 (en) * 2001-11-27 2003-07-31 Staszewski Robert B. All-digital frequency synthesis with non-linear differential term for handling frequency perturbations
JP2004094945A (ja) * 2002-08-29 2004-03-25 Seiko Epson Corp ホストと、ホストよりも大きなレイテンシを有するスレーブデバイス間のインタフェース
US20050225365A1 (en) * 2002-02-15 2005-10-13 John Wood Electronic circuits

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US5498977A (en) * 1995-03-03 1996-03-12 Hewlett-Packard Company Output driver having process, voltage and temperature compensation for delay and risetime
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6535988B1 (en) * 1999-09-29 2003-03-18 Intel Corporation System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6829715B2 (en) * 2000-05-31 2004-12-07 Broadcom Corporation Multiprotocol computer bus interface adapter and method
US6668346B1 (en) * 2000-11-10 2003-12-23 Sun Microsystems, Inc. Digital process monitor
US6566924B2 (en) * 2001-07-25 2003-05-20 Hewlett-Packard Development Company L.P. Parallel push algorithm detecting constraints to minimize clock skew
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
US6943610B2 (en) * 2002-04-19 2005-09-13 Intel Corporation Clock distribution network using feedback for skew compensation and jitter filtering
KR100470995B1 (ko) * 2002-04-23 2005-03-08 삼성전자주식회사 클럭수신 동기회로를 갖는 멀티클럭 도메인 데이터 입력처리장치 및 그에 따른 클럭신호 인가방법
US6985400B2 (en) * 2002-09-30 2006-01-10 Infineon Technologies Ag On-die detection of the system operation frequency in a DRAM to adjust DRAM operations

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030141936A1 (en) * 2001-11-27 2003-07-31 Staszewski Robert B. All-digital frequency synthesis with non-linear differential term for handling frequency perturbations
US20050225365A1 (en) * 2002-02-15 2005-10-13 John Wood Electronic circuits
JP2004094945A (ja) * 2002-08-29 2004-03-25 Seiko Epson Corp ホストと、ホストよりも大きなレイテンシを有するスレーブデバイス間のインタフェース

Also Published As

Publication number Publication date
US20070214377A1 (en) 2007-09-13
TWI442213B (zh) 2014-06-21
EP1999538A2 (en) 2008-12-10
KR101334630B1 (ko) 2013-12-02
JP2009529296A (ja) 2009-08-13
CN101535917A (zh) 2009-09-16
TW200801891A (en) 2008-01-01
EP1999538A4 (en) 2014-01-08
WO2007120957A3 (en) 2009-04-09
US7716511B2 (en) 2010-05-11
WO2007120957A2 (en) 2007-10-25
EP1999538B1 (en) 2018-08-22
KR20080098524A (ko) 2008-11-10

Similar Documents

Publication Publication Date Title
JP4827932B2 (ja) 回路装置における動的なタイミング調整
US8040155B2 (en) Systems and methods of integrated circuit clocking
CN100334523C (zh) 用于多核心微处理器热管理的装置
JP3737701B2 (ja) 遅延ロックループを備えた遅延装置及びこれの較正方法
US7639054B1 (en) Techniques for generating programmable delays
KR102839436B1 (ko) 디지털 주파수-고정 루프의 드룹 검출 및 제어
JP2015530820A (ja) クロック信号を調整するシステムおよび方法
WO2007038033A2 (en) Method and apparatus for late timing transition detection
US7486126B2 (en) Semiconductor integrated circuit with pulse generation sections
JP4852770B2 (ja) 遅延回路のための方法および装置
CN101013883A (zh) 数据延迟控制电路及方法
CN110649922A (zh) 一种数字时钟倍频器
US7688671B2 (en) Semiconductor memory chip with on-die termination function
US20180219541A1 (en) Semiconductor device
US12461166B2 (en) On-die power supply monitor design
JP2008010607A (ja) 半導体集積回路およびクロックスキュー低減方法
KR20250050024A (ko) 지연 라인을 이용한 저전력 인터-다이 통신
US7885322B2 (en) Jitter measuring circuit
WO2024255999A1 (en) Clock generator system and method
JPH02226316A (ja) 半導体装置
JP2005094484A (ja) 位相差検出回路、クロックスキュー補正回路、位相差検出方法及びクロックスキュー補正方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100119

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100119

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110906

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110913

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140922

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4827932

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250