KR101334630B1 - 회로 디바이스에서 동적 타이밍 조정 - Google Patents

회로 디바이스에서 동적 타이밍 조정 Download PDF

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KR101334630B1
KR101334630B1 KR1020087021970A KR20087021970A KR101334630B1 KR 101334630 B1 KR101334630 B1 KR 101334630B1 KR 1020087021970 A KR1020087021970 A KR 1020087021970A KR 20087021970 A KR20087021970 A KR 20087021970A KR 101334630 B1 KR101334630 B1 KR 101334630B1
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signal
clock signal
latch
input
output
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KR20080098524A (ko
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아니스 엠. 자라
콜린 맥도날드
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프리스케일 세미컨덕터, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
KR1020087021970A 2006-03-08 2007-01-29 회로 디바이스에서 동적 타이밍 조정 Active KR101334630B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/371,142 2006-03-08
US11/371,142 US7716511B2 (en) 2006-03-08 2006-03-08 Dynamic timing adjustment in a circuit device
PCT/US2007/061188 WO2007120957A2 (en) 2006-03-08 2007-01-29 Dynamic timing adjustment in a circuit device

Publications (2)

Publication Number Publication Date
KR20080098524A KR20080098524A (ko) 2008-11-10
KR101334630B1 true KR101334630B1 (ko) 2013-12-02

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ID=38480317

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KR1020087021970A Active KR101334630B1 (ko) 2006-03-08 2007-01-29 회로 디바이스에서 동적 타이밍 조정

Country Status (7)

Country Link
US (1) US7716511B2 (enExample)
EP (1) EP1999538B1 (enExample)
JP (1) JP4827932B2 (enExample)
KR (1) KR101334630B1 (enExample)
CN (1) CN101535917A (enExample)
TW (1) TWI442213B (enExample)
WO (1) WO2007120957A2 (enExample)

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US8050781B2 (en) * 2007-06-29 2011-11-01 Emulex Design & Manufacturing Corporation Systems and methods for ASIC power consumption reduction
US8161431B2 (en) * 2008-10-30 2012-04-17 Agere Systems Inc. Integrated circuit performance enhancement using on-chip adaptive voltage scaling
US8560875B2 (en) * 2009-09-17 2013-10-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode
US8575993B2 (en) 2011-08-17 2013-11-05 Broadcom Corporation Integrated circuit with pre-heating for reduced subthreshold leakage
KR20130048650A (ko) * 2011-11-02 2013-05-10 에스케이하이닉스 주식회사 집적회로 시스템 및 메모리 시스템
US20140136177A1 (en) * 2012-11-09 2014-05-15 Mediatek Inc. Critical path emulating apparatus using hybrid architecture
US9207693B1 (en) * 2014-05-29 2015-12-08 Infineon Technologies Ag Method and apparatus for compensating PVT variations
FR3024619B1 (fr) * 2014-08-01 2016-07-29 Pyxalis Circuit integre photorepete avec compensation des retards de propagation de signaux, notamment de signaux d'horloge
US9664737B2 (en) * 2014-08-19 2017-05-30 Mediatek Inc. Method for providing an on-chip variation determination and integrated circuit utilizing the same
US9413344B2 (en) * 2014-09-08 2016-08-09 Qualcomm Incorporated Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
CN105718402B (zh) * 2016-01-13 2021-04-20 福州瑞芯微电子股份有限公司 可编程时序发生器
KR102565184B1 (ko) * 2018-07-09 2023-08-08 에스케이하이닉스 주식회사 디지털 회로를 모델링하는 회로 모듈 및 이를 포함하는 시뮬레이션 장치
JP7422066B2 (ja) * 2020-12-28 2024-01-25 ルネサスエレクトロニクス株式会社 半導体装置
JP2023122380A (ja) * 2022-02-22 2023-09-01 キオクシア株式会社 半導体装置及びメモリシステム
TWI819628B (zh) * 2022-05-26 2023-10-21 瑞昱半導體股份有限公司 速度偵測電路與相關的晶片
US12407352B2 (en) 2023-06-20 2025-09-02 Htc Corporation Synchronization signal generation circuit and synchronization method between multiple devices
TWI890312B (zh) * 2023-06-20 2025-07-11 宏達國際電子股份有限公司 同步信號產生電路以及多個裝置間的同步方法

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US6754840B2 (en) 1999-09-29 2004-06-22 Intel Corporation Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate
US6952378B2 (en) 2002-09-30 2005-10-04 Infineon Technologies Ag Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations
US7038971B2 (en) 2002-04-23 2006-05-02 Samsung Electronics Co., Ltd. Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof

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US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US5498977A (en) 1995-03-03 1996-03-12 Hewlett-Packard Company Output driver having process, voltage and temperature compensation for delay and risetime
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6643787B1 (en) 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
AU2001275503A1 (en) * 2000-05-31 2001-12-11 Broadcom Corporation Multiprotocol computer bus interface adapter and method
US6668346B1 (en) 2000-11-10 2003-12-23 Sun Microsystems, Inc. Digital process monitor
US6566924B2 (en) 2001-07-25 2003-05-20 Hewlett-Packard Development Company L.P. Parallel push algorithm detecting constraints to minimize clock skew
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
US7483508B2 (en) 2001-11-27 2009-01-27 Texas Instruments Incorporated All-digital frequency synthesis with non-linear differential term for handling frequency perturbations
CN1647012A (zh) 2002-02-15 2005-07-27 马尔帝吉格有限公司 电子电路
US6943610B2 (en) * 2002-04-19 2005-09-13 Intel Corporation Clock distribution network using feedback for skew compensation and jitter filtering
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6754840B2 (en) 1999-09-29 2004-06-22 Intel Corporation Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate
US7038971B2 (en) 2002-04-23 2006-05-02 Samsung Electronics Co., Ltd. Multi-clock domain data input-processing device having clock-receiving locked loop and clock signal input method thereof
US6952378B2 (en) 2002-09-30 2005-10-04 Infineon Technologies Ag Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations

Also Published As

Publication number Publication date
WO2007120957A2 (en) 2007-10-25
JP4827932B2 (ja) 2011-11-30
EP1999538A2 (en) 2008-12-10
WO2007120957A3 (en) 2009-04-09
JP2009529296A (ja) 2009-08-13
CN101535917A (zh) 2009-09-16
KR20080098524A (ko) 2008-11-10
EP1999538A4 (en) 2014-01-08
TWI442213B (zh) 2014-06-21
US20070214377A1 (en) 2007-09-13
TW200801891A (en) 2008-01-01
US7716511B2 (en) 2010-05-11
EP1999538B1 (en) 2018-08-22

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