JP2010532572A - トランジスタのゲート電極のプレアモルファス化のブロッキング - Google Patents

トランジスタのゲート電極のプレアモルファス化のブロッキング Download PDF

Info

Publication number
JP2010532572A
JP2010532572A JP2010514850A JP2010514850A JP2010532572A JP 2010532572 A JP2010532572 A JP 2010532572A JP 2010514850 A JP2010514850 A JP 2010514850A JP 2010514850 A JP2010514850 A JP 2010514850A JP 2010532572 A JP2010532572 A JP 2010532572A
Authority
JP
Japan
Prior art keywords
transistor
gate electrode
preamorphized
source
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010514850A
Other languages
English (en)
Japanese (ja)
Inventor
モーリー アンソニー
レンスキ マルクス
ウェイ アンディ
ボシュケ ロマン
Original Assignee
グローバルファウンドリーズ・インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by グローバルファウンドリーズ・インコーポレイテッド filed Critical グローバルファウンドリーズ・インコーポレイテッド
Publication of JP2010532572A publication Critical patent/JP2010532572A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
JP2010514850A 2007-06-29 2008-06-30 トランジスタのゲート電極のプレアモルファス化のブロッキング Pending JP2010532572A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102007030056A DE102007030056B3 (de) 2007-06-29 2007-06-29 Verfahren zum Blockieren einer Voramorphisierung einer Gateelektrode eines Transistors
US12/026,273 US7879667B2 (en) 2007-06-29 2008-02-05 Blocking pre-amorphization of a gate electrode of a transistor
PCT/US2008/008152 WO2009005787A1 (en) 2007-06-29 2008-06-30 Blocking pre-amorphization of a gate electrode of a transistor

Publications (1)

Publication Number Publication Date
JP2010532572A true JP2010532572A (ja) 2010-10-07

Family

ID=40149341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010514850A Pending JP2010532572A (ja) 2007-06-29 2008-06-30 トランジスタのゲート電極のプレアモルファス化のブロッキング

Country Status (8)

Country Link
US (1) US7879667B2 (de)
JP (1) JP2010532572A (de)
KR (1) KR101413272B1 (de)
CN (1) CN101809713B (de)
DE (1) DE102007030056B3 (de)
GB (1) GB201000477D0 (de)
TW (1) TWI438847B (de)
WO (1) WO2009005787A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101279326B1 (ko) * 2011-10-20 2013-06-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다수의 스트레스 구조들을 갖는 반도체 디바이스 및 이의 형성 방법

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070108529A1 (en) * 2005-11-14 2007-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strained gate electrodes in semiconductor devices
DE102008016426B4 (de) * 2008-03-31 2012-04-19 Globalfoundries Inc. Verfahren zum Erzeugen einer Zugverformung durch Anwenden von Verspannungsgedächtnistechniken in unmittelbarer Nähe zu der Gateelektrode
US20100120351A1 (en) * 2008-11-10 2010-05-13 Thermo Fisher Scientific (Asheville) Llc Frost reduction by air curtain
US7902541B2 (en) * 2009-04-03 2011-03-08 International Business Machines Corporation Semiconductor nanowire with built-in stress
JP5075897B2 (ja) * 2009-09-25 2012-11-21 株式会社東芝 半導体装置の製造方法
TWI473208B (zh) * 2009-10-23 2015-02-11 United Microelectronics Corp 一種製作互補式金氧半導體電晶體的方法
DE102010028462B4 (de) * 2010-04-30 2015-06-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verspannungsgedächtnistechnik mit geringerer Randzonenkapazität auf der Grundlage von Siliziumnitrid in MOS-Halbleiterbauelementen
US8030154B1 (en) * 2010-08-03 2011-10-04 International Business Machines Corporation Method for forming a protection layer over metal semiconductor contact and structure formed thereon
US8551845B2 (en) 2010-09-21 2013-10-08 International Business Machines Corporation Structure and method for increasing strain in a device
US8343825B2 (en) 2011-01-19 2013-01-01 International Business Machines Corporation Reducing dislocation formation in semiconductor devices through targeted carbon implantation
US8629046B2 (en) * 2011-07-06 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with a dislocation structure and method of forming the same
CN102983104B (zh) * 2011-09-07 2015-10-21 中芯国际集成电路制造(上海)有限公司 Cmos晶体管的制作方法
TWI567826B (zh) * 2011-09-21 2017-01-21 聯華電子股份有限公司 半導體元件製造方法
JP5955670B2 (ja) * 2011-09-26 2016-07-20 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法
CN103050430B (zh) * 2011-10-14 2015-11-25 中国科学院微电子研究所 半导体器件及其制造方法
US20130237026A1 (en) * 2012-03-09 2013-09-12 Taiwan Semiconductor Manufacturing Company, Ltd., ("Tsmc") Finfet device having a strained region
US9224604B2 (en) 2012-04-05 2015-12-29 Globalfoundries Inc. Device and method for forming sharp extension region with controllable junction depth and lateral overlap
US8877599B2 (en) 2012-05-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
CN103594350B (zh) * 2013-10-22 2016-04-06 溧阳市东大技术转移中心有限公司 一种减小界面层生长的方法
KR102137371B1 (ko) * 2013-10-29 2020-07-27 삼성전자 주식회사 반도체 장치 및 이의 제조 방법
TWI550716B (zh) * 2015-07-08 2016-09-21 力晶科技股份有限公司 半導體元件的製造方法
CN109346440B (zh) * 2018-09-28 2021-07-06 长江存储科技有限责任公司 半导体器件的制造方法和集成电路的制造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5845099A (en) * 1996-06-28 1998-12-01 Intel Corporation Length detecting unit for parallel processing of variable sequential instructions
JPH11168069A (ja) * 1997-12-03 1999-06-22 Nec Corp 半導体装置の製造方法
US5948096A (en) * 1997-12-23 1999-09-07 Intel Corporation Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes
US6355543B1 (en) * 1998-09-29 2002-03-12 Advanced Micro Devices, Inc. Laser annealing for forming shallow source/drain extension for MOS transistor
US6260134B1 (en) 1998-11-02 2001-07-10 Advanced Micro Devices, Inc. Fixed shift amount variable length instruction stream pre-decoding for start byte determination based on prefix indicating length vector presuming potential start byte
US6180476B1 (en) * 1998-11-06 2001-01-30 Advanced Micro Devices, Inc. Dual amorphization implant process for ultra-shallow drain and source extensions
US6265293B1 (en) * 1999-08-27 2001-07-24 Advanced Micro Devices, Inc. CMOS transistors fabricated in optimized RTA scheme
US6335253B1 (en) * 2000-07-12 2002-01-01 Chartered Semiconductor Manufacturing Ltd. Method to form MOS transistors with shallow junctions using laser annealing
US6403434B1 (en) * 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6682980B2 (en) * 2002-05-06 2004-01-27 Texas Instruments Incorporated Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
EP1524699B1 (de) * 2003-10-17 2012-12-26 Imec Verfahren zur Herstellung CMOS Bauelementen mit einer kerbenförmigen Gatterisolierschicht und so erhaltene Vorrichtungen
DE102004031743B4 (de) * 2004-06-30 2006-10-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Epitaxieschicht für erhöhte Drain-und Sourcegebiete durch Entfernen von Oberflächendefekten der anfänglichen Kristalloberfläche
DE102004031710B4 (de) * 2004-06-30 2007-12-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen unterschiedlich verformter Halbleitergebiete und Transistorpaar in unterschiedlich verformten Halbleitergebieten
WO2007035398A2 (en) * 2005-09-15 2007-03-29 Amberwave Systems Corporation Control of strain in device layers by selective relaxation and prevention of relaxation
DE102006019935B4 (de) * 2006-04-28 2011-01-13 Advanced Micro Devices, Inc., Sunnyvale SOI-Transistor mit reduziertem Körperpotential und ein Verfahren zur Herstellung
DE102006019936B4 (de) * 2006-04-28 2015-01-29 Globalfoundries Inc. Halbleiterbauelement mit unterschiedlich verspannten Ätzstoppschichten in Verbindung mit PN-Übergängen unterschiedlicher Gestaltung in unterschiedlichen Bauteilgebieten und Verfahren zur Herstellung des Halbleiterbauelements
DE102006035646B3 (de) * 2006-07-31 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung verformter Transistoren durch Verspannungskonservierung auf der Grundlage einer verspannten Implantationsmaske

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101279326B1 (ko) * 2011-10-20 2013-06-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 다수의 스트레스 구조들을 갖는 반도체 디바이스 및 이의 형성 방법

Also Published As

Publication number Publication date
GB2462989A (en) 2010-03-03
US20090001371A1 (en) 2009-01-01
WO2009005787A1 (en) 2009-01-08
KR20100046159A (ko) 2010-05-06
GB201000477D0 (en) 2010-03-03
CN101809713B (zh) 2012-04-25
TWI438847B (zh) 2014-05-21
TW200915434A (en) 2009-04-01
US7879667B2 (en) 2011-02-01
KR101413272B1 (ko) 2014-06-27
DE102007030056B3 (de) 2009-01-22
CN101809713A (zh) 2010-08-18

Similar Documents

Publication Publication Date Title
US7879667B2 (en) Blocking pre-amorphization of a gate electrode of a transistor
JP5204645B2 (ja) 強化した応力伝送効率でコンタクト絶縁層を形成する技術
US8772878B2 (en) Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material
JP4937253B2 (ja) コンタクト絶縁層および異なる特性を有するシリサイド領域を形成するための技法
JP5795735B2 (ja) チャネル領域への減少させられたオフセットを有する埋め込みＳｉ／Ｇｅ材質を伴うトランジスタ
JP4937263B2 (ja) Ｎｍｏｓトランジスタおよびｐｍｏｓトランジスタに凹んだ歪みのあるドレイン／ソース領域を形成する技術
US7344984B2 (en) Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors
TWI387009B (zh) 藉由偏斜式預非晶形化而減少受應變之電晶體中之晶體缺陷之技術
KR101148138B1 (ko) 리세스된 드레인 및 소스 영역을 갖는 ｎｍｏｓ 트랜지스터와 드레인 및 소스 영역에 실리콘/게르마늄 물질을 갖는 ｐｍｏｓ 트랜지스터를 포함하는 ｃｍｏｓ 디바이스
JP5544367B2 (ja) トランジスタにおいて進歩したシリサイド形成と組み合わされる凹型のドレイン及びソース区域
JP2009545879A (ja) 応力注入マスクに基づく応力メモライゼーションにより歪みトランジスタを形成する方法
US20090001479A1 (en) Transistor having reduced gate resistance and enhanced stress transfer efficiency and method of forming the same
US7906385B2 (en) Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps
JP2012516556A (ja) 減少させられたゲート電極ピッチを有する非対称トランジスタのための段階的なウエル注入
US8999803B2 (en) Methods for fabricating integrated circuits with the implantation of fluorine
US7951662B2 (en) Method of fabricating strained silicon transistor
WO2008016505A1 (en) Method for forming a strained transistor by stress memorization based on a stressed implantation mask
US8916430B2 (en) Methods for fabricating integrated circuits with the implantation of nitrogen
US20100025742A1 (en) Transistor having a strained channel region caused by hydrogen-induced lattice deformation

Legal Events

Date Code Title Description
RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902