JP2010502013A5 - - Google Patents

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Publication number
JP2010502013A5
JP2010502013A5 JP2009525600A JP2009525600A JP2010502013A5 JP 2010502013 A5 JP2010502013 A5 JP 2010502013A5 JP 2009525600 A JP2009525600 A JP 2009525600A JP 2009525600 A JP2009525600 A JP 2009525600A JP 2010502013 A5 JP2010502013 A5 JP 2010502013A5
Authority
JP
Japan
Prior art keywords
floating gate
well region
gate portion
doped well
shield layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009525600A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010502013A (ja
Filing date
Publication date
Priority claimed from US11/639,658 external-priority patent/US7759727B2/en
Application filed filed Critical
Publication of JP2010502013A publication Critical patent/JP2010502013A/ja
Publication of JP2010502013A5 publication Critical patent/JP2010502013A5/ja
Pending legal-status Critical Current

Links

JP2009525600A 2006-08-21 2007-08-20 フローティングゲートトンネリング素子構造体のシールド Pending JP2010502013A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US83926206P 2006-08-21 2006-08-21
US11/639,658 US7759727B2 (en) 2006-08-21 2006-12-14 Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology
PCT/US2007/018442 WO2008024322A1 (en) 2006-08-21 2007-08-20 Shielding floating gate tunneling element structure

Publications (2)

Publication Number Publication Date
JP2010502013A JP2010502013A (ja) 2010-01-21
JP2010502013A5 true JP2010502013A5 (https=) 2010-09-30

Family

ID=38776179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009525600A Pending JP2010502013A (ja) 2006-08-21 2007-08-20 フローティングゲートトンネリング素子構造体のシールド

Country Status (6)

Country Link
US (1) US7759727B2 (https=)
EP (1) EP2067169A1 (https=)
JP (1) JP2010502013A (https=)
CN (1) CN101506968B (https=)
TW (1) TW200818410A (https=)
WO (1) WO2008024322A1 (https=)

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US9087587B2 (en) * 2013-03-15 2015-07-21 GlobalFoundries, Inc. Integrated circuits and methods for operating integrated circuits with non-volatile memory
US9312015B1 (en) * 2014-10-25 2016-04-12 Sandisk Technologies Inc. Methods for reducing body effect and increasing junction breakdown voltage
US9450052B1 (en) * 2015-07-01 2016-09-20 Chengdu Monolithic Power Systems Co., Ltd. EEPROM memory cell with a coupler region and method of making the same
CN109037225B (zh) * 2018-09-19 2023-09-12 长江存储科技有限责任公司 存储器结构
US10741611B1 (en) 2019-02-11 2020-08-11 International Business Machines Corporation Resistive processing units with complementary metal-oxide-semiconductor non-volatile analog memory
US11450677B2 (en) * 2020-11-09 2022-09-20 Globalfoundries Singapore Pte. Ltd. Partially silicided nonvolatile memory devices and integration schemes
CN115472699B (zh) * 2022-09-29 2025-12-23 西安电子科技大学 一种系pn结的复合结构mos抗辐照器件及制备方法

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JP3059442B2 (ja) * 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
US4970565A (en) * 1988-09-01 1990-11-13 Atmel Corporation Sealed charge storage structure
JPH0357280A (ja) 1989-07-25 1991-03-12 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US5576568A (en) * 1995-01-18 1996-11-19 Actel Corporation Single-transistor electrically-alterable switch employing fowler nordheim tunneling for program and erase
US6740573B2 (en) * 1995-02-17 2004-05-25 Micron Technology, Inc. Method for forming an integrated circuit interconnect using a dual poly process
DE69734278D1 (de) * 1997-07-03 2006-02-09 St Microelectronics Srl Herstellungsverfahren eines nichtflüchtigen Halbleiterspeicherbauelementes mit abgeschirmtem Einpolysiliziumgate-Speicherabschnitt
US6157574A (en) * 1998-04-01 2000-12-05 National Semiconductor Corporation Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data
US6137723A (en) * 1998-04-01 2000-10-24 National Semiconductor Corporation Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure
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