US6794236B1 - Eeprom device with improved capacitive coupling and fabrication process - Google Patents
Eeprom device with improved capacitive coupling and fabrication process Download PDFInfo
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- US6794236B1 US6794236B1 US10/160,855 US16085502A US6794236B1 US 6794236 B1 US6794236 B1 US 6794236B1 US 16085502 A US16085502 A US 16085502A US 6794236 B1 US6794236 B1 US 6794236B1
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- 238000000034 method Methods 0.000 title claims description 49
- 230000008569 process Effects 0.000 title claims description 45
- 230000008878 coupling Effects 0.000 title abstract description 17
- 238000010168 coupling process Methods 0.000 title abstract description 17
- 238000005859 coupling reaction Methods 0.000 title abstract description 17
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000003990 capacitor Substances 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 239000003870 refractory metal Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000027756 respiratory electron transport chain Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 150000001793 charged compounds Chemical class 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
Definitions
- the present invention relates, generally, to electrically-erasable-programmable-read-only-memory (EEPROM) devices and, more particularly, to improving the capacitive coupling within an EEPROM device.
- EEPROM electrically-erasable-programmable-read-only-memory
- Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated.
- One particular type of non-volatile memory device is the EEPROM device.
- EEPROM device In a flash EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate. Typically, the electron transfer is carried out either by hot electron injection, or by Fowler Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode that may be formed as a region in the substrate. The control-gate is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode.
- EEPROM cells are extensively used in programmable logic devices (PLDs). EEPROM cells used in PLDs can have a two transistor design or a three transistor design.
- a three transistor EEPROM cell for example, includes a write transistor, a read transistor, and a sense transistor. In a two transistor device, the functions of read and sense transistors are combined into a single transistor.
- a high voltage V pp + is applied to the gate electrode of the write transistor and a relatively high voltage V pp is applied to the drain (bitline contact) of the write transistor.
- V pp is applied to the gate electrode of the write transistor and a relatively high voltage V pp is applied to the drain (bitline contact) of the write transistor.
- the voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bitline to be transferred to the source of the write transistor.
- Electrons on the floating-gate electrode are drawn from the floating-gate electrode to the source of the write transistor, leaving the floating-gate electrode at a high positive potential.
- the application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
- a voltage V cc is applied to the gate of the write transistor and ground potential is applied to the bitline and a high voltage V pp + is applied to the control-gate.
- V pp + is applied to the control-gate.
- Efficient programming of the EEPROM cell requires a large capacitive coupling between the floating gate electrode and the array-control-gate. Improved capacitive coupling also allows programming and erasing to be carried out at reduced voltages. Additionally, during the read cycle, improved reading currents can be achieved. The capacitive coupling is improved by increasing the capacitor area, which is typically accomplished by increasing the size of the floating gate electrode or substrate area of the array-control-gate, or both.
- the present invention is for an EEPROM device with improved capacitive coupling and a process for fabricating the device.
- a single-gate layer EEPROM device is provided having a high coupling ratio between the floating gate electrode and a control gate electrode residing in a semiconductor substrate in close proximity to the floating gate electrode.
- a capacitor plate that at least partially overlies the floating gate electrode, a large capacitive coupling is obtained between the control gate and the floating gate.
- the substrate area required for the control gate can be reduced enabling the overall size of the EEPROM device to also be reduced.
- a single-gate layer EEPROM device that includes a control gate region in a semiconductor substrate and a floating gate electrode overlying at least a portion of the control gate region and separated from the control gate region by a first capacitor dielectric layer.
- a second capacitor dielectric layer overlies the floating gate electrode and a capacitor plate at least partially encapsulates the floating gate electrode. The capacitor plate is locally interconnected to the control gate region.
- the invention includes a process for fabricating a single-gate layer EEPROM device that includes providing a semiconductor substrate having a floating gate electrode overlying a control gate region and separated from the control gate region by a first capacitor dielectric layer.
- a second capacitor dielectric layer is formed to overlie the floating gate electrode and a salicide process is carried out to form a capacitor plate that encapsulates at least a portion of a floating gate electrode and a local interconnect is formed to electrically couple the salicide capacitor plate to the control gate region in the semiconductor substrate.
- FIGS. 1-5 illustrate, in cross-section, process steps in accordance with the invention
- FIGS. 6A and 6B are partial composite views of alternative embodiments of the device illustrate in FIG. 5;
- FIGS. 7A and 7B illustrate schematic circuit diagrams of 3-transistor EEPROM devices arranged in accordance with the invention.
- FIGS. 8A and 8B illustrate schematic circuit diagrams of 2-transistor EEPROM devices arranged in accordance with the invention.
- a semiconductor substrate 10 includes a control gate region 12 in semiconductor substrate 10 and electrically isolated from a program junction region 14 by isolation regions 16 and 18 .
- program junction region refers to a highly doped junction region in the substrate underlying the tunnel region and the control gate region.
- the program junction region is also known in the art by various terms, such as the tunneling implant region.
- a second program junction region 20 resides in control gate region 12 and is electrically isolated from program junction region 14 by isolation region 16 .
- Semiconductor substrate 10 further includes source and drain regions 22 and 24 , respectively. The source and drain regions reside in an active region (not shown) and are electrically isolated from control gate region 12 and from remaining portions of substrate 10 by isolation regions 18 and 26 .
- a floating gate electrode 28 overlies control gate region 12 and program junction region 14 .
- Floating gate electrode 28 is separated from control gate region 12 by a first capacitor dielectric layer 30 and from program junction region 14 by a tunnel dielectric layer 32 .
- a gate electrode 34 resides adjacent to floating gate electrode 28 and overlies a channel region located between source and drain regions 22 and 24 .
- a gate dielectric layer 36 separates gate electrode 34 from semiconductor substrate 10 .
- FIG. 1 Also illustrated in FIG. 1 is a portion of a floating gate electrode 28 ′ that is associated with an adjacent EEPROM memory cell.
- EEPROM memory cell many memory cells are formed in close proximity to one another, such as in an embedded memory array within an integrated circuit device.
- the device and process of the present invention will be described in the context of an N-type EEPROM memory cell.
- semiconductor substrate 10 is illustrated as a single-crystal semiconductor substrate, other types of semiconductor substrates, such as epitaxial substrates, silicon-on-insulator substrates, and the like, can also be employed in the present invention.
- isolation regions illustrated in FIG. 1 are generally descriptive of trench isolation regions, other kinds of isolation regions can also be fabricated, such as those obtained by a localized-oxidation-of-silicon (LOCOS) process, and the like.
- LOC localized-oxidation-of-silicon
- floating gate electrodes 28 and 28 ′ and gate electrode 34 are preferably fabricated by the deposition and anisotropic etching of polycrystalline silicon, other electrically conductive and semiconductive material, such as refractory metals, refractory metal silicides, and the like, and also be employed to form electrode structures.
- a second capacitor dielectric layer 38 is formed to overlie semiconductor substrate 10 .
- second capacitor dielectric layer 38 is a blanket-deposited dielectric layer that conformally overlies floating gate electrodes 28 and 28 ′ and gate electrode 34 .
- a second capacitor dielectric layer 38 can be fabricated from a wide variety of dielectric materials. The choice of a particular dielectric material is determined by device performance and reliability characteristics necessary for a specific application.
- second capacitor dielectric layer 38 can be fabricated from substantially the same material as first capacitor dielectric layer 30 . Alternatively, different materials can be utilized for the fabrication of first and second capacitor dielectric layers 30 and 38 .
- first and second capacitor dielectric layers 30 and 38 can be a dielectric material, such as silicon oxide, oxynitride, a composite dielectric layer including silicon oxide and silicon nitride, and the like.
- first and second capacitor dielectric layer 30 and 38 can be a high dielectric constant material, such as a refractory metal oxide.
- a suitable high dielectric constant metal oxide is tantalum oxide.
- Lithographic pattern 40 can be formed from a photolithographic material, such as photoresist, and the like, a deep-UV resist material, and X-ray resist material, and the like.
- an etching process is carried out to remove portions of second capacitor dielectric layer 38 exposed by lithographic pattern 40 .
- the etching process can be isotropic or anisotropic.
- silicon layer 46 is deposited to overlie semiconductor substrate 10 , as illustrated in FIG. 3 .
- Silicon layer 46 is preferably conformally deposited by a chemical-vapor-deposition (CVD) process to overlie floating gate electrodes 28 and 28 ′, gate electrode 34 , and capacitor dielectric portion 42 .
- silicon layer 46 can be any of a number of different kinds of silicon, including polycrystalline silicon, amorphous silicon, and the like.
- the etching process exposed a surface contact region 48 of semiconductor substrate 10 .
- the formation of silicon layer 46 is carried out, such that silicon layer 46 intimately contacts second program junction region 20 in semiconductor substrate 10 at surface contact region 48 .
- a lithographic pattern 49 is formed to overlie a portion of silicon layer 46 .
- Lithographic pattern 49 can be formed of a resist material similar to that used to form lithographic pattern 40 .
- capacitor plate 50 overlies a portion of floating gate electrode 28 and is electrically connected to control gate region 12 through second program junction region 20 and a local interconnect 52 . As further illustrated in FIG. 4, capacitor plate 50 also overlies a portion of adjacent floating gate electrode 28 ′. Capacitor plate 50 is electrically isolated from floating gate electrode 28 by second capacitor dielectric layer 38 .
- a metal interconnect and contact structure can also be formed to electrically connect capacitor plate 50 to second program junction region 20 .
- a metal interconnect structure requires an additional conductive layer and contact openings to expose portions of the structures to be interconnected.
- a salicide process is carried out to form a refractory metal salicide in at least surface portions of capacitor plate 50 , gate electrode 34 , source and drain regions 22 and 24 , and surface portions of semiconductor substrate 10 on either side of second capacitor dielectric portion 42 .
- the salicide process substantially converts local interconnect 52 into a suicide material.
- a thin layer of a refractory metal such as titanium, cobalt, nickel, and the like, is deposited to overlie the surface of substrate 10 .
- a thermal process is carried out to react the refractory metal with any silicon in direct contact with the refractory metal.
- the thermally induced reaction forms a refractory metal salicide as all locations where the refractory metal comes into direct contact with a silicon surface.
- the thermal process can be one of a number of different thermal processes, such as conventional conductive heating, rapid thermal annealing, and the like.
- the thermal processing can be carried out in stages, in which a first thermal annealing process is performed, followed by a brief etching process to remove unreacted portions of the refractory metal overlying dielectric surfaces, followed by a second thermal annealing step to complete the reaction to form a low-resistance refractory metal salicide.
- a first thermal annealing process is performed, followed by a brief etching process to remove unreacted portions of the refractory metal overlying dielectric surfaces, followed by a second thermal annealing step to complete the reaction to form a low-resistance refractory metal salicide.
- a first thermal annealing process is performed, followed by a brief etching process to remove unreacted portions of the refractory metal overlying dielectric surfaces, followed by a second thermal annealing step to complete the reaction to form a low-resistance refractory metal salicide.
- various surface treatment processes can be carried out prior to depositing a
- refractory metal silicide regions 54 are formed as illustrated in FIG. 5.
- a dielectric liner 56 is deposited to overlie the surface of substrate 10 .
- an inter-level-dielectric (ILD) layer 58 is formed to overlie dielectric liner 56 .
- Dielectric liner 56 and ILD layer 58 can be formed from any of a number of dielectric materials, such as silicon oxide, doped silicon oxide, silicon nitride, and the like. Further, ILD layer 58 can be formed by a CVD, or formed by a plasma-enhanced-CVD (PECVD) process, or the like.
- PECVD plasma-enhanced-CVD
- silicided capacitor plate 50 encapsulates at least a portion of floating gates 28 and 28 ′. Also, capacitor plate 50 is directly electrically connected to control gate 12 and second program junction region 20 at local interconnect 52 .
- FIG. 6A illustrates a partial composite view of the device structure illustrated in FIG. 5 in accordance with a local interconnect embodiment of the invention.
- Floating gate electrodes 28 and 28 ′ overlie portions of control gate region 12 .
- An elongated portion 60 of control gate electrode 28 extends over program junction region 14 .
- the partial composite view of FIG. 6A illustrates portions of two adjacent EEPROM memory cells sharing a common control gate region 12 .
- semiconductor devices containing embedded EEPROM memory arrays and in EEPROM device components numerous memory cells are formed and electrically coupled in order to store large quantities of information.
- floating gate electrodes 28 and 28 ′ and control gate region 12 can potentially occupy a large portion of an EEPROM memory cell. Indeed, in order to obtain a high degree of capacity coupling necessary for efficient cell operation, the substrate area required to create a high capacity coupling between floating gate electrode 28 and control gate region 12 typically can occupy a substantial portion of any EEPROM memory cell.
- a partially encapsulated floating gate electrode is created by forming capacitor plate 50 , such that it partially encapsulates floating gate electrode 28 .
- FIG. 6B illustrates a partial composite view of the device structure illustrated in FIG. 5 in accordance with a metallized interconnect embodiment of the invention.
- An electrically conductive layer 62 overlies a portion of capacitor plates 28 and 28 ′ and is electrically connected to the capacitor plates through contacts 64 and 66 .
- Electrically conductive layer 62 is also electrically connected to second program junction region 20 through a contact 68 .
- FIGS. 7A and 7B Schematic circuit diagram of two exemplary three-transistor EEPROM memory cells are illustrated in FIGS. 7A and 7B.
- control gate region 12 is depicted by the symbol “ACG”
- floating gate electrode 28 is depicted by the symbol “FG” in FIGS. 7A and 7B.
- WL represent a word line
- WBL represent a write bit line
- WLR represents a read word line
- PT represent a product term
- PSG represent a product term ground
- V 0 is an output node voltage.
- FIGS. 8A and 8B exemplary schematic circuit diagrams of two-transistor EEPROM memory cells are illustrated in FIGS. 8A and 8B.
- the components identified by symbols are the same elements as described above.
- the position of control gate region 12 and floating gate electrode 28 relative to other circuit components is also illustrated.
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Abstract
Description
Claims (14)
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US10/160,855 US6794236B1 (en) | 2002-06-03 | 2002-06-03 | Eeprom device with improved capacitive coupling and fabrication process |
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US10/160,855 US6794236B1 (en) | 2002-06-03 | 2002-06-03 | Eeprom device with improved capacitive coupling and fabrication process |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070048939A1 (en) * | 2005-08-29 | 2007-03-01 | Ralph Oberhuber | Single-poly eprom device and method of manufacturing |
US20080044973A1 (en) * | 2006-08-21 | 2008-02-21 | Alexander Kalnitsky | Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology |
US20110108929A1 (en) * | 2002-08-26 | 2011-05-12 | Round Rock Research, Llc | Enhanced atomic layer deposition |
US20150162369A1 (en) * | 2013-12-09 | 2015-06-11 | Tower Semiconductor Ltd. | Single-Poly Floating Gate Solid State Direct Radiation Sensor Using STI Dielectric And Isolated PWells |
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