JP2010258124A5 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2010258124A5
JP2010258124A5 JP2009104723A JP2009104723A JP2010258124A5 JP 2010258124 A5 JP2010258124 A5 JP 2010258124A5 JP 2009104723 A JP2009104723 A JP 2009104723A JP 2009104723 A JP2009104723 A JP 2009104723A JP 2010258124 A5 JP2010258124 A5 JP 2010258124A5
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JP
Japan
Prior art keywords
semiconductor device
finfet
insulating layer
gate insulating
field effect
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009104723A
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English (en)
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JP2010258124A (ja
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Application filed filed Critical
Priority to JP2009104723A priority Critical patent/JP2010258124A/ja
Priority claimed from JP2009104723A external-priority patent/JP2010258124A/ja
Priority to US12/662,498 priority patent/US8269271B2/en
Publication of JP2010258124A publication Critical patent/JP2010258124A/ja
Publication of JP2010258124A5 publication Critical patent/JP2010258124A5/ja
Priority to US13/585,394 priority patent/US8586437B2/en
Pending legal-status Critical Current

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Claims (1)

  1. ＦｉｎＦＥＴ（Ｆｉｎ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）と、
    前記ＦｉｎＦＥＴと同一のチップ上に設けられたＰｌａｎａｒＦＥＴ（Ｐｌａｎａｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）と
    を具備し、
    前記ＰｌａｎａｒＦＥＴの第２ゲート絶縁層は、前記ＦｉｎＦＥＴの第１ゲート絶縁層よりも厚い
    半導体装置。
JP2009104723A 2009-04-23 2009-04-23 半導体装置及び半導体装置の製造方法 Pending JP2010258124A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009104723A JP2010258124A (ja) 2009-04-23 2009-04-23 半導体装置及び半導体装置の製造方法
US12/662,498 US8269271B2 (en) 2009-04-23 2010-04-20 Hybrid planarFET and FinFET provided on a chip
US13/585,394 US8586437B2 (en) 2009-04-23 2012-08-14 Semiconductor device and method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009104723A JP2010258124A (ja) 2009-04-23 2009-04-23 半導体装置及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2010258124A JP2010258124A (ja) 2010-11-11
JP2010258124A5 true JP2010258124A5 (ja) 2012-04-19

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Family Applications (1)

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JP2009104723A Pending JP2010258124A (ja) 2009-04-23 2009-04-23 半導体装置及び半導体装置の製造方法

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US (2) US8269271B2 (ja)
JP (1) JP2010258124A (ja)

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US8901659B2 (en) * 2012-02-09 2014-12-02 International Business Machines Corporation Tapered nanowire structure with reduced off current
US8729634B2 (en) * 2012-06-15 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with high mobility and strain channel
US9431497B2 (en) * 2013-05-21 2016-08-30 Globalfoundries Singapore Pte. Ltd. Transistor devices having an anti-fuse configuration and methods of forming the same
US9166024B2 (en) * 2013-09-30 2015-10-20 United Microelectronics Corp. FinFET structure with cavities and semiconductor compound portions extending laterally over sidewall spacers
US9059020B1 (en) 2013-12-02 2015-06-16 International Business Machins Corporation Implementing buried FET below and beside FinFET on bulk substrate
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US11355493B2 (en) 2020-03-13 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method to embed planar FETs with finFETs
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