JP2010232655A - 複数の集積半導体構成素子の製造方法 - Google Patents
複数の集積半導体構成素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000010410 layer Substances 0.000 claims description 38
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 15
- 239000011247 coating layer Substances 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 2
- 239000011148 porous material Substances 0.000 claims 1
- 239000003990 capacitor Substances 0.000 description 8
- 230000000873 masking effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
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Abstract
【解決手段】集積される複数の半導体構成素子8を担体2に製造する方法では、能動基礎構造部4が、製造される半導体構成素子8の境界10の少なくとも一部を越えて連続して担体2へ挿入され、半導体構成素子8の領域が担体2に画定され、各半導体構成素子8の領域にマスク12を用いて被覆層14が担体2に塗布され、担体2が半導体構成素子8を形成するためにこれらの境界10で切断される。
【選択図】図1
Description
4 基礎構造部
6 上面
8 半導体構成素子
10 境界
12 マスク
14 被覆層
16 金属化部
18 構造部素子
20 誘電体層
22 更なる層
24 TMAH
Claims (12)
- 複数の集積される半導体構成素子(8)を担体(2)に製造するための方法であって、
− 能動基礎構造部(4)が、担体(2)へ製造されるべき半導体構成素子(8)の境界(10)の少なくとも一部を越えて連続して導入され、
− 半導体構成素子(8)の領域が、担体(2)に画定され、
− 夫々の半導体構成素子(8)の領域にマスク(12)を用いて構造化された被覆層(14)が担体(2)に塗布され、
− 担体(2)が、半導体構成素子(8)を形成するためにこれらの境界(10)で切断される
方法。 - 面上に並んで配されている同じ構造部素子(18、20、22)が、基礎構造部(4)として担体(2)へ導入される、請求項1に記載の方法。
- 孔構造部或いは溝構造部が、構造部素子(18、20、22)として担体(2)へ導入される、請求項2に記載の方法。
- 担体(2)の切断前に、少なくとも基礎構造部(4)の一部が境界(10)の領域で取り除かれる、請求項1〜3のうちのいずれか一項に記載の方法。
- 基礎構造部(4)が補助最上層(22)を有し、この補助層(22)が基礎構造部(4)の部分として境界(10)の領域で取り除かれる、請求項4に記載の方法。
- 補助層(22)としてポリシリコンが用いられる、請求項5に記載の方法。
- 補助層(22)が、TMAH(24)を用いて取り除かれる、請求項5又は6に記載の方法。
- 被覆層(14)が、マスク(12)として遮蔽マスクを用いて製造される、請求項1〜7のうちのいずれか一項に記載の方法。
- 被覆層(14)として金属化層が塗布される、請求項1〜8のうちのいずれか一項に記載の方法。
- 担体(2)としてシリコンウェハが用いられる、請求項1〜9のうちのいずれか一項に記載の方法。
- 半導体構成素子(8)として回路構成素子が半導体をベースにして製造される、請求項1〜10のうちのいずれか一項に記載の方法。
- 半導体構成素子(8)として3Dスナバ回路が製造される、請求項11に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102009001919A DE102009001919B4 (de) | 2009-03-26 | 2009-03-26 | Verfahren zum Herstellen einer Mehrzahl von integrierten Halbleiterbauelementen |
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JP2010232655A true JP2010232655A (ja) | 2010-10-14 |
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JP2010062206A Pending JP2010232655A (ja) | 2009-03-26 | 2010-03-18 | 複数の集積半導体構成素子の製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8563388B2 (ja) |
EP (1) | EP2234146A3 (ja) |
JP (1) | JP2010232655A (ja) |
KR (1) | KR20100108256A (ja) |
CN (1) | CN101847600B (ja) |
BR (1) | BRPI1000868A2 (ja) |
DE (1) | DE102009001919B4 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019012830A (ja) * | 2017-06-29 | 2019-01-24 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | 能動放電回路を備えた電気回路装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102655121A (zh) * | 2011-03-03 | 2012-09-05 | 中国科学院微电子研究所 | 牺牲栅去除方法及栅堆叠制作方法 |
DE102012202765B3 (de) | 2012-02-23 | 2013-04-18 | Semikron Elektronik Gmbh & Co. Kg | Halbleitermodul |
EP2999002A1 (en) * | 2014-09-18 | 2016-03-23 | Services Petroliers Schlumberger | Capacitor cell and method for manufacturing same |
DE102018217001B4 (de) * | 2018-10-04 | 2020-06-25 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung von Halbleiterkondensatoren unterschiedlicher Kapazitätswerte in einem Halbleitersubstrat |
DE102020127640B4 (de) | 2020-07-10 | 2024-05-08 | X-FAB Global Services GmbH | Halbleiterbauelement für Leistungselektronikanwendungen und Verfahren zum Betrieb eines Leistungsmoduls |
Citations (5)
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JPH05198741A (ja) * | 1991-08-14 | 1993-08-06 | Siemens Ag | コンデンサを備えた回路パターンおよびその製造方法 |
JPH07326715A (ja) * | 1994-05-26 | 1995-12-12 | Siemens Ag | シリコンコンデンサの製造方法 |
JPH1041504A (ja) * | 1996-07-24 | 1998-02-13 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004068005A (ja) * | 2002-06-27 | 2004-03-04 | Infineon Technologies Ag | 銅の拡散に対するバリア効果を有する誘電体 |
US20070274014A1 (en) * | 2006-04-13 | 2007-11-29 | Sven Berberich | Integrated Snubber Device on a Semiconductor Basis for Switching Load Reduction, Voltage Limitation and/or Oscillation Attenuation |
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US6689643B2 (en) * | 2002-04-25 | 2004-02-10 | Chartered Semiconductor Manufacturing Ltd. | Adjustable 3D capacitor |
JP4185704B2 (ja) * | 2002-05-15 | 2008-11-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP4830360B2 (ja) * | 2005-06-17 | 2011-12-07 | 株式会社デンソー | 半導体装置およびその製造方法 |
US7557002B2 (en) * | 2006-08-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming transistor devices |
US7781310B2 (en) * | 2007-08-07 | 2010-08-24 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
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2009
- 2009-03-26 DE DE102009001919A patent/DE102009001919B4/de active Active
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2010
- 2010-01-30 EP EP10000959.6A patent/EP2234146A3/de not_active Withdrawn
- 2010-03-18 JP JP2010062206A patent/JP2010232655A/ja active Pending
- 2010-03-19 US US12/727,759 patent/US8563388B2/en not_active Expired - Fee Related
- 2010-03-25 KR KR1020100026669A patent/KR20100108256A/ko active Search and Examination
- 2010-03-26 BR BRPI1000868-3A patent/BRPI1000868A2/pt not_active Application Discontinuation
- 2010-03-26 CN CN201010150053.3A patent/CN101847600B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05198741A (ja) * | 1991-08-14 | 1993-08-06 | Siemens Ag | コンデンサを備えた回路パターンおよびその製造方法 |
JPH07326715A (ja) * | 1994-05-26 | 1995-12-12 | Siemens Ag | シリコンコンデンサの製造方法 |
JPH1041504A (ja) * | 1996-07-24 | 1998-02-13 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004068005A (ja) * | 2002-06-27 | 2004-03-04 | Infineon Technologies Ag | 銅の拡散に対するバリア効果を有する誘電体 |
US20070274014A1 (en) * | 2006-04-13 | 2007-11-29 | Sven Berberich | Integrated Snubber Device on a Semiconductor Basis for Switching Load Reduction, Voltage Limitation and/or Oscillation Attenuation |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019012830A (ja) * | 2017-06-29 | 2019-01-24 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | 能動放電回路を備えた電気回路装置 |
JP7298997B2 (ja) | 2017-06-29 | 2023-06-27 | フラウンホッファー-ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | 能動放電回路を備えた電気回路装置 |
Also Published As
Publication number | Publication date |
---|---|
CN101847600A (zh) | 2010-09-29 |
US20100330766A1 (en) | 2010-12-30 |
CN101847600B (zh) | 2014-03-12 |
EP2234146A3 (de) | 2016-03-16 |
DE102009001919A1 (de) | 2010-09-30 |
KR20100108256A (ko) | 2010-10-06 |
US8563388B2 (en) | 2013-10-22 |
EP2234146A2 (de) | 2010-09-29 |
DE102009001919B4 (de) | 2013-10-02 |
BRPI1000868A2 (pt) | 2011-03-22 |
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