JP2010212375A - Ic搭載基板、プリント配線板、及び製造方法 - Google Patents
Ic搭載基板、プリント配線板、及び製造方法 Download PDFInfo
- Publication number
- JP2010212375A JP2010212375A JP2009055533A JP2009055533A JP2010212375A JP 2010212375 A JP2010212375 A JP 2010212375A JP 2009055533 A JP2009055533 A JP 2009055533A JP 2009055533 A JP2009055533 A JP 2009055533A JP 2010212375 A JP2010212375 A JP 2010212375A
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- Prior art keywords
- insulating
- insulating layer
- layer
- printed wiring
- wiring board
- Prior art date
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
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Abstract
【解決手段】IC搭載基板1は、絶縁材(PTFE等)からなる絶縁層20、及びその絶縁層20上に形成された配線パターン10が複数積層されてなる多層プリント配線板2と、ICのベアチップ3とが電気的に接続された構造を有する。そして、配線パターン10のうち、ベアチップ3が電気的に接続される部位を電極部10a〜10fとして、多層プリント配線板2の絶縁層20は、配線パターン10の電極部10a〜10fに対向する領域(直下領域)に銅部材6が埋設されている。なお、絶縁層20の直下領域は、絶縁層20の厚み方向をZ軸として電極部10a〜10fからZ軸方向に直下した絶縁層20内の所定領域をいう。このため、絶縁層20のうち直下領域の剛性が銅部材6により補強された構造となる。
【選択図】図3
Description
このように構成されたIC搭載基板によれば、プリント配線板の面積を小さくすることができる。
そこで、多層プリント配線板は、請求項6に記載のように、複数の絶縁層のうち、一層目の絶縁層の厚みが、他の絶縁層の厚みに比べて小さくなるように構成されることが望ましい。
次に、第二発明であるプリント配線板は、請求項9に記載のように、絶縁材からなる絶縁層上に配線パターンが形成され、その配線パターン上にICのベアチップを電気的に接続するための電極部を備えている。このうち絶縁層は、配線パターン上の電極部に対向する直下領域に、少なくとも絶縁材に比べて剛性の高い強化材が埋設されていることを要旨とする。
そして、第三発明である製造方法は、絶縁材からなる絶縁層、及びその絶縁層上に形成された配線パターンが複数積層された多層プリント配線板に、ICのベアチップが搭載されたIC搭載基板の製造方法である。なお、多層プリント配線板において、配線パターンのうちICのベアチップが電気的に接続される部位を電極部、複数の絶縁層のうち、電極部が形成された絶縁層を一層目、その一層目の絶縁層に電極部の反対側から積層される絶縁層を二層目とする。
[第一実施形態]
図1は、第一実施形態におけるIC搭載基板の構成を断面視で示す構成図、図2は、その製造方法における主要な行程を断面視で示す行程図である。
図1に示すように、IC搭載基板1は、銅薄膜を加工して形成された複数の配線パターン10が多層化された構造を有する多層プリント配線板2と、シリコン等の半導体からなるICのベアチップ3と、コンデンサーや抵抗等のチップ部品4とを備え、多層プリント配線板2の表面に、ベアチップ3及びチップ部品4が実装されている。なお、ベアチップ3と多層プリント配線板2の表面とは、金や銅等の導体ワイヤ5を介して電気的に接続されている。また、チップ部品4は、多層プリント配線板2に内蔵されてもよい。
次に、本実施形態のIC搭載基板1の製造方法Aにおける主要な行程を説明する。
図2に示すように、IC搭載基板1の製造方法Aでは、絶縁層20と配線パターン10とを一層毎に順次積み上げて作製されたベース基板8の上に、絶縁層20及び銅部材6をさらに積み上げてプレス基板9を作製するシーケンシャル積層法が用いられる。
このIC搭載基板1の製造方法Aでは、ワイヤボンディング接続により、ベアチップ3のパッド部3a,3bと、多層プリント配線板2の電極部10a,10bとを接続する際に、多層プリント配線板2側に超音波および荷重が与えられても、絶縁層20の直下位置に設けられた銅部材6により、その超音波および荷重が分散されずに済むため、電極部10a,10bに導体ワイヤ5を適切に熱融着させることができる。
また、IC搭載基板1によれば、配線パターン10と同じ線膨張係数となるように、銅部材6と配線パターン10との材質を同じにすることにより、銅部材6からの絶縁層20の剥離、及びその付随効果として、絶縁層20からの配線パターン10の剥離を防止することができる。
次に、本発明の第二実施形態を図面と共に説明する。
図3は、第二実施形態におけるIC搭載基板の構成を断面視で示す構成図、図4は、その製造方法における主要な行程を断面視で示す行程図である。
図3に示すように、本実施形態のIC搭載基板1は、第一実施形態と比較して、多層プリント配線板2の構成が主に異なるため、この相違点を中心に説明し、その他の共通する部分については説明を省略する。
次に、本実施形態のIC搭載基板1の製造方法Bにおける主要な行程を説明する。
なお、この製造方法Bは、前述した製造方法Aと比較して、プレス基板9の作製行程でチップ部品4等を内蔵させる点が主に異なるため、この相違点を中心に説明し、その他の共通する部分については説明を省略する。
具体的にプレス基板9の作製行程i),ii)では、レーザ装置などを用いて、2層目および3層目の絶縁層20に第一のキャビティを、3層目〜5層目の絶縁層20に第二のキャビティをそれぞれ設け、第一のキャビティに銅部材6を、第二のキャビティにチップ部品4を挿入するようにして、配線パターン10が形成された七層分の各絶縁層20を、積層プレス等により加熱加圧しにより接着させる。なお、6層目の絶縁層のうちチップ部品4の実装位置に対応する領域には、チップ部品4を電気的に接続するためのビア7が少なくとも設けられている。
以上、説明したように、本実施形態のIC搭載基板1によれば、多層プリント配線板2の絶縁層20にPTFEが用いられているため、一般的に用いられるガラスエポキシ樹脂に比べて誘電正接が小さく、誘電体損失を抑制することができるため、ミリ波等の高周波信号を扱う機器に好適に使用することができる。
次に、本発明の第三実施形態を図面と共に説明する。
図5は、第三実施形態におけるIC搭載基板の構成を断面視で示す構成図、図6は、その製造方法における主要な行程を断面視で示す行程図である。
図5に示すように、本実施形態のIC搭載基板1は、第一実施形態と比較して、ベアチップ3と多層プリント配線板2との接続方法が主に異なるため、この相違点を中心に説明し、その他の共通する部分については説明を省略する。
また、図6に示すように、本実施形態のIC搭載基板1の製造方法は、第一実施形態の製造方法Aと比較して、プレス基板9の作製行程でキャビティを一箇所のみ設ける点、及びIC搭載基板1の作製行程でフリップチップ接続する点が異なるため、この相違点を中心に説明し、その他の共通する部分については説明を省略する。
このIC搭載基板1の製造方法によれば、導体ワイヤ5を介することなくベアチップ3を多層プリント配線板2に接続するため、ベアチップ3の実装面積を小さくすることができると共に、両者の接続部の長さを必要最小限に抑えることにより、この方法で製造されたIC搭載基板1の電気的特性を向上させることができる。
以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において、様々な態様にて実施することが可能である。
Z=(120π/εeff1/2)/{W/h+1.393+ln(W/h+1.444)} ・・・(1)
但し、εeff=(εr+1)/2+(εr−1)/2(1+12h/W)1/2
に基づいて設定されればよい。例えば、Z=50Ω、εr=3.5、W=300μmである場合、h≒135μmとなるため、各絶縁層20の厚みを約67.5μmとすることが考えられる。
Claims (10)
- 絶縁材からなる絶縁層上に配線パターンが形成されてなるプリント配線板と、ICのベアチップとが電気的に接続されたIC搭載基板であって、
前記絶縁層は、前記配線パターンのうち前記ベアチップが電気的に接続される部位を電極部として、該電極部に対向する直下領域に、少なくとも前記絶縁材に比べて剛性の高い強化材が埋設されていることを特徴とするIC搭載基板。 - 前記絶縁材は、熱可塑性樹脂であることを特徴とする請求項1に記載のIC搭載基板。
- 前記直下領域は、前記電極部に対応して複数設けられていることを特徴とする請求項1または請求項2に記載のIC搭載基板。
- 前記プリント配線板は、前記絶縁層および前記配線パターンが複数積層されてなる多層プリント配線板であることを特徴とする請求項1ないし請求項3のいずれかに記載のIC搭載基板。
- 前記強化材は、複数の前記絶縁層のうち、前記電極部が形成された絶縁層を一層目、該一層目の絶縁層に前記電極部の反対側から積層された絶縁層を二層目として、前記一層目を除き、且つ前記二層目を含む複数の絶縁層に渡って埋設されていることを特徴とする請求項4に記載のIC搭載基板。
- 前記多層プリント配線板は、複数の前記絶縁層のうち、前記一層目の絶縁層の厚みが、他の絶縁層の厚みに比べて小さいことを特徴とする請求項5に記載のIC搭載基板。
- 前記多層プリント配線板は、複数の前記配線パターンが線路パターンとグランドパターンとの組合せからなるマイクロストリップ線路により形成され、
複数の前記絶縁層のうち、前記一層目の絶縁層において前記電極部を含む側の第一面上には前記線路パターン、前記一層目と前記二層目とが重なる第二面上には、前記直下領域に相当する領域にのみ前記グランドパターン、前記二層目の絶縁層において前記一層目に対する反対側の第三面上には前記グランドパターンがそれぞれ形成され、
前記第二面上および前記第三面上のグランドパターンは、前記二層目の絶縁層に設けられたビアを介在して接続されていることを特徴とする請求項5または請求項6に記載のIC搭載基板。 - 前記絶縁材は、前記配線パターンと同じ線膨張係数となるように予め補填材が含まれ、
前記強化材は、前記配線パターンと同じ線膨張係数を有する材質であることを特徴とする請求項1ないし請求項7のいずれかに記載のIC搭載基板。 - 絶縁材からなる絶縁層上に配線パターンが形成されてなるプリント配線板であって、
前記配線パターン上にICのベアチップを電気的に接続するための電極部を備え、
前記絶縁層は、前記電極部に対向する直下領域に、少なくとも前記絶縁材に比べて剛性の高い強化材が埋設されていることを特徴とするプリント配線板。 - 絶縁材からなる絶縁層、及び該絶縁層上に形成された配線パターンが複数積層されてなる多層プリント配線板に、ICのベアチップが搭載されたIC搭載基板の製造方法において、
前記配線パターンのうち、前記ベアチップが電気的に接続される部位を電極部、複数の前記絶縁層のうち、前記電極部が形成された絶縁層を一層目、該一層目の絶縁層に前記電極部の反対側から積層される絶縁層を二層目として、前記一層目を除き、且つ前記二層目を含む複数の絶縁層に渡って、前記電極部に対向する直下領域に貫通孔を形成する第一行程と、
該第一行程により形成された貫通孔に、少なくとも前記絶縁材に比べて剛性の高い強化材を挿入し、前記一層目の絶縁層と、前記二層目を含む複数の絶縁層とを積層する第二行程と、
を行うことを特徴とするIC搭載基板の製造方法。
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DE102010002540A DE102010002540A1 (de) | 2009-03-09 | 2010-03-03 | Platine, IC-Karte mit der Platine und Herstellungsverfahren hierfür |
US12/660,824 US20100226110A1 (en) | 2009-03-09 | 2010-03-04 | Printed wiring board, printed IC board having the printed wiring board, and method of manufacturing the same |
CN201010129308A CN101835343A (zh) | 2009-03-09 | 2010-03-09 | 印刷布线板、包含其的印刷集成电路板及其制造方法 |
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US9006901B2 (en) * | 2013-07-19 | 2015-04-14 | Alpha & Omega Semiconductor, Inc. | Thin power device and preparation method thereof |
WO2015163095A1 (ja) * | 2014-04-23 | 2015-10-29 | 京セラ株式会社 | 電子素子実装用基板および電子装置 |
CN112349695B (zh) * | 2020-09-28 | 2022-04-19 | 中国电子科技集团公司第二十九研究所 | 一种四层布线lcp封装基板、制造方法及多芯片系统级封装结构 |
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