JP2010157700A - 高アスペクト比プラグの充填方法 - Google Patents

高アスペクト比プラグの充填方法 Download PDF

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Publication number
JP2010157700A
JP2010157700A JP2009269279A JP2009269279A JP2010157700A JP 2010157700 A JP2010157700 A JP 2010157700A JP 2009269279 A JP2009269279 A JP 2009269279A JP 2009269279 A JP2009269279 A JP 2009269279A JP 2010157700 A JP2010157700 A JP 2010157700A
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Japan
Prior art keywords
layer
forming
nucleation
silicide
nucleation layer
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JP2009269279A
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English (en)
Japanese (ja)
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JP2010157700A5 (https=
Inventor
Yakov Shor
ショル ヤコヴ
Semeon Altshuler
アルトシューラー セメオン
Maor Rotlain
ロトレイン マオー
Yigal Alon
アロン イガル
Dror Horvitz
ホルヴィッツ ドロア
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Publication of JP2010157700A publication Critical patent/JP2010157700A/ja
Publication of JP2010157700A5 publication Critical patent/JP2010157700A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2009269279A 2008-12-31 2009-11-05 高アスペクト比プラグの充填方法 Pending JP2010157700A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/347,721 US8236691B2 (en) 2008-12-31 2008-12-31 Method of high aspect ratio plug fill

Publications (2)

Publication Number Publication Date
JP2010157700A true JP2010157700A (ja) 2010-07-15
JP2010157700A5 JP2010157700A5 (https=) 2012-12-20

Family

ID=42221054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009269279A Pending JP2010157700A (ja) 2008-12-31 2009-11-05 高アスペクト比プラグの充填方法

Country Status (5)

Country Link
US (1) US8236691B2 (https=)
JP (1) JP2010157700A (https=)
CN (1) CN101770978B (https=)
DE (1) DE102009052393B8 (https=)
TW (1) TWI415218B (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
CN113862634A (zh) * 2012-03-27 2021-12-31 诺发系统公司 钨特征填充
CN104157562A (zh) * 2014-08-26 2014-11-19 上海华虹宏力半导体制造有限公司 半导体结构的形成方法
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9640482B1 (en) * 2016-04-13 2017-05-02 United Microelectronics Corp. Semiconductor device with a contact plug and method of fabricating the same
KR102441431B1 (ko) * 2016-06-06 2022-09-06 어플라이드 머티어리얼스, 인코포레이티드 표면을 갖는 기판을 프로세싱 챔버에 포지셔닝하는 단계를 포함하는 프로세싱 방법
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
KR20250073535A (ko) 2017-08-14 2025-05-27 램 리써치 코포레이션 3차원 수직 nand 워드라인을 위한 금속 충진 프로세스
KR102806630B1 (ko) 2018-05-03 2025-05-12 램 리써치 코포레이션 3d nand 구조체들에 텅스텐 및 다른 금속들을 증착하는 방법
WO2020118100A1 (en) 2018-12-05 2020-06-11 Lam Research Corporation Void free low stress fill
WO2020123987A1 (en) 2018-12-14 2020-06-18 Lam Research Corporation Atomic layer deposition on 3d nand structures
SG11202108725XA (en) 2019-02-13 2021-09-29 Lam Res Corp Tungsten feature fill with inhibition control
WO2020210260A1 (en) 2019-04-11 2020-10-15 Lam Research Corporation High step coverage tungsten deposition
US12237221B2 (en) 2019-05-22 2025-02-25 Lam Research Corporation Nucleation-free tungsten deposition
WO2021030836A1 (en) 2019-08-12 2021-02-18 Lam Research Corporation Tungsten deposition

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136058A (ja) * 1991-11-08 1993-06-01 Nippon Steel Corp スパツタ成膜方法及びスパツタ成膜装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2061119C (en) * 1991-04-19 1998-02-03 Pei-Ing P. Lee Method of depositing conductors in high aspect ratio apertures
JPH08191054A (ja) * 1995-01-10 1996-07-23 Kawasaki Steel Corp 半導体装置及びその製造方法
JPH08213610A (ja) * 1995-02-07 1996-08-20 Sony Corp 電界効果型半導体装置及びその製造方法
US5757879A (en) * 1995-06-07 1998-05-26 International Business Machines Corporation Tungsten absorber for x-ray mask
US6406998B1 (en) * 1996-02-05 2002-06-18 Micron Technology, Inc. Formation of silicided contact by ion implantation
JPH1064848A (ja) * 1996-08-13 1998-03-06 Toshiba Corp 半導体装置の製造装置および製造方法
US5918141A (en) * 1997-06-20 1999-06-29 National Semiconductor Corporation Method of masking silicide deposition utilizing a photoresist mask
US6696746B1 (en) * 1998-04-29 2004-02-24 Micron Technology, Inc. Buried conductors
TW439102B (en) * 1998-12-02 2001-06-07 Nippon Electric Co Field effect transistor and method of manufacturing the same
US6686278B2 (en) * 2001-06-19 2004-02-03 United Microelectronics Corp. Method for forming a plug metal layer
TWI270180B (en) * 2004-06-21 2007-01-01 Powerchip Semiconductor Corp Flash memory cell and manufacturing method thereof
ITMI20070446A1 (it) * 2007-03-06 2008-09-07 St Microelectronics Srl Processo perfabbricare circuiti integrati formati su un substrato seminconduttore e comprendenti strati di tungsteno
US8372744B2 (en) * 2007-04-20 2013-02-12 International Business Machines Corporation Fabricating a contact rhodium structure by electroplating and electroplating composition
KR20090074561A (ko) * 2008-01-02 2009-07-07 주식회사 하이닉스반도체 반도체소자의 컨택 형성방법
US20100065949A1 (en) * 2008-09-17 2010-03-18 Andreas Thies Stacked Semiconductor Chips with Through Substrate Vias

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136058A (ja) * 1991-11-08 1993-06-01 Nippon Steel Corp スパツタ成膜方法及びスパツタ成膜装置

Also Published As

Publication number Publication date
DE102009052393A1 (de) 2010-07-01
TW201029112A (en) 2010-08-01
DE102009052393B4 (de) 2017-11-16
US8236691B2 (en) 2012-08-07
CN101770978A (zh) 2010-07-07
US20100167532A1 (en) 2010-07-01
TWI415218B (zh) 2013-11-11
DE102009052393B8 (de) 2018-02-08
CN101770978B (zh) 2014-04-16

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