JP2010113793A5 - - Google Patents

Download PDF

Info

Publication number
JP2010113793A5
JP2010113793A5 JP2009209072A JP2009209072A JP2010113793A5 JP 2010113793 A5 JP2010113793 A5 JP 2010113793A5 JP 2009209072 A JP2009209072 A JP 2009209072A JP 2009209072 A JP2009209072 A JP 2009209072A JP 2010113793 A5 JP2010113793 A5 JP 2010113793A5
Authority
JP
Japan
Prior art keywords
sram
control signal
circuits
signal group
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009209072A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010113793A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2009209072A priority Critical patent/JP2010113793A/ja
Priority claimed from JP2009209072A external-priority patent/JP2010113793A/ja
Priority to US12/585,495 priority patent/US8164962B2/en
Priority to CN200910204646.0A priority patent/CN101727973B/zh
Publication of JP2010113793A publication Critical patent/JP2010113793A/ja
Publication of JP2010113793A5 publication Critical patent/JP2010113793A5/ja
Pending legal-status Critical Current

Links

JP2009209072A 2008-10-10 2009-09-10 半導体記憶装置 Pending JP2010113793A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009209072A JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置
US12/585,495 US8164962B2 (en) 2008-10-10 2009-09-16 Semiconductor memory apparatus
CN200910204646.0A CN101727973B (zh) 2008-10-10 2009-10-10 半导体存储器装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008264008 2008-10-10
JP2009209072A JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2010113793A JP2010113793A (ja) 2010-05-20
JP2010113793A5 true JP2010113793A5 (enExample) 2012-06-28

Family

ID=42098722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009209072A Pending JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置

Country Status (3)

Country Link
US (1) US8164962B2 (enExample)
JP (1) JP2010113793A (enExample)
CN (1) CN101727973B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5398599B2 (ja) * 2010-03-10 2014-01-29 ルネサスエレクトロニクス株式会社 半導体記憶装置及びそのセル活性化方法
CN102906819B (zh) * 2010-12-16 2016-01-06 株式会社索思未来 半导体存储装置
JP5539916B2 (ja) * 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
EP2681740B1 (en) * 2011-03-04 2016-10-19 Stichting IMEC Nederland Local write and read assist circuitry for memory device
US8958232B2 (en) * 2012-04-02 2015-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for read assist to compensate for weak bit
JP2014041668A (ja) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd 半導体記憶装置及び半導体記憶装置の制御方法
US10008257B2 (en) * 2015-11-20 2018-06-26 Oracle International Corporation Memory bitcell with column select

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0184638B1 (ko) * 1989-02-23 1999-04-15 엔.라이스 머레트 세그먼트 비트 라인 스태틱 랜덤 액세스 메모리 구조물
JPH06119784A (ja) 1992-10-07 1994-04-28 Hitachi Ltd センスアンプとそれを用いたｓｒａｍとマイクロプロセッサ
JPH103790A (ja) * 1996-06-18 1998-01-06 Mitsubishi Electric Corp 半導体記憶装置
JPH10162580A (ja) * 1996-11-29 1998-06-19 Mitsubishi Electric Corp スタティック型半導体記憶装置とその動作方法
US6011711A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. SRAM cell with p-channel pull-up sources connected to bit lines
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
US7289354B2 (en) * 2005-07-28 2007-10-30 Texas Instruments Incorporated Memory array with a delayed wordline boost

Similar Documents

Publication Publication Date Title
JP2010267373A5 (enExample)
JP2010113793A5 (enExample)
KR102023487B1 (ko) 오토 리프레쉬 커맨드를 사용하지 않고 리프레쉬를 수행할 수 있는 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
JP2009510562A5 (enExample)
TWI256647B (en) Multi-port memory device with stacked banks
JP2006523360A5 (enExample)
JP2007059026A5 (enExample)
WO2009029737A3 (en) Dynamic random access memory having junction field effect transistor cell access device
WO2008121556A3 (en) Semi-shared sense amplifier and global read line architecture
JP2010146678A5 (enExample)
KR100890381B1 (ko) 반도체 메모리 소자
JP2011014195A5 (enExample)
CN107086046B (zh) 存储器件
JP2006155710A5 (enExample)
US20140050039A1 (en) Semiconductor memory devices
US20140016418A1 (en) Semiconductor memory device
JP2013041657A5 (enExample)
JP2013041657A (ja) 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ
JP2010010369A5 (enExample)
TW464863B (en) Semiconductor memory
JP2008541333A5 (enExample)
TW200614236A (en) Semiconductor memory device for low power condition
KR101090410B1 (ko) 반도체 메모리 장치
JP2008503029A5 (enExample)
US7924595B2 (en) High-density semiconductor device