JP2008541333A5 - - Google Patents

Download PDF

Info

Publication number
JP2008541333A5
JP2008541333A5 JP2008512275A JP2008512275A JP2008541333A5 JP 2008541333 A5 JP2008541333 A5 JP 2008541333A5 JP 2008512275 A JP2008512275 A JP 2008512275A JP 2008512275 A JP2008512275 A JP 2008512275A JP 2008541333 A5 JP2008541333 A5 JP 2008541333A5
Authority
JP
Japan
Prior art keywords
memory cell
terminal
data value
select gate
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008512275A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008541333A (ja
Filing date
Publication date
Priority claimed from US11/132,457 external-priority patent/US7295487B2/en
Application filed filed Critical
Publication of JP2008541333A publication Critical patent/JP2008541333A/ja
Publication of JP2008541333A5 publication Critical patent/JP2008541333A5/ja
Pending legal-status Critical Current

Links

JP2008512275A 2005-05-19 2006-03-29 記憶回路及びその方法 Pending JP2008541333A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/132,457 US7295487B2 (en) 2005-05-19 2005-05-19 Storage circuit and method therefor
PCT/US2006/011560 WO2006127117A2 (en) 2005-05-19 2006-03-29 Storage circuit and method therefor

Publications (2)

Publication Number Publication Date
JP2008541333A JP2008541333A (ja) 2008-11-20
JP2008541333A5 true JP2008541333A5 (enExample) 2009-05-14

Family

ID=37448177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008512275A Pending JP2008541333A (ja) 2005-05-19 2006-03-29 記憶回路及びその方法

Country Status (5)

Country Link
US (2) US7295487B2 (enExample)
JP (1) JP2008541333A (enExample)
KR (1) KR20080009129A (enExample)
TW (1) TWI336476B (enExample)
WO (1) WO2006127117A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI455148B (zh) * 2010-12-13 2014-10-01 Vanguard Int Semiconduct Corp 用以存取多埠輸入讀寫事件的積體裝置
CN103597545B (zh) * 2011-06-09 2016-10-19 株式会社半导体能源研究所 高速缓冲存储器及其驱动方法
JP6012263B2 (ja) 2011-06-09 2016-10-25 株式会社半導体エネルギー研究所 半導体記憶装置
US9208859B1 (en) 2014-08-22 2015-12-08 Globalfoundries Inc. Low power static random access memory (SRAM) read data path
US9786359B2 (en) * 2016-01-29 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Static random access memory (SRAM) tracking cells and methods of forming same
US9934846B1 (en) 2017-03-01 2018-04-03 Nxp Usa, Inc. Memory circuit and method for increased write margin
US9940996B1 (en) 2017-03-01 2018-04-10 Nxp Usa, Inc. Memory circuit having increased write margin and method therefor
US11482276B2 (en) * 2020-10-30 2022-10-25 Taiwan Semiconductor Manufacturing Company Limited System and method for read speed improvement in 3T DRAM
US12361985B2 (en) * 2022-09-16 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06215580A (ja) * 1993-01-18 1994-08-05 Mitsubishi Electric Corp メモリセル回路
JPH08161890A (ja) * 1994-12-02 1996-06-21 Fujitsu Ltd メモリセル回路及びマルチポート半導体記憶装置
KR100431478B1 (ko) * 1995-07-27 2004-08-25 텍사스 인스트루먼츠 인코포레이티드 고밀도2포트메모리셀
US5854761A (en) 1997-06-26 1998-12-29 Sun Microsystems, Inc. Cache memory array which stores two-way set associative data
US6282143B1 (en) 1998-05-26 2001-08-28 Hewlett-Packard Company Multi-port static random access memory design for column interleaved arrays
US6804143B1 (en) * 2003-04-02 2004-10-12 Cogent Chipware Inc. Write-assisted SRAM bit cell
JP4330396B2 (ja) * 2003-07-24 2009-09-16 株式会社ルネサステクノロジ 半導体記憶装置
JP4010995B2 (ja) * 2003-07-31 2007-11-21 Ｎｅｃエレクトロニクス株式会社 半導体メモリ及びそのリファレンス電位発生方法

Similar Documents

Publication Publication Date Title
TW200710661A (en) Memory controller interface for micro-tiled memory access
CN107924693A (zh) 多区块系统中的可编程的片上端接定时
TW200710662A (en) Micro-tile memory interfaces
TW200605080A (en) Method of reading NAND memory to compensate for coupling between storage elements
US8988933B2 (en) Semiconductor memory device and driving method of the same
US20090157983A1 (en) Method and apparatus for using a variable page length in a memory
JP2010510615A5 (enExample)
TW200703625A (en) Semiconductor storage device
US9001546B2 (en) 3D structure for advanced SRAM design to avoid half-selected issue
JP2007272938A5 (enExample)
WO2007126830A3 (en) Memory array having a programmable word length, and method of operating same
JP2005044456A5 (enExample)
CN106155926B (zh) 存储器及存储器的数据交互方法
CN104599700B (zh) 高密度存储器结构
ATE475180T1 (de) Registerlesen für flüchtigen speicher
DE602006016041D1 (de) Magnetischer Direktzugriffsspeicherarray mit Bit-/Wortleitungen für gemeinsame Schreibauswahl- und Leseoperationen
US9076512B2 (en) Synchronous nonvolatile memory device and memory system supporting consecutive division addressing DRAM protocol
JP2008541333A5 (enExample)
JP2005531876A5 (enExample)
ATE475181T1 (de) Konfigurierbarer mvram und konfigurationsverfahren
JP2006155710A5 (enExample)
WO2005124558A3 (en) Method and system for optimizing the number of word line segments in a segmented mram array
TW200518103A (en) Method and system for enhancing the endurance of memory cells
TW200636721A (en) Memory device with pre-fetch circuit and pre-fetch method
WO2005029500A3 (en) Eeprom architecture and programming protocol