KR20080009129A - 저장 회로 및 방법 - Google Patents

저장 회로 및 방법 Download PDF

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Publication number
KR20080009129A
KR20080009129A KR1020077026821A KR20077026821A KR20080009129A KR 20080009129 A KR20080009129 A KR 20080009129A KR 1020077026821 A KR1020077026821 A KR 1020077026821A KR 20077026821 A KR20077026821 A KR 20077026821A KR 20080009129 A KR20080009129 A KR 20080009129A
Authority
KR
South Korea
Prior art keywords
storage cell
terminal
read
coupled
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020077026821A
Other languages
English (en)
Korean (ko)
Inventor
라빈드라라 라마라주
프라샨트 유. 켄카레
제레미야 티. 씨. 팔머
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20080009129A publication Critical patent/KR20080009129A/ko
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020077026821A 2005-05-19 2006-03-29 저장 회로 및 방법 Ceased KR20080009129A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/132,457 2005-05-19
US11/132,457 US7295487B2 (en) 2005-05-19 2005-05-19 Storage circuit and method therefor

Publications (1)

Publication Number Publication Date
KR20080009129A true KR20080009129A (ko) 2008-01-24

Family

ID=37448177

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020077026821A Ceased KR20080009129A (ko) 2005-05-19 2006-03-29 저장 회로 및 방법

Country Status (5)

Country Link
US (2) US7295487B2 (enExample)
JP (1) JP2008541333A (enExample)
KR (1) KR20080009129A (enExample)
TW (1) TWI336476B (enExample)
WO (1) WO2006127117A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8908406B2 (en) 2011-06-09 2014-12-09 Semiconductor Energy Laboratory Co., Ltd. Cache memory and method for driving the same

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI455148B (zh) * 2010-12-13 2014-10-01 Vanguard Int Semiconduct Corp 用以存取多埠輸入讀寫事件的積體裝置
JP6012263B2 (ja) 2011-06-09 2016-10-25 株式会社半導体エネルギー研究所 半導体記憶装置
US9208859B1 (en) 2014-08-22 2015-12-08 Globalfoundries Inc. Low power static random access memory (SRAM) read data path
US9786359B2 (en) * 2016-01-29 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Static random access memory (SRAM) tracking cells and methods of forming same
US9934846B1 (en) 2017-03-01 2018-04-03 Nxp Usa, Inc. Memory circuit and method for increased write margin
US9940996B1 (en) 2017-03-01 2018-04-10 Nxp Usa, Inc. Memory circuit having increased write margin and method therefor
US11482276B2 (en) * 2020-10-30 2022-10-25 Taiwan Semiconductor Manufacturing Company Limited System and method for read speed improvement in 3T DRAM
US12361985B2 (en) * 2022-09-16 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06215580A (ja) * 1993-01-18 1994-08-05 Mitsubishi Electric Corp メモリセル回路
JPH08161890A (ja) * 1994-12-02 1996-06-21 Fujitsu Ltd メモリセル回路及びマルチポート半導体記憶装置
KR100431478B1 (ko) * 1995-07-27 2004-08-25 텍사스 인스트루먼츠 인코포레이티드 고밀도2포트메모리셀
US5854761A (en) 1997-06-26 1998-12-29 Sun Microsystems, Inc. Cache memory array which stores two-way set associative data
US6282143B1 (en) 1998-05-26 2001-08-28 Hewlett-Packard Company Multi-port static random access memory design for column interleaved arrays
US6804143B1 (en) * 2003-04-02 2004-10-12 Cogent Chipware Inc. Write-assisted SRAM bit cell
JP4330396B2 (ja) * 2003-07-24 2009-09-16 株式会社ルネサステクノロジ 半導体記憶装置
JP4010995B2 (ja) * 2003-07-31 2007-11-21 Ｎｅｃエレクトロニクス株式会社 半導体メモリ及びそのリファレンス電位発生方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8908406B2 (en) 2011-06-09 2014-12-09 Semiconductor Energy Laboratory Co., Ltd. Cache memory and method for driving the same

Also Published As

Publication number Publication date
US20060262633A1 (en) 2006-11-23
US20080022047A1 (en) 2008-01-24
WO2006127117A3 (en) 2009-05-07
US7525867B2 (en) 2009-04-28
TWI336476B (en) 2011-01-21
US7295487B2 (en) 2007-11-13
TW200643967A (en) 2006-12-16
WO2006127117A2 (en) 2006-11-30
JP2008541333A (ja) 2008-11-20

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PA0105 International application

Patent event date: 20071119

Patent event code: PA01051R01D

Comment text: International Patent Application

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PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20110329

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
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Comment text: Notification of reason for refusal

Patent event date: 20120827

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20121101

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20120827

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I