CN101727973B - 半导体存储器装置 - Google Patents

半导体存储器装置 Download PDF

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Publication number
CN101727973B
CN101727973B CN200910204646.0A CN200910204646A CN101727973B CN 101727973 B CN101727973 B CN 101727973B CN 200910204646 A CN200910204646 A CN 200910204646A CN 101727973 B CN101727973 B CN 101727973B
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CN
China
Prior art keywords
sram cell
sram
circuit
semiconductor memory
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN200910204646.0A
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English (en)
Chinese (zh)
Other versions
CN101727973A (zh
Inventor
武田晃一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN101727973A publication Critical patent/CN101727973A/zh
Application granted granted Critical
Publication of CN101727973B publication Critical patent/CN101727973B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
CN200910204646.0A 2008-10-10 2009-10-10 半导体存储器装置 Expired - Fee Related CN101727973B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008-264008 2008-10-10
JP2008264008 2008-10-10
JP2009209072A JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置
JP2009-209072 2009-09-10

Publications (2)

Publication Number Publication Date
CN101727973A CN101727973A (zh) 2010-06-09
CN101727973B true CN101727973B (zh) 2014-06-25

Family

ID=42098722

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200910204646.0A Expired - Fee Related CN101727973B (zh) 2008-10-10 2009-10-10 半导体存储器装置

Country Status (3)

Country Link
US (1) US8164962B2 (enExample)
JP (1) JP2010113793A (enExample)
CN (1) CN101727973B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5398599B2 (ja) * 2010-03-10 2014-01-29 ルネサスエレクトロニクス株式会社 半導体記憶装置及びそのセル活性化方法
CN102906819B (zh) * 2010-12-16 2016-01-06 株式会社索思未来 半导体存储装置
WO2012119988A1 (en) * 2011-03-04 2012-09-13 Imec Local write and read assist circuitry for memory device
JP5539916B2 (ja) * 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US8958232B2 (en) * 2012-04-02 2015-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for read assist to compensate for weak bit
JP2014041668A (ja) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd 半導体記憶装置及び半導体記憶装置の制御方法
US10008257B2 (en) * 2015-11-20 2018-06-26 Oracle International Corporation Memory bitcell with column select

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0184638B1 (ko) * 1989-02-23 1999-04-15 엔.라이스 머레트 세그먼트 비트 라인 스태틱 랜덤 액세스 메모리 구조물
JPH06119784A (ja) 1992-10-07 1994-04-28 Hitachi Ltd センスアンプとそれを用いたｓｒａｍとマイクロプロセッサ
JPH103790A (ja) * 1996-06-18 1998-01-06 Mitsubishi Electric Corp 半導体記憶装置
JPH10162580A (ja) * 1996-11-29 1998-06-19 Mitsubishi Electric Corp スタティック型半導体記憶装置とその動作方法
US6011711A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. SRAM cell with p-channel pull-up sources connected to bit lines
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
US7289354B2 (en) * 2005-07-28 2007-10-30 Texas Instruments Incorporated Memory array with a delayed wordline boost

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A low-power SRAM using hierarchical bit line and local sense amplifiers;Byung-Do Yang and Lee-Sup Kim;《IEEE JOURNAL OF SOLID-STATE CIRCUITS 》;20050630;第40卷(第6期);第1366-1376页 *
Byung-Do Yang and Lee-Sup Kim.A low-power SRAM using hierarchical bit line and local sense amplifiers.《IEEE JOURNAL OF SOLID-STATE CIRCUITS 》.2005,第40卷(第6期),1366-1376.

Also Published As

Publication number Publication date
JP2010113793A (ja) 2010-05-20
CN101727973A (zh) 2010-06-09
US20100091590A1 (en) 2010-04-15
US8164962B2 (en) 2012-04-24

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
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GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140625

Termination date: 20161010