JP2010113793A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
JP2010113793A
JP2010113793A JP2009209072A JP2009209072A JP2010113793A JP 2010113793 A JP2010113793 A JP 2010113793A JP 2009209072 A JP2009209072 A JP 2009209072A JP 2009209072 A JP2009209072 A JP 2009209072A JP 2010113793 A JP2010113793 A JP 2010113793A
Authority
JP
Japan
Prior art keywords
sram
sram cell
circuit
bit line
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009209072A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010113793A5 (enExample
Inventor
Koichi Takeda
晃一 武田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009209072A priority Critical patent/JP2010113793A/ja
Priority to US12/585,495 priority patent/US8164962B2/en
Priority to CN200910204646.0A priority patent/CN101727973B/zh
Publication of JP2010113793A publication Critical patent/JP2010113793A/ja
Publication of JP2010113793A5 publication Critical patent/JP2010113793A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
JP2009209072A 2008-10-10 2009-09-10 半導体記憶装置 Pending JP2010113793A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009209072A JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置
US12/585,495 US8164962B2 (en) 2008-10-10 2009-09-16 Semiconductor memory apparatus
CN200910204646.0A CN101727973B (zh) 2008-10-10 2009-10-10 半导体存储器装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008264008 2008-10-10
JP2009209072A JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2010113793A true JP2010113793A (ja) 2010-05-20
JP2010113793A5 JP2010113793A5 (enExample) 2012-06-28

Family

ID=42098722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009209072A Pending JP2010113793A (ja) 2008-10-10 2009-09-10 半導体記憶装置

Country Status (3)

Country Link
US (1) US8164962B2 (enExample)
JP (1) JP2010113793A (enExample)
CN (1) CN101727973B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012081159A1 (ja) * 2010-12-16 2012-06-21 パナソニック株式会社 半導体記憶装置
JP2014510359A (ja) * 2011-03-04 2014-04-24 スティヒティング・イメック・ネーデルラント メモリ装置用ローカル書き込み及び読み出し回路構成

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5398599B2 (ja) * 2010-03-10 2014-01-29 ルネサスエレクトロニクス株式会社 半導体記憶装置及びそのセル活性化方法
JP5539916B2 (ja) * 2011-03-04 2014-07-02 ルネサスエレクトロニクス株式会社 半導体装置
US8958232B2 (en) * 2012-04-02 2015-02-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for read assist to compensate for weak bit
JP2014041668A (ja) * 2012-08-21 2014-03-06 Fujitsu Semiconductor Ltd 半導体記憶装置及び半導体記憶装置の制御方法
US10008257B2 (en) * 2015-11-20 2018-06-26 Oracle International Corporation Memory bitcell with column select

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH031395A (ja) * 1989-02-23 1991-01-08 Texas Instr Inc <Ti> 静止形ランダムアクセス・メモリ
JPH103790A (ja) * 1996-06-18 1998-01-06 Mitsubishi Electric Corp 半導体記憶装置
JPH10162580A (ja) * 1996-11-29 1998-06-19 Mitsubishi Electric Corp スタティック型半導体記憶装置とその動作方法
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06119784A (ja) 1992-10-07 1994-04-28 Hitachi Ltd センスアンプとそれを用いたｓｒａｍとマイクロプロセッサ
US6011711A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. SRAM cell with p-channel pull-up sources connected to bit lines
US7289354B2 (en) * 2005-07-28 2007-10-30 Texas Instruments Incorporated Memory array with a delayed wordline boost

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH031395A (ja) * 1989-02-23 1991-01-08 Texas Instr Inc <Ti> 静止形ランダムアクセス・メモリ
JPH103790A (ja) * 1996-06-18 1998-01-06 Mitsubishi Electric Corp 半導体記憶装置
JPH10162580A (ja) * 1996-11-29 1998-06-19 Mitsubishi Electric Corp スタティック型半導体記憶装置とその動作方法
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012081159A1 (ja) * 2010-12-16 2012-06-21 パナソニック株式会社 半導体記憶装置
US8830774B2 (en) 2010-12-16 2014-09-09 Panasonic Corporation Semiconductor memory device
JP2014510359A (ja) * 2011-03-04 2014-04-24 スティヒティング・イメック・ネーデルラント メモリ装置用ローカル書き込み及び読み出し回路構成

Also Published As

Publication number Publication date
CN101727973B (zh) 2014-06-25
CN101727973A (zh) 2010-06-09
US20100091590A1 (en) 2010-04-15
US8164962B2 (en) 2012-04-24

Similar Documents

Publication Publication Date Title
US20210134371A1 (en) Sram memory having subarrays with common io block
US7471590B2 (en) Write control circuitry and method for a memory array configured with multiple memory subarrays
JPS621183A (ja) ダイナミツク型ｒａｍ
JP2010113793A (ja) 半導体記憶装置
CN102859600A (zh) 用于通过选择性偏置来降低高容量存储器中存储器阵列漏电的系统和方法
US6765817B2 (en) Semiconductor memory
CN105097012B (zh) 存储器结构
JP2011170918A (ja) 半導体記憶装置
US7924605B2 (en) Semiconductor memory device
JP4954954B2 (ja) 半導体記憶装置
JP2005135461A (ja) 階層ワード線方式の半導体記憶装置と、それに使用されるサブワードドライバ回路
JP5398599B2 (ja) 半導体記憶装置及びそのセル活性化方法
JP5306125B2 (ja) 半導体記憶装置
US7489581B2 (en) Semiconductor memory
KR100769492B1 (ko) 반도체 집적 회로
JP2008198243A (ja) 半導体記憶装置
JP4965844B2 (ja) 半導体メモリ装置
JP3290315B2 (ja) 半導体記憶装置
JP2006269023A (ja) 半導体記憶装置
JP5073541B2 (ja) 半導体記憶装置
JP2006202458A (ja) 表示装置のメモリ構造及びそれに用いるメモリ記録方法。
KR20080047157A (ko) 반도체 메모리 소자의 센스앰프 전원 공급 회로
JPH10200073A (ja) 半導体装置
JPWO2009041471A1 (ja) 半導体記憶装置
JP2009064509A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120516

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120516

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130305

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130502

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130723

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140107

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140624