JP2013041657A5 - - Google Patents

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Publication number
JP2013041657A5
JP2013041657A5 JP2012132108A JP2012132108A JP2013041657A5 JP 2013041657 A5 JP2013041657 A5 JP 2013041657A5 JP 2012132108 A JP2012132108 A JP 2012132108A JP 2012132108 A JP2012132108 A JP 2012132108A JP 2013041657 A5 JP2013041657 A5 JP 2013041657A5
Authority
JP
Japan
Prior art keywords
random access
access memory
memory controller
sense amplifier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012132108A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013041657A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JP2013041657A publication Critical patent/JP2013041657A/ja
Publication of JP2013041657A5 publication Critical patent/JP2013041657A5/ja
Pending legal-status Critical Current

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JP2012132108A 2011-06-22 2012-06-11 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ Pending JP2013041657A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161499959P 2011-06-22 2011-06-22
US61/499,959 2011-06-22

Publications (2)

Publication Number Publication Date
JP2013041657A JP2013041657A (ja) 2013-02-28
JP2013041657A5 true JP2013041657A5 (enExample) 2015-07-16

Family

ID=47361722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012132108A Pending JP2013041657A (ja) 2011-06-22 2012-06-11 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ

Country Status (3)

Country Link
US (1) US8913420B2 (enExample)
JP (1) JP2013041657A (enExample)
KR (1) KR20130000361A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11011238B2 (en) * 2018-06-28 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Floating data line circuits and methods
US10705984B1 (en) * 2018-09-26 2020-07-07 Cadence Design Systems, Inc. High-speed low VT drift receiver
US10978139B2 (en) * 2019-06-04 2021-04-13 Qualcomm Incorporated Dual-mode high-bandwidth SRAM with self-timed clock circuit
US12159664B2 (en) * 2019-10-14 2024-12-03 Arm Limited Concurrent memory access operations

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136991A (ja) * 1983-12-26 1985-07-20 Matsushita Electric Ind Co Ltd 半導体メモリ
JP3112117B2 (ja) * 1992-04-17 2000-11-27 松下電器産業株式会社 差動伝送回路
JP3560266B2 (ja) * 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
JPH1166858A (ja) * 1997-08-12 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
JP2002230980A (ja) * 2001-01-31 2002-08-16 Mitsubishi Electric Corp 半導体記憶装置
US6456521B1 (en) * 2001-03-21 2002-09-24 International Business Machines Corporation Hierarchical bitline DRAM architecture system
US6631093B2 (en) * 2001-06-29 2003-10-07 Intel Corporation Low power precharge scheme for memory bit lines
US6707707B2 (en) * 2001-12-21 2004-03-16 Micron Technology, Inc. SRAM power-up system and method
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same
US8027218B2 (en) * 2006-10-13 2011-09-27 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
JP5178182B2 (ja) * 2007-12-25 2013-04-10 株式会社東芝 半導体記憶装置
US7843725B2 (en) * 2008-06-11 2010-11-30 Micron Technology, Inc. M+L bit read column architecture for M bit memory cells
US20110149667A1 (en) * 2009-12-23 2011-06-23 Fatih Hamzaoglu Reduced area memory array by using sense amplifier as write driver

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