JP2013041657A - 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ - Google Patents

共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ Download PDF

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Publication number
JP2013041657A
JP2013041657A JP2012132108A JP2012132108A JP2013041657A JP 2013041657 A JP2013041657 A JP 2013041657A JP 2012132108 A JP2012132108 A JP 2012132108A JP 2012132108 A JP2012132108 A JP 2012132108A JP 2013041657 A JP2013041657 A JP 2013041657A
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JP
Japan
Prior art keywords
random access
access memory
data
column
circuit
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Pending
Application number
JP2012132108A
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English (en)
Japanese (ja)
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JP2013041657A5 (enExample
Inventor
Yanni Meny
ヤニ メニー
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Marvell Israel MISL Ltd
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Marvell Israel MISL Ltd
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Publication date
Application filed by Marvell Israel MISL Ltd filed Critical Marvell Israel MISL Ltd
Publication of JP2013041657A publication Critical patent/JP2013041657A/ja
Publication of JP2013041657A5 publication Critical patent/JP2013041657A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
JP2012132108A 2011-06-22 2012-06-11 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ Pending JP2013041657A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161499959P 2011-06-22 2011-06-22
US61/499,959 2011-06-22

Publications (2)

Publication Number Publication Date
JP2013041657A true JP2013041657A (ja) 2013-02-28
JP2013041657A5 JP2013041657A5 (enExample) 2015-07-16

Family

ID=47361722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012132108A Pending JP2013041657A (ja) 2011-06-22 2012-06-11 共通の列マルチプレクサ及びセンスアンプハードウェアを有するランダムアクセスメモリコントローラ

Country Status (3)

Country Link
US (1) US8913420B2 (enExample)
JP (1) JP2013041657A (enExample)
KR (1) KR20130000361A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11011238B2 (en) * 2018-06-28 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Floating data line circuits and methods
US10705984B1 (en) * 2018-09-26 2020-07-07 Cadence Design Systems, Inc. High-speed low VT drift receiver
US10978139B2 (en) * 2019-06-04 2021-04-13 Qualcomm Incorporated Dual-mode high-bandwidth SRAM with self-timed clock circuit
US12159664B2 (en) * 2019-10-14 2024-12-03 Arm Limited Concurrent memory access operations

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136991A (ja) * 1983-12-26 1985-07-20 Matsushita Electric Ind Co Ltd 半導体メモリ
JPH05298886A (ja) * 1992-04-17 1993-11-12 Matsushita Electric Ind Co Ltd 差動伝送回路
JPH09128970A (ja) * 1995-08-31 1997-05-16 Hitachi Ltd 半導体メモリ装置及び半導体データ処理装置
JPH1166858A (ja) * 1997-08-12 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
JP2002230980A (ja) * 2001-01-31 2002-08-16 Mitsubishi Electric Corp 半導体記憶装置
US20020136072A1 (en) * 2001-03-21 2002-09-26 International Business Machines Corporation Hierarchical bitline dram architecture system
JP2009157959A (ja) * 2007-12-25 2009-07-16 Toshiba Corp 半導体記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6631093B2 (en) * 2001-06-29 2003-10-07 Intel Corporation Low power precharge scheme for memory bit lines
US6707707B2 (en) * 2001-12-21 2004-03-16 Micron Technology, Inc. SRAM power-up system and method
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same
US8027218B2 (en) * 2006-10-13 2011-09-27 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
US7843725B2 (en) * 2008-06-11 2010-11-30 Micron Technology, Inc. M+L bit read column architecture for M bit memory cells
US20110149667A1 (en) * 2009-12-23 2011-06-23 Fatih Hamzaoglu Reduced area memory array by using sense amplifier as write driver

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136991A (ja) * 1983-12-26 1985-07-20 Matsushita Electric Ind Co Ltd 半導体メモリ
JPH05298886A (ja) * 1992-04-17 1993-11-12 Matsushita Electric Ind Co Ltd 差動伝送回路
JPH09128970A (ja) * 1995-08-31 1997-05-16 Hitachi Ltd 半導体メモリ装置及び半導体データ処理装置
JPH1166858A (ja) * 1997-08-12 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
JP2002230980A (ja) * 2001-01-31 2002-08-16 Mitsubishi Electric Corp 半導体記憶装置
US20020136072A1 (en) * 2001-03-21 2002-09-26 International Business Machines Corporation Hierarchical bitline dram architecture system
JP2009157959A (ja) * 2007-12-25 2009-07-16 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
KR20130000361A (ko) 2013-01-02
US20120327703A1 (en) 2012-12-27
US8913420B2 (en) 2014-12-16

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