JP2009519524A - データ伝送バスにアクセスする方法、対応する装置およびシステム - Google Patents

データ伝送バスにアクセスする方法、対応する装置およびシステム Download PDF

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Publication number
JP2009519524A
JP2009519524A JP2008544948A JP2008544948A JP2009519524A JP 2009519524 A JP2009519524 A JP 2009519524A JP 2008544948 A JP2008544948 A JP 2008544948A JP 2008544948 A JP2008544948 A JP 2008544948A JP 2009519524 A JP2009519524 A JP 2009519524A
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JP
Japan
Prior art keywords
bus
access
master
peripheral device
master peripheral
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2008544948A
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English (en)
Japanese (ja)
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JP2009519524A5 (de
Inventor
ドーレ ルノー
ジャンヌ リュドヴィック
フォンテーヌ パトリック
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Thomson Licensing SAS
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Thomson Licensing SAS
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Publication of JP2009519524A publication Critical patent/JP2009519524A/ja
Publication of JP2009519524A5 publication Critical patent/JP2009519524A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP2008544948A 2005-12-14 2006-12-01 データ伝送バスにアクセスする方法、対応する装置およびシステム Pending JP2009519524A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0553872A FR2894696A1 (fr) 2005-12-14 2005-12-14 Procede d'acces a un bus de transmission de donnees, dispositif et systeme correspondant
PCT/EP2006/069181 WO2007068606A1 (fr) 2005-12-14 2006-12-01 Procede d'acces a un bus de transmission de donnees, dispositif et systeme correspondant.

Publications (2)

Publication Number Publication Date
JP2009519524A true JP2009519524A (ja) 2009-05-14
JP2009519524A5 JP2009519524A5 (de) 2009-12-10

Family

ID=36889282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008544948A Pending JP2009519524A (ja) 2005-12-14 2006-12-01 データ伝送バスにアクセスする方法、対応する装置およびシステム

Country Status (7)

Country Link
US (1) US20100122000A1 (de)
EP (1) EP1960891A1 (de)
JP (1) JP2009519524A (de)
KR (1) KR20080080538A (de)
CN (1) CN101331469B (de)
FR (1) FR2894696A1 (de)
WO (1) WO2007068606A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014138362A (ja) * 2013-01-18 2014-07-28 Nippon Telegr & Teleph Corp <Ntt> 信号受信回路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI494944B (zh) * 2013-10-25 2015-08-01 Phison Electronics Corp 記憶體模組偵測方法、記憶體控制電路單元及儲存裝置
CN106610906A (zh) * 2015-10-27 2017-05-03 深圳市中兴微电子技术有限公司 一种数据访问方法及总线
US9965410B2 (en) 2016-01-21 2018-05-08 Qualcomm Incorporated Priority-based data communication over multiple communication buses

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201054A (ja) * 1989-12-28 1991-09-02 Hitachi Ltd 共通バス制御方法及びその制御装置並びにマスタ装置と計算機システム
JPH06195313A (ja) * 1992-12-25 1994-07-15 Hitachi Ltd コンピュータシステムおよびそれに適した集積回路並びに要求選択回路
JPH07244634A (ja) * 1994-03-03 1995-09-19 Hitachi Ltd 外部記憶制御装置およびバス切り替え制御方法
JP2001195353A (ja) * 2000-01-06 2001-07-19 Rohm Co Ltd Ｄｍａ転送システム
JP2002123484A (ja) * 2000-09-08 2002-04-26 Texas Instruments Inc バス・システム用の即時許可バス・アービタ
JP2002251370A (ja) * 2001-02-21 2002-09-06 Noritsu Koki Co Ltd 要求調停方法、要求調停装置、メモリ装置、および写真処理システム
JP2002278922A (ja) * 2001-03-16 2002-09-27 Ricoh Co Ltd コンピュータバスシステム
JP2002312309A (ja) * 2001-04-09 2002-10-25 Nec Eng Ltd 調停回路及び調停方法
JP2002318782A (ja) * 2001-04-20 2002-10-31 Nec Corp バスシステム
JP2003256358A (ja) * 2002-02-28 2003-09-12 Sony Corp アービタ装置及び方法、並びに、リソース共有システム
JP2003348097A (ja) * 2002-05-29 2003-12-05 Hitachi Ulsi Systems Co Ltd 無線ｌａｎ装置
JP2005071049A (ja) * 2003-08-22 2005-03-17 Murata Mach Ltd データ転送制御装置

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE445861B (sv) * 1984-12-12 1986-07-21 Ellemtel Utvecklings Ab Prioritetsfordelningsanordning for datorer
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
DE69030640T2 (de) * 1989-11-03 1997-11-06 Compaq Computer Corp Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5862355A (en) * 1996-09-12 1999-01-19 Telxon Corporation Method and apparatus for overriding bus prioritization scheme
US5925118A (en) * 1996-10-11 1999-07-20 International Business Machines Corporation Methods and architectures for overlapped read and write operations
US5884051A (en) * 1997-06-13 1999-03-16 International Business Machines Corporation System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities
GB2337138B (en) * 1998-01-30 2002-12-18 * Sgs-Thomson Microelectronics Limited Arbitration
US6073132A (en) * 1998-03-27 2000-06-06 Lsi Logic Corporation Priority arbiter with shifting sequential priority scheme
US6745243B2 (en) * 1998-06-30 2004-06-01 Nortel Networks Limited Method and apparatus for network caching and load balancing
US6490642B1 (en) * 1999-08-12 2002-12-03 Mips Technologies, Inc. Locked read/write on separate address/data bus using write barrier
US6772254B2 (en) * 2000-06-21 2004-08-03 International Business Machines Corporation Multi-master computer system with overlapped read and write operations and scalable address pipelining
US6587905B1 (en) * 2000-06-29 2003-07-01 International Business Machines Corporation Dynamic data bus allocation
US6745273B1 (en) * 2001-01-12 2004-06-01 Lsi Logic Corporation Automatic deadlock prevention via arbitration switching
JP3791005B2 (ja) * 2001-11-20 2006-06-28 日本電気株式会社 バスアクセス調停装置及びバスアクセス調停方法
US6931470B2 (en) * 2002-02-11 2005-08-16 Motorola, Inc. Dual access serial peripheral interface
US20030229743A1 (en) * 2002-06-05 2003-12-11 Brown Andrew C. Methods and structure for improved fairness bus arbitration
US7107365B1 (en) * 2002-06-25 2006-09-12 Cypress Semiconductor Corp. Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
KR101089324B1 (ko) * 2004-02-20 2011-12-02 삼성전자주식회사 복수의 마스터들을 포함하는 서브 시스템을 개방형 코어프로토콜을 기반으로 하는 버스에 연결하기 위한 버스시스템
US8478921B2 (en) 2004-03-31 2013-07-02 Silicon Laboratories, Inc. Communication apparatus implementing time domain isolation with restricted bus access
US20060026329A1 (en) * 2004-07-30 2006-02-02 Yu James K System and method for an arbiter rewind
JP2006172256A (ja) * 2004-12-17 2006-06-29 Renesas Technology Corp 情報処理装置
GB2426604B (en) * 2005-05-26 2010-07-14 Advanced Risc Mach Ltd Interconnect logic for a data processing apparatus
US7467245B2 (en) * 2005-07-22 2008-12-16 Cisco Technology, Inc. PCI arbiter
US7395361B2 (en) * 2005-08-19 2008-07-01 Qualcomm Incorporated Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03201054A (ja) * 1989-12-28 1991-09-02 Hitachi Ltd 共通バス制御方法及びその制御装置並びにマスタ装置と計算機システム
JPH06195313A (ja) * 1992-12-25 1994-07-15 Hitachi Ltd コンピュータシステムおよびそれに適した集積回路並びに要求選択回路
JPH07244634A (ja) * 1994-03-03 1995-09-19 Hitachi Ltd 外部記憶制御装置およびバス切り替え制御方法
JP2001195353A (ja) * 2000-01-06 2001-07-19 Rohm Co Ltd Ｄｍａ転送システム
JP2002123484A (ja) * 2000-09-08 2002-04-26 Texas Instruments Inc バス・システム用の即時許可バス・アービタ
JP2002251370A (ja) * 2001-02-21 2002-09-06 Noritsu Koki Co Ltd 要求調停方法、要求調停装置、メモリ装置、および写真処理システム
JP2002278922A (ja) * 2001-03-16 2002-09-27 Ricoh Co Ltd コンピュータバスシステム
JP2002312309A (ja) * 2001-04-09 2002-10-25 Nec Eng Ltd 調停回路及び調停方法
JP2002318782A (ja) * 2001-04-20 2002-10-31 Nec Corp バスシステム
JP2003256358A (ja) * 2002-02-28 2003-09-12 Sony Corp アービタ装置及び方法、並びに、リソース共有システム
JP2003348097A (ja) * 2002-05-29 2003-12-05 Hitachi Ulsi Systems Co Ltd 無線ｌａｎ装置
JP2005071049A (ja) * 2003-08-22 2005-03-17 Murata Mach Ltd データ転送制御装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014138362A (ja) * 2013-01-18 2014-07-28 Nippon Telegr & Teleph Corp <Ntt> 信号受信回路

Also Published As

Publication number Publication date
WO2007068606A1 (fr) 2007-06-21
US20100122000A1 (en) 2010-05-13
CN101331469B (zh) 2011-11-09
FR2894696A1 (fr) 2007-06-15
KR20080080538A (ko) 2008-09-04
EP1960891A1 (de) 2008-08-27
CN101331469A (zh) 2008-12-24

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