JP2009513030A5 - - Google Patents
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- Publication number
- JP2009513030A5 JP2009513030A5 JP2008537793A JP2008537793A JP2009513030A5 JP 2009513030 A5 JP2009513030 A5 JP 2009513030A5 JP 2008537793 A JP2008537793 A JP 2008537793A JP 2008537793 A JP2008537793 A JP 2008537793A JP 2009513030 A5 JP2009513030 A5 JP 2009513030A5
- Authority
- JP
- Japan
- Prior art keywords
- buffer layer
- chip
- die
- sealing
- dielectric constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims 5
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 239000003566 sealing material Substances 0.000 claims 3
- 230000005684 electric field Effects 0.000 claims 2
- 238000007789 sealing Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
Claims (5)
- 半導体チップを配設する方法において、
導電配線及びボンディングパッドが設けられた主面を有するチップを設ける工程と、
バッファ層を形成すべくチップの主面の少なくとも一部をバッファ層の材料で被覆する工程と、
前記ダイを封止材料で封止する工程と、
バッファ層をパターニングして、チップを外部リードに接続するために使用されるボンディングパッド上の領域の大部分を露出させる間に、バッファ層を導電配線の少なくとも一部の上に残す工程とを備え、
前記バッファ層材料は、(1)前記封止材料の誘電率よりも低い誘電率、及び、(2)前記封止材料の損失正接よりも低い損失正接のうちの少なくとも一方を有する、方法。 - 前記バッファ層材料の誘電率は3.0よりも低い、請求項1記載の方法。
- バッファ層の材料で被覆する前記工程では、バッファ層が均一な厚さを有するように前記ダイの主面の大部分をバッファ層で被覆する、請求項1記載の方法。
- 被覆する工程の後に、シール層をバッファ層の外側表面上に形成する工程をさらに備える、請求項1記載の方法。
- 前記半導体ダイは所定の周波数で動作したときにフリンジ電界を生じ、前記バッファ層材料で被覆する工程では、前記フリンジ電界をバッファ層の内部に収めるために十分な一定の膜厚を有したバッファ層を形成すべく前記ダイの主面の大部分をバッファ層で被覆する、請求項1記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/257,822 US7432133B2 (en) | 2005-10-24 | 2005-10-24 | Plastic packaged device with die interface layer |
PCT/US2006/040871 WO2007050422A2 (en) | 2005-10-24 | 2006-10-18 | Plastic packaged device with die interface layer |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009513030A JP2009513030A (ja) | 2009-03-26 |
JP2009513030A5 true JP2009513030A5 (ja) | 2009-12-03 |
Family
ID=37968398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008537793A Pending JP2009513030A (ja) | 2005-10-24 | 2006-10-18 | 界面層を有する樹脂パッケージ半導体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7432133B2 (ja) |
JP (1) | JP2009513030A (ja) |
CN (1) | CN101517718B (ja) |
TW (1) | TWI470747B (ja) |
WO (1) | WO2007050422A2 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2005304912A1 (en) | 2004-11-04 | 2006-05-18 | Smith & Nephew, Inc. | Cycle and load measurement device |
CA2620247C (en) | 2005-08-23 | 2014-04-29 | Smith & Nephew, Inc. | Telemetric orthopaedic implant |
JP4773307B2 (ja) * | 2006-09-15 | 2011-09-14 | Okiセミコンダクタ株式会社 | 半導体装置の製造方法 |
WO2008103181A1 (en) | 2007-02-23 | 2008-08-28 | Smith & Nephew, Inc. | Processing sensed accelerometer data for determination of bone healing |
US8570187B2 (en) * | 2007-09-06 | 2013-10-29 | Smith & Nephew, Inc. | System and method for communicating with a telemetric implant |
AU2009209045B2 (en) * | 2008-02-01 | 2014-09-18 | Smith & Nephew, Inc. | System and method for communicating with an implant |
US8704124B2 (en) | 2009-01-29 | 2014-04-22 | Smith & Nephew, Inc. | Low temperature encapsulate welding |
US8866708B2 (en) * | 2011-01-21 | 2014-10-21 | Peter Sui Lun Fong | Light emitting diode switch device and array |
US9190393B1 (en) | 2013-09-10 | 2015-11-17 | Delta Electronics, Inc. | Low parasitic capacitance semiconductor device package |
US10224260B2 (en) * | 2013-11-26 | 2019-03-05 | Infineon Technologies Ag | Semiconductor package with air gap |
JP2015231027A (ja) * | 2014-06-06 | 2015-12-21 | 住友電気工業株式会社 | 半導体装置 |
US10672703B2 (en) | 2018-09-26 | 2020-06-02 | Nxp Usa, Inc. | Transistor with shield structure, packaged device, and method of fabrication |
CN109273418A (zh) * | 2018-11-08 | 2019-01-25 | 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 | 一种芯片封装结构及方法 |
US11248769B2 (en) | 2019-04-10 | 2022-02-15 | Peter Sui Lun Fong | Optic for touch-sensitive light emitting diode switch |
US11728305B2 (en) | 2021-05-11 | 2023-08-15 | Sandisk Technologies Llc | Capacitor structure including bonding pads as electrodes and methods of forming the same |
CN114678298B (zh) * | 2022-03-14 | 2022-09-09 | 珠海市众知科技有限公司 | 一种集成电路块引脚封装装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2906282B2 (ja) * | 1990-09-20 | 1999-06-14 | 富士通株式会社 | ガラスセラミック・グリーンシートと多層基板、及び、その製造方法 |
JPH04314394A (ja) * | 1991-04-12 | 1992-11-05 | Fujitsu Ltd | ガラスセラミック回路基板とその製造方法 |
US5598034A (en) * | 1992-07-22 | 1997-01-28 | Vlsi Packaging Corporation | Plastic packaging of microelectronic circuit devices |
KR100280762B1 (ko) * | 1992-11-03 | 2001-03-02 | 비센트 비.인그라시아 | 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법 |
JP3170141B2 (ja) * | 1993-07-27 | 2001-05-28 | 株式会社東芝 | 半導体装置 |
US5578860A (en) * | 1995-05-01 | 1996-11-26 | Motorola, Inc. | Monolithic high frequency integrated circuit structure having a grounded source configuration |
JPH1065067A (ja) * | 1996-08-22 | 1998-03-06 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3516592B2 (ja) * | 1998-08-18 | 2004-04-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
US6001673A (en) * | 1999-02-11 | 1999-12-14 | Ericsson Inc. | Methods for packaging integrated circuit devices including cavities adjacent active regions |
KR100298827B1 (ko) * | 1999-07-09 | 2001-11-01 | 윤종용 | 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법 |
US6509415B1 (en) * | 2000-04-07 | 2003-01-21 | Honeywell International Inc. | Low dielectric constant organic dielectrics based on cage-like structures |
US6627669B2 (en) * | 2000-06-06 | 2003-09-30 | Honeywell International Inc. | Low dielectric materials and methods of producing same |
US6423811B1 (en) * | 2000-07-19 | 2002-07-23 | Honeywell International Inc. | Low dielectric constant materials with polymeric networks |
EP1215724B1 (en) * | 2000-11-20 | 2012-10-31 | Texas Instruments Incorporated | Wire bonded semiconductor device with low capacitance coupling |
US6744117B2 (en) * | 2002-02-28 | 2004-06-01 | Motorola, Inc. | High frequency semiconductor device and method of manufacture |
-
2005
- 2005-10-24 US US11/257,822 patent/US7432133B2/en active Active
-
2006
- 2006-10-18 WO PCT/US2006/040871 patent/WO2007050422A2/en active Application Filing
- 2006-10-18 JP JP2008537793A patent/JP2009513030A/ja active Pending
- 2006-10-18 CN CN2006800397984A patent/CN101517718B/zh active Active
- 2006-10-23 TW TW95139048A patent/TWI470747B/zh active
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