JP2009513030A5 - - Google Patents

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Publication number
JP2009513030A5
JP2009513030A5 JP2008537793A JP2008537793A JP2009513030A5 JP 2009513030 A5 JP2009513030 A5 JP 2009513030A5 JP 2008537793 A JP2008537793 A JP 2008537793A JP 2008537793 A JP2008537793 A JP 2008537793A JP 2009513030 A5 JP2009513030 A5 JP 2009513030A5
Authority
JP
Japan
Prior art keywords
buffer layer
chip
die
sealing
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008537793A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009513030A (ja
Filing date
Publication date
Priority claimed from US11/257,822 external-priority patent/US7432133B2/en
Application filed filed Critical
Publication of JP2009513030A publication Critical patent/JP2009513030A/ja
Publication of JP2009513030A5 publication Critical patent/JP2009513030A5/ja
Pending legal-status Critical Current

Links

JP2008537793A 2005-10-24 2006-10-18 界面層を有する樹脂パッケージ半導体装置 Pending JP2009513030A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/257,822 US7432133B2 (en) 2005-10-24 2005-10-24 Plastic packaged device with die interface layer
PCT/US2006/040871 WO2007050422A2 (en) 2005-10-24 2006-10-18 Plastic packaged device with die interface layer

Publications (2)

Publication Number Publication Date
JP2009513030A JP2009513030A (ja) 2009-03-26
JP2009513030A5 true JP2009513030A5 (enExample) 2009-12-03

Family

ID=37968398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008537793A Pending JP2009513030A (ja) 2005-10-24 2006-10-18 界面層を有する樹脂パッケージ半導体装置

Country Status (5)

Country Link
US (1) US7432133B2 (enExample)
JP (1) JP2009513030A (enExample)
CN (1) CN101517718B (enExample)
TW (1) TWI470747B (enExample)
WO (1) WO2007050422A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006052765A2 (en) 2004-11-04 2006-05-18 Smith & Nephew, Inc. Cycle and load measurement device
CN103637840A (zh) 2005-08-23 2014-03-19 史密夫和内修有限公司 遥测矫形植入物
JP4773307B2 (ja) * 2006-09-15 2011-09-14 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
EP2114247B1 (en) 2007-02-23 2013-10-30 Smith & Nephew, Inc. Processing sensed accelerometer data for determination of bone healing
US8570187B2 (en) * 2007-09-06 2013-10-29 Smith & Nephew, Inc. System and method for communicating with a telemetric implant
WO2009097485A1 (en) * 2008-02-01 2009-08-06 Smith & Nephew, Inc. System and method for communicating with an implant
US8704124B2 (en) 2009-01-29 2014-04-22 Smith & Nephew, Inc. Low temperature encapsulate welding
US8866708B2 (en) * 2011-01-21 2014-10-21 Peter Sui Lun Fong Light emitting diode switch device and array
US9190393B1 (en) 2013-09-10 2015-11-17 Delta Electronics, Inc. Low parasitic capacitance semiconductor device package
US10224260B2 (en) * 2013-11-26 2019-03-05 Infineon Technologies Ag Semiconductor package with air gap
JP2015231027A (ja) * 2014-06-06 2015-12-21 住友電気工業株式会社 半導体装置
US10672703B2 (en) 2018-09-26 2020-06-02 Nxp Usa, Inc. Transistor with shield structure, packaged device, and method of fabrication
CN109273418A (zh) * 2018-11-08 2019-01-25 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 一种芯片封装结构及方法
US11248769B2 (en) 2019-04-10 2022-02-15 Peter Sui Lun Fong Optic for touch-sensitive light emitting diode switch
US11728305B2 (en) 2021-05-11 2023-08-15 Sandisk Technologies Llc Capacitor structure including bonding pads as electrodes and methods of forming the same
CN114678298B (zh) * 2022-03-14 2022-09-09 珠海市众知科技有限公司 一种集成电路块引脚封装装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2906282B2 (ja) 1990-09-20 1999-06-14 富士通株式会社 ガラスセラミック・グリーンシートと多層基板、及び、その製造方法
JPH04314394A (ja) 1991-04-12 1992-11-05 Fujitsu Ltd ガラスセラミック回路基板とその製造方法
US5598034A (en) 1992-07-22 1997-01-28 Vlsi Packaging Corporation Plastic packaging of microelectronic circuit devices
KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
JP3170141B2 (ja) * 1993-07-27 2001-05-28 株式会社東芝 半導体装置
US5578860A (en) 1995-05-01 1996-11-26 Motorola, Inc. Monolithic high frequency integrated circuit structure having a grounded source configuration
JPH1065067A (ja) * 1996-08-22 1998-03-06 Toshiba Corp 半導体装置及びその製造方法
JP3516592B2 (ja) * 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6001673A (en) 1999-02-11 1999-12-14 Ericsson Inc. Methods for packaging integrated circuit devices including cavities adjacent active regions
KR100298827B1 (ko) * 1999-07-09 2001-11-01 윤종용 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
US6509415B1 (en) 2000-04-07 2003-01-21 Honeywell International Inc. Low dielectric constant organic dielectrics based on cage-like structures
US6627669B2 (en) 2000-06-06 2003-09-30 Honeywell International Inc. Low dielectric materials and methods of producing same
US6423811B1 (en) 2000-07-19 2002-07-23 Honeywell International Inc. Low dielectric constant materials with polymeric networks
EP1215724B1 (en) * 2000-11-20 2012-10-31 Texas Instruments Incorporated Wire bonded semiconductor device with low capacitance coupling
US6744117B2 (en) 2002-02-28 2004-06-01 Motorola, Inc. High frequency semiconductor device and method of manufacture

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