JP2009302226A - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
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- JP2009302226A JP2009302226A JP2008153961A JP2008153961A JP2009302226A JP 2009302226 A JP2009302226 A JP 2009302226A JP 2008153961 A JP2008153961 A JP 2008153961A JP 2008153961 A JP2008153961 A JP 2008153961A JP 2009302226 A JP2009302226 A JP 2009302226A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000009792 diffusion process Methods 0.000 claims abstract description 45
- 239000012535 impurity Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000001514 detection method Methods 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract 3
- 239000003990 capacitor Substances 0.000 description 49
- 239000011229 interlayer Substances 0.000 description 13
- 239000010410 layer Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910020781 SixOy Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】各メモリセルは、ワードラインによって制御される選択トランジスタと、半導体基板内に形成され、選択トランジスタのソース又はドレインに接続された不純物拡散領域と、半導体基板上に絶縁膜を介して形成され、一部に開口が形成されて、制御信号が印加される第1の電極と、第1の電極上に絶縁膜を介して形成され、該絶縁膜を介して第1の電極に対向し、第1の電極に設けられた開口を通して半導体基板側に突出すると共にトンネル膜を介して不純物拡散領域に対向する突出部を有し、印加される電圧に応じて情報を格納する第2の電極と、第2の電極に蓄積される電荷に応じて動作することにより、メモリセルに格納されている情報を検出する検出トランジスタとを具備する。
【選択図】図1
Description
図1は、本発明の第1の実施形態に係る半導体集積回路に内蔵されているEEPROMのメモリセルの構造を示す図である。図1の(a)は、平面図であり、図1の(b)は、図1の(a)に示すI−Iにおける断面図である。なお、図1においては、導電体の位置関係を示すために、層間絶縁膜が省略されている。
図3は、図1に示すメモリセルの回路図である。データの書込みにおいて、トランジスタQ1(検出トランジスタ)のソースはオープン状態とされる。また、当該メモリセルを選択する場合には、トランジスタQ2(選択トランジスタ)のゲート電極であるワードラインに所定の高電位VDが印加される。
図4は、本発明の第2の実施形態に係る半導体集積回路に内蔵されているEEPROMのメモリセルの構造を示す図である。図4の(a)は、平面図であり、図4の(b)は、図4の(a)に示すIV−IVにおける断面図である。なお、図4においては、導電体の位置関係を示すために、層間絶縁膜が省略されている。
図5は、本発明の第3の実施形態に係る半導体集積回路に内蔵されているEEPROMのメモリセルの構造を示す図である。図5の(a)は、平面図であり、図5の(b)は、図5の(a)に示すV−Vにおける断面図である。なお、図5においては、導電体の位置関係を示すために、層間絶縁膜が省略されている。
Claims (5)
- データの書込み及び消去を電気的に行う不揮発性メモリを内蔵した半導体集積回路であって、各メモリセルが、
ワードラインによって制御される選択トランジスタと、
半導体基板内に形成され、前記選択トランジスタのソース又はドレインに接続された不純物拡散領域と、
前記半導体基板上に絶縁膜を介して形成され、一部に開口が形成された第1の電極であって、制御信号が印加される前記第1の電極と、
前記第1の電極上に絶縁膜を介して形成され、該絶縁膜を介して前記第1の電極に対向する第2の電極であって、前記第1の電極に設けられた開口を通して前記半導体基板側に突出すると共にトンネル膜を介して前記不純物拡散領域に対向する突出部を有し、印加される電圧に応じて情報を格納する前記第2の電極と、
前記第2の電極に蓄積される電荷に応じて動作することにより、メモリセルに格納されている情報を検出する検出トランジスタと、
を具備する半導体集積回路。 - 前記半導体基板の主面において、前記第1の電極に対向する領域に酸化膜が形成されており、前記酸化膜が形成された領域が、前記不純物拡散領域が形成された領域の周囲を囲んでいる、請求項1記載の半導体集積回路。
- 前記第2の電極と前記第1の電極との間の絶縁膜が、窒化膜を含む、請求項1又は2記載の半導体集積回路。
- 前記検出トランジスタが、前記第2の電極に電気的に接続されたフローティングゲート電極を有する、請求項1〜3のいずれか1項記載の半導体集積回路。
- 前記検出トランジスタが、前記第2の電極と一体化されて形成されたフローティングゲート電極を有する、請求項1〜3のいずれか1項記載の半導体集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008153961A JP4609533B2 (ja) | 2008-06-12 | 2008-06-12 | 半導体集積回路 |
US12/469,181 US8040728B2 (en) | 2008-06-12 | 2009-05-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008153961A JP4609533B2 (ja) | 2008-06-12 | 2008-06-12 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
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JP2009302226A true JP2009302226A (ja) | 2009-12-24 |
JP4609533B2 JP4609533B2 (ja) | 2011-01-12 |
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Application Number | Title | Priority Date | Filing Date |
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JP2008153961A Expired - Fee Related JP4609533B2 (ja) | 2008-06-12 | 2008-06-12 | 半導体集積回路 |
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US (1) | US8040728B2 (ja) |
JP (1) | JP4609533B2 (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59500343A (ja) * | 1982-03-09 | 1984-03-01 | ア−ルシ−エ− コ−ポレ−シヨン | 電気的に改変可能の不揮発性浮動ゲ−ト記憶装置 |
JPS62502156A (ja) * | 1985-03-08 | 1987-08-20 | エヌ・シ−・ア−ル・コ−ポレ−シヨン | フロ−ティング・ゲ−ト不揮発性電界効果メモリ−装置 |
JPH01146371A (ja) * | 1987-12-02 | 1989-06-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH06244431A (ja) * | 1993-02-16 | 1994-09-02 | Matsushita Electron Corp | 半導体記憶装置 |
JP2003092368A (ja) * | 2001-09-19 | 2003-03-28 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0215064A1 (en) | 1985-03-08 | 1987-03-25 | Ncr Corporation | Floating gate nonvolatile field effect memory device |
US5457061A (en) * | 1994-07-15 | 1995-10-10 | United Microelectronics Corporation | Method of making top floating-gate flash EEPROM structure |
JP2000012709A (ja) | 1998-06-18 | 2000-01-14 | Toshiba Corp | 不揮発性半導体メモリ及びその製造方法 |
JP2002246485A (ja) | 2001-02-13 | 2002-08-30 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置およびその製造方法 |
US7307309B2 (en) * | 2004-03-04 | 2007-12-11 | Texas Instruments Incorporated | EEPROM with etched tunneling window |
JP2006066695A (ja) * | 2004-08-27 | 2006-03-09 | Renesas Technology Corp | 半導体装置およびその製造方法 |
-
2008
- 2008-06-12 JP JP2008153961A patent/JP4609533B2/ja not_active Expired - Fee Related
-
2009
- 2009-05-20 US US12/469,181 patent/US8040728B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59500343A (ja) * | 1982-03-09 | 1984-03-01 | ア−ルシ−エ− コ−ポレ−シヨン | 電気的に改変可能の不揮発性浮動ゲ−ト記憶装置 |
JPS62502156A (ja) * | 1985-03-08 | 1987-08-20 | エヌ・シ−・ア−ル・コ−ポレ−シヨン | フロ−ティング・ゲ−ト不揮発性電界効果メモリ−装置 |
JPH01146371A (ja) * | 1987-12-02 | 1989-06-08 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH06244431A (ja) * | 1993-02-16 | 1994-09-02 | Matsushita Electron Corp | 半導体記憶装置 |
JP2003092368A (ja) * | 2001-09-19 | 2003-03-28 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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US20090310417A1 (en) | 2009-12-17 |
US8040728B2 (en) | 2011-10-18 |
JP4609533B2 (ja) | 2011-01-12 |
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