JP2009272453A5 - - Google Patents
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- Publication number
- JP2009272453A5 JP2009272453A5 JP2008121920A JP2008121920A JP2009272453A5 JP 2009272453 A5 JP2009272453 A5 JP 2009272453A5 JP 2008121920 A JP2008121920 A JP 2008121920A JP 2008121920 A JP2008121920 A JP 2008121920A JP 2009272453 A5 JP2009272453 A5 JP 2009272453A5
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- layer
- region
- semiconductor
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 claims 36
- 239000012535 impurity Substances 0.000 claims 25
- 239000000758 substrate Substances 0.000 claims 15
- 238000009792 diffusion process Methods 0.000 claims 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008121920A JP2009272453A (ja) | 2008-05-08 | 2008-05-08 | トランジスタ、半導体装置及びその製造方法 |
| US12/434,128 US8022475B2 (en) | 2008-05-08 | 2009-05-01 | Semiconductor device optimized to increase withstand voltage and reduce on resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008121920A JP2009272453A (ja) | 2008-05-08 | 2008-05-08 | トランジスタ、半導体装置及びその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2009272453A JP2009272453A (ja) | 2009-11-19 |
| JP2009272453A5 true JP2009272453A5 (enExample) | 2011-05-19 |
Family
ID=41266173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008121920A Pending JP2009272453A (ja) | 2008-05-08 | 2008-05-08 | トランジスタ、半導体装置及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8022475B2 (enExample) |
| JP (1) | JP2009272453A (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928513B (zh) * | 2013-01-15 | 2017-03-29 | 无锡华润上华半导体有限公司 | 一种沟槽dmos器件及其制作方法 |
| KR102316160B1 (ko) | 2014-12-22 | 2021-10-26 | 삼성전자주식회사 | 반도체 소자 및 이를 제조하는 방법 |
| US9391194B1 (en) * | 2015-06-19 | 2016-07-12 | Sanken Electric Co., Ltd. | High voltage vertical FPMOS fets |
| US20180076038A1 (en) * | 2016-09-09 | 2018-03-15 | Texas Instruments Incorporated | Method For Producing Two N-Type Buried Layers In An Integrated Circuit |
| CN109216175B (zh) * | 2017-07-03 | 2021-01-08 | 无锡华润上华科技有限公司 | 半导体器件的栅极结构及其制造方法 |
| JP7157027B2 (ja) * | 2019-09-12 | 2022-10-19 | 株式会社東芝 | 半導体装置 |
| US11670693B2 (en) * | 2021-01-28 | 2023-06-06 | Semiconductor Components Industries, Llc | Trench gate field-effect transistors with drain runner |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4111720A (en) * | 1977-03-31 | 1978-09-05 | International Business Machines Corporation | Method for forming a non-epitaxial bipolar integrated circuit |
| JPH02170571A (ja) * | 1988-12-23 | 1990-07-02 | Fujitsu Ltd | 半導体装置とその製造方法 |
| US5218224A (en) * | 1989-06-14 | 1993-06-08 | Kabushiki Kaisha Toshiba | Semiconductor device including inversion preventing layers having a plurality of impurity concentration peaks in direction of depth |
| US5290714A (en) * | 1990-01-12 | 1994-03-01 | Hitachi, Ltd. | Method of forming semiconductor device including a CMOS structure having double-doped channel regions |
| JP2736493B2 (ja) * | 1992-04-03 | 1998-04-02 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| JPH07326742A (ja) * | 1994-05-30 | 1995-12-12 | Toshiba Corp | 半導体装置およびその製造方法 |
| JP3303601B2 (ja) * | 1995-05-19 | 2002-07-22 | 日産自動車株式会社 | 溝型半導体装置 |
| JP3306273B2 (ja) * | 1995-10-31 | 2002-07-24 | 三洋電機株式会社 | 半導体集積回路とその製造方法 |
| JP3104747B2 (ja) * | 1996-12-27 | 2000-10-30 | サンケン電気株式会社 | 半導体装置の製造方法 |
| US5854099A (en) * | 1997-06-06 | 1998-12-29 | National Semiconductor Corporation | DMOS process module applicable to an E2 CMOS core process |
| JP4534267B2 (ja) * | 1998-12-22 | 2010-09-01 | ソニー株式会社 | 半導体装置の製造方法 |
| JP3530414B2 (ja) * | 1999-03-26 | 2004-05-24 | 三洋電機株式会社 | 半導体装置 |
| DE19929235B4 (de) * | 1999-06-25 | 2005-06-23 | Infineon Technologies Ag | Vertikaler DMOS-Transistor und Verfahren zum Herstellen eines vertikalen DMOS- Transistor |
| JP2002141476A (ja) * | 2000-11-07 | 2002-05-17 | Hitachi Ltd | BiCMOS半導体集積回路装置およびその製造方法 |
| JP2003209246A (ja) * | 2002-01-16 | 2003-07-25 | Sanken Electric Co Ltd | 半導体装置及びその製造方法 |
| JP2003303960A (ja) * | 2002-04-09 | 2003-10-24 | Sanyo Electric Co Ltd | 縦型mos半導体装置およびその製造方法 |
| JP2003303959A (ja) | 2002-04-09 | 2003-10-24 | Sanyo Electric Co Ltd | 縦型mos半導体装置およびその製造方法 |
| JP3644682B2 (ja) | 2002-06-03 | 2005-05-11 | 三洋電機株式会社 | 半導体装置の製造方法 |
| US6900091B2 (en) * | 2002-08-14 | 2005-05-31 | Advanced Analogic Technologies, Inc. | Isolated complementary MOS devices in epi-less substrate |
| JP3865728B2 (ja) * | 2003-12-05 | 2007-01-10 | シャープ株式会社 | 閾値電圧変調方式のmos型固体撮像素子およびその製造方法 |
| US7211829B2 (en) * | 2004-03-01 | 2007-05-01 | Matsushita Electric Industrial Co., Ltd | Semiconductor photodetector device |
| JP5307966B2 (ja) * | 2005-03-30 | 2013-10-02 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置の製造方法 |
| JP5164333B2 (ja) | 2005-12-28 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
| TW200847448A (en) * | 2007-05-30 | 2008-12-01 | Intersil Inc | Junction barrier schottky diode |
| US20090090981A1 (en) * | 2007-10-05 | 2009-04-09 | Kazuhiro Natsuaki | Semiconductor device |
-
2008
- 2008-05-08 JP JP2008121920A patent/JP2009272453A/ja active Pending
-
2009
- 2009-05-01 US US12/434,128 patent/US8022475B2/en active Active
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