JP2009130054A - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP2009130054A
JP2009130054A JP2007302007A JP2007302007A JP2009130054A JP 2009130054 A JP2009130054 A JP 2009130054A JP 2007302007 A JP2007302007 A JP 2007302007A JP 2007302007 A JP2007302007 A JP 2007302007A JP 2009130054 A JP2009130054 A JP 2009130054A
Authority
JP
Japan
Prior art keywords
wiring
layer
wiring board
support
concave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007302007A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009130054A5 (https=
Inventor
Takashi Kurihara
孝 栗原
Hiroshi Murayama
啓 村山
Mitsutoshi Higashi
光敏 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007302007A priority Critical patent/JP2009130054A/ja
Priority to KR1020080115571A priority patent/KR20090052814A/ko
Priority to US12/274,719 priority patent/US20090134530A1/en
Priority to EP08169709A priority patent/EP2066156A3/en
Priority to TW097145075A priority patent/TW200924596A/zh
Publication of JP2009130054A publication Critical patent/JP2009130054A/ja
Publication of JP2009130054A5 publication Critical patent/JP2009130054A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0376—Etching temporary metallic carrier substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2007302007A 2007-11-21 2007-11-21 配線基板及びその製造方法 Pending JP2009130054A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2007302007A JP2009130054A (ja) 2007-11-21 2007-11-21 配線基板及びその製造方法
KR1020080115571A KR20090052814A (ko) 2007-11-21 2008-11-20 배선기판 및 이의 제조방법
US12/274,719 US20090134530A1 (en) 2007-11-21 2008-11-20 Wiring substrate and method of manufacturing the same
EP08169709A EP2066156A3 (en) 2007-11-21 2008-11-21 Wiring substrate and method of manufacturing the same
TW097145075A TW200924596A (en) 2007-11-21 2008-11-21 Wiring substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007302007A JP2009130054A (ja) 2007-11-21 2007-11-21 配線基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2009130054A true JP2009130054A (ja) 2009-06-11
JP2009130054A5 JP2009130054A5 (https=) 2010-10-21

Family

ID=40409951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007302007A Pending JP2009130054A (ja) 2007-11-21 2007-11-21 配線基板及びその製造方法

Country Status (5)

Country Link
US (1) US20090134530A1 (https=)
EP (1) EP2066156A3 (https=)
JP (1) JP2009130054A (https=)
KR (1) KR20090052814A (https=)
TW (1) TW200924596A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5120342B2 (ja) * 2009-06-18 2013-01-16 ソニー株式会社 半導体パッケージの製造方法
US8127979B1 (en) * 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
KR102079256B1 (ko) 2013-09-13 2020-02-20 삼성디스플레이 주식회사 표시장치 및 이의 제조방법
JP2017017238A (ja) * 2015-07-03 2017-01-19 株式会社ジェイデバイス 半導体装置及びその製造方法
US20180190596A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Standoff members for semiconductor package
KR101938104B1 (ko) * 2018-01-25 2019-01-14 주식회사 기가레인 접합 평탄도가 개선된 연성회로기판
CN112038242A (zh) * 2020-09-10 2020-12-04 华进半导体封装先导技术研发中心有限公司 先重布线扇出型封装方法及结构
KR102901072B1 (ko) * 2023-08-07 2025-12-16 삼성전기주식회사 회로 기판

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050877A (ja) * 1996-07-30 1998-02-20 Toshiba Corp 半導体パッケージ
JP2001060648A (ja) * 1999-08-23 2001-03-06 Dainippon Printing Co Ltd リードフレーム及びその製造方法並びに半導体装置
JP2002299495A (ja) * 2001-03-30 2002-10-11 Fuji Electric Co Ltd 半導体回路基板
JP2005302922A (ja) * 2004-04-09 2005-10-27 Ngk Spark Plug Co Ltd 配線基板およびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552267B2 (en) * 2001-08-13 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic assembly with stiffening member
SG102637A1 (en) * 2001-09-10 2004-03-26 Micron Technology Inc Bow control in an electronic package
JP3615727B2 (ja) * 2001-10-31 2005-02-02 新光電気工業株式会社 半導体装置用パッケージ
JP3664720B2 (ja) 2001-10-31 2005-06-29 新光電気工業株式会社 半導体装置用多層回路基板の製造方法
JP4094494B2 (ja) * 2002-08-23 2008-06-04 新光電気工業株式会社 半導体パッケージ
AU2003227213A1 (en) * 2003-03-26 2004-10-18 Fujitsu Limited Semiconductor device
JP2006186136A (ja) * 2004-12-28 2006-07-13 Toshiba Corp 両面部品実装回路基板及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050877A (ja) * 1996-07-30 1998-02-20 Toshiba Corp 半導体パッケージ
JP2001060648A (ja) * 1999-08-23 2001-03-06 Dainippon Printing Co Ltd リードフレーム及びその製造方法並びに半導体装置
JP2002299495A (ja) * 2001-03-30 2002-10-11 Fuji Electric Co Ltd 半導体回路基板
JP2005302922A (ja) * 2004-04-09 2005-10-27 Ngk Spark Plug Co Ltd 配線基板およびその製造方法

Also Published As

Publication number Publication date
EP2066156A3 (en) 2009-12-02
TW200924596A (en) 2009-06-01
EP2066156A2 (en) 2009-06-03
KR20090052814A (ko) 2009-05-26
US20090134530A1 (en) 2009-05-28

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