JP2009094238A - 半導体記憶装置およびその製造方法 - Google Patents
半導体記憶装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 114
- 238000003860 storage Methods 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 96
- 239000002096 quantum dot Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 40
- 238000001459 lithography Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 32
- 239000010410 layer Substances 0.000 abstract description 19
- 239000011229 interlayer Substances 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 38
- 229910021417 amorphous silicon Inorganic materials 0.000 description 34
- 238000005530 etching Methods 0.000 description 32
- 150000004767 nitrides Chemical class 0.000 description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 10
- 238000002513 implantation Methods 0.000 description 10
- 238000001039 wet etching Methods 0.000 description 10
- 238000000059 patterning Methods 0.000 description 8
- 238000004380 ashing Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 3
- 238000010894 electron beam technology Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 125000001301 ethoxy group Chemical group [H]C([H])([H])C([H])([H])O* 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004460 silage Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7888—Transistors programmable by two single electrons
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
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Abstract
【解決手段】半導体記憶装置1は、SOI基板11と、量子ドット21と、インターポリ絶縁膜27と、ラインパターン29と、層間絶縁膜301と、ビット線31とを備える。量子ドット21は、トンネル酸化膜13を介してSOI基板11上に多結晶シリコンで形成されて電荷蓄積層をなす。ラインパターン29は、インターポリ絶縁膜27上で、多結晶シリコンで形成されてコントロールゲート(ワード線)をなす。量子ドット21は、ビット線31に直列に接続される。量子ドット21の4つの側壁と、ラインパターン29のビット線に平行な方向における側壁は、熱酸化膜33で覆われている。量子ドット21a〜21dを一単位として、間隔S4だけ離隔するように反復形成される。
【選択図】図1
Description
少なくとも表面に半導体層を有する基板と、
ビット線に直列に接続されるように前記半導体層上にトンネル絶縁膜となる第一の絶縁膜を介して形成された電荷蓄積層をなす複数の量子ドット素子を備える半導体記憶装置が提供される。
リソグラフィ工程と側壁マスク工程とを用いて、少なくとも表面に半導体層を有する基板の前記半導体層上に、トンネル絶縁膜となる第一の絶縁膜を介して電荷蓄積層をなす複数の量子ドット素子を周期的に反復形成する半導体記憶装置の製造方法が提供される。
13:トンネル絶縁膜
21a〜21g:量子ドット
29:コントロールゲート(ワード線)
31:ビット線
S2〜S4:間隔
64,65,69,70,143,106a,LP26:側壁マスクパターン
Claims (5)
- 少なくとも表面に半導体層を有する基板と、
ビット線に直列に接続されるように前記半導体層上にトンネル絶縁膜となる第一の絶縁膜を介して形成された電荷蓄積層をなす複数の量子ドット素子を備える半導体記憶装置。 - 前記複数の量子ドット素子は、第1乃至第3の間隔だけ互いに離隔して配置される第1乃至第4の量子ドット素子を一単位として前記ビット線方向に互いに第4の間隔だけ離隔して周期的に反復形成され、
前記第1の間隔と前記第3の間隔は互いに同一である、
ことを特徴とする請求項1に記載の半導体記憶装置。 - 各量子ドット素子の上にビット線方向と直交する方向に各量子ドット素子と実質的に同一の幅で形成されたワード線をさらに備えることを特徴とする請求項1または2に記載の半導体記憶装置。
- リソグラフィ工程と側壁マスク工程とを用いて、少なくとも表面に半導体層を有する基板の前記半導体層上に、トンネル絶縁膜となる第一の絶縁膜を介して電荷蓄積層をなす複数の量子ドット素子を周期的に反復形成する半導体記憶装置の製造方法。
- 前記側壁マスク加工は、側壁マスクパターンが互いに直交する方向に重ねて行われ、
前記量子ドット素子は、前記側壁マスクパターンが交差する箇所の下に形成される、
ことを特徴とする請求項4に記載の半導体記憶装置の製造方法。
Priority Applications (2)
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JP2007262471A JP5134331B2 (ja) | 2007-10-05 | 2007-10-05 | 半導体記憶装置およびその製造方法 |
US12/245,396 US8198665B2 (en) | 2007-10-05 | 2008-10-03 | Semiconductor storage device and manufacturing method thereof |
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JP2007262471A JP5134331B2 (ja) | 2007-10-05 | 2007-10-05 | 半導体記憶装置およびその製造方法 |
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JP2009094238A true JP2009094238A (ja) | 2009-04-30 |
JP5134331B2 JP5134331B2 (ja) | 2013-01-30 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013135202A (ja) * | 2011-12-27 | 2013-07-08 | Toshiba Corp | 半導体装置の製造方法 |
JP2014072420A (ja) * | 2012-09-28 | 2014-04-21 | Toshiba Corp | マスクデータの作成方法及び集積回路装置の製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1738378A4 (en) | 2004-03-18 | 2010-05-05 | Nanosys Inc | NANOFIBRE SURFACE BASED CAPACITORS |
US8877367B2 (en) | 2009-01-16 | 2014-11-04 | The Board Of Trustees Of The Leland Stanford Junior University | High energy storage capacitor by embedding tunneling nano-structures |
CA2748655A1 (en) * | 2009-01-16 | 2010-07-22 | The Board Of Trustees Of The Leland Stanford Junior University | Quantum dot ultracapacitor and electron battery |
JP4929300B2 (ja) * | 2009-02-25 | 2012-05-09 | 株式会社東芝 | マルチドットフラッシュメモリ及びその製造方法 |
CN102439694A (zh) * | 2009-04-01 | 2012-05-02 | 利兰·斯坦福青年大学托管委员会 | 带有面积增加的电极的全电子电池 |
CN110020727B (zh) * | 2019-04-09 | 2021-06-08 | 合肥本源量子计算科技有限责任公司 | 一种基于mpi多进程的单量子逻辑门实现方法 |
KR20200137379A (ko) | 2019-05-30 | 2020-12-09 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
Citations (3)
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JPH0855920A (ja) * | 1994-08-15 | 1996-02-27 | Toshiba Corp | 半導体装置の製造方法 |
JPH08288480A (ja) * | 1995-04-12 | 1996-11-01 | Sony Corp | シリコン量子ドットの製造方法 |
JPH0936105A (ja) * | 1995-07-17 | 1997-02-07 | Siemens Ag | サブリソグラフ式エッチングマスクの製造方法 |
Family Cites Families (11)
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JP4538693B2 (ja) | 1998-01-26 | 2010-09-08 | ソニー株式会社 | メモリ素子およびその製造方法 |
KR100325689B1 (ko) | 1999-12-01 | 2002-02-25 | 오길록 | 전자-홀 결합을 이용한 단전자 메모리 소자 |
US6694352B1 (en) * | 1999-12-16 | 2004-02-17 | Microsoft Corporation | Methods and systems for notifying clients concerning live electronic presentations |
TW550797B (en) | 2002-07-04 | 2003-09-01 | Nat Science Council | Single electron transistor structure with self-aligned polysilicon spacer gate and its manufacturing method |
JP2004349341A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | 半導体記憶素子、半導体装置およびそれらの製造方法、携帯電子機器並びにicカード |
JP2005223234A (ja) * | 2004-02-09 | 2005-08-18 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP2004343128A (ja) | 2004-06-01 | 2004-12-02 | Hitachi Ltd | 半導体記憶素子、半導体記憶装置とその制御方法 |
JP2006196622A (ja) | 2005-01-12 | 2006-07-27 | Nec Electronics Corp | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法 |
KR100745400B1 (ko) * | 2006-03-08 | 2007-08-02 | 삼성전자주식회사 | 게이트 구조 및 이를 형성하는 방법, 비휘발성 메모리 장치및 이의 제조 방법 |
US7419868B2 (en) * | 2006-11-20 | 2008-09-02 | Macronix International Co., Ltd. | Gated diode nonvolatile memory process |
US7512012B2 (en) * | 2007-04-30 | 2009-03-31 | Macronix International Co., Ltd. | Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory |
-
2007
- 2007-10-05 JP JP2007262471A patent/JP5134331B2/ja not_active Expired - Fee Related
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2008
- 2008-10-03 US US12/245,396 patent/US8198665B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0855920A (ja) * | 1994-08-15 | 1996-02-27 | Toshiba Corp | 半導体装置の製造方法 |
JPH08288480A (ja) * | 1995-04-12 | 1996-11-01 | Sony Corp | シリコン量子ドットの製造方法 |
JPH0936105A (ja) * | 1995-07-17 | 1997-02-07 | Siemens Ag | サブリソグラフ式エッチングマスクの製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013135202A (ja) * | 2011-12-27 | 2013-07-08 | Toshiba Corp | 半導体装置の製造方法 |
US8975178B2 (en) | 2011-12-27 | 2015-03-10 | Kabushiki Kaisha Toshiba | Method of manufacturing a memory device using fine patterning techniques |
JP2014072420A (ja) * | 2012-09-28 | 2014-04-21 | Toshiba Corp | マスクデータの作成方法及び集積回路装置の製造方法 |
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Publication number | Publication date |
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US8198665B2 (en) | 2012-06-12 |
US20090096004A1 (en) | 2009-04-16 |
JP5134331B2 (ja) | 2013-01-30 |
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