JP2009094105A - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 151
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000002344 surface layer Substances 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims abstract description 28
- 230000015556 catabolic process Effects 0.000 claims description 64
- 230000005684 electric field Effects 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 16
- 230000006378 damage Effects 0.000 abstract 2
- 230000004048 modification Effects 0.000 description 14
- 238000012986 modification Methods 0.000 description 14
- 230000002093 peripheral effect Effects 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Abstract
【解決手段】IGBTとダイオードとが形成される素子領域には、半導体基板101の第1主面側表層に、IGBTのトレンチゲート103と、IGBTのチャネル領域102と、IGBTのエミッタ領域105と、ダイオードのアノード領域104とが形成され、半導体基板101の第2主面側表層に、IGBTのコレクタ領域108と、ダイオードのカソード領域107とが形成され、素子領域を囲うように形成される高耐圧化領域には、半導体基板101の第1主面側表層に、ガードリング110,111が形成され、半導体基板101の第2主面側表層には、フィールドストップ層109のみを形成する。
【選択図】図1
Description
次に、変形例1における半導体装置に関して説明する。図2は、本発明の実施の形態の変形例1における半導体装置の概略構成を示す断面図である。なお、変形例1は、上述の実施の形態と同等な箇所が多いため、同等な箇所に関しては同一の符号を付与して説明を省略し、異なる箇所を重点的に説明する。
つまり、裏面電極(コレクタ電極)114aは、コレクタ領域108及びカソード領域107のみと電気的に接続(接触)させ、高耐圧化領域におけるフィールドストップ層109とは接触させないようにする。
次に、変形例2における半導体装置に関して説明する。図3は、本発明の実施の形態の変形例2における半導体装置の概略構成を示す断面図である。なお、変形例2は、上述の実施の形態と同等な箇所が多いため、同等な箇所に関しては同一の符号を付与して説明を省略し、異なる箇所を重点的に説明する。
Claims (3)
- IGBTとダイオードとが同じ第1導電型の半導体基板に形成されてなる半導体装置であって、
前記半導体基板は、前記IGBTと前記ダイオードとが形成される素子領域と、前記素子領域を囲うように形成される高耐圧化領域とを含み、
前記素子領域は、
前記半導体基板の主面側の表層部に、前記IGBTのトレンチゲートと、前記IGBTのチャネル形成領域となる第2導電型の第1半導体領域と、前記IGBTのエミッタ領域となる第1導電型の第2半導体領域と、前記ダイオードのアノード領域となる第2導電型の第3半導体領域とが形成され、
前記半導体基板の裏面側の表層部に、前記IGBTのコレクタ領域となる第2導電型の第4半導体領域と、前記ダイオードのカソード領域となる第1導電型の第5半導体領域とが形成され、
前記高耐圧化領域は、
前記半導体基板の主面側の表層部に、第2導電型のガードリングが形成され、
前記半導体基板の裏面側の表層部には、第1導電型からなる電界緩和用のフィールドストップ層のみが形成されることを特徴とする半導体装置。 - 前記半導体基板の裏面側の表層部において、前記第4半導体領域と、前記第5半導体領域と接触し、前記高耐圧化領域を除く位置に形成される裏面電極を備えることを特徴とする請求項1に記載の半導体装置。
- IGBTとダイオードが、同じ第1導電型の半導体基板に形成されてなる半導体装置の製造方法であって、
前記半導体基板は、前記IGBTと前記ダイオードとが形成される素子領域と、前記素子領域を囲うように形成される高耐圧化領域とを含み、
前記素子領域における前記半導体基板の主面側の表層部に、前記IGBTのトレンチゲートを形成する第1工程と、
前記素子領域における前記半導体基板の主面側の表層部に、前記IGBTのチャネル形成領域となる第2導電型の第1半導体領域を形成する第2工程と、
前記素子領域における前記半導体基板の主面側の表層部に、前記IGBTのエミッタ領域となる第1導電型の第2半導体領域を形成する第3工程と、
前記素子領域における前記半導体基板の主面側の表層部に、前記ダイオードのアノード領域となる第2導電型の第3半導体領域を形成する第4工程と、
前記高耐圧化領域における前記半導体基板の主面側の表層部に、第2導電型のガードリングを形成する第5工程と、
前記素子領域及び前記高耐圧化領域における前記半導体基板の裏面側の表層部に、第1導電型からなる電界緩和用のフィールドストップ層を形成する第6工程と、
前記フィールドストップ層内に前記IGBTのコレクタ領域となる第2導電型の第4半導体領域と前記ダイオードのカソード領域となる第1導電型の第5半導体領域とを形成する第7工程と、
前記高耐圧化領域において、前記フィールドストップ層を残しつつ、前記第4半導体領域と前記第5半導体領域とを除去する第8工程と、
を備えることを特徴とする半導体装置の製造方法。
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Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012069634A (ja) * | 2010-09-22 | 2012-04-05 | Mitsubishi Electric Corp | 半導体装置 |
JP2014241433A (ja) * | 2010-05-26 | 2014-12-25 | 三菱電機株式会社 | 半導体装置 |
WO2015004716A1 (ja) * | 2013-07-08 | 2015-01-15 | 三菱電機株式会社 | 半導体装置 |
KR101490350B1 (ko) | 2013-08-21 | 2015-02-10 | 이태복 | 전력용 반도체 장치 및 제조방법 |
US9054066B2 (en) | 2012-08-30 | 2015-06-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
CN107749420A (zh) * | 2017-11-20 | 2018-03-02 | 电子科技大学 | 一种逆阻型igbt |
CN108511512A (zh) * | 2018-02-05 | 2018-09-07 | 东南大学 | 一种带有波浪型场限环结构的功率半导体器件及其制备方法 |
CN109256422A (zh) * | 2017-07-12 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
Families Citing this family (2)
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---|---|---|---|---|
JP6565815B2 (ja) | 2016-07-21 | 2019-08-28 | 株式会社デンソー | 半導体装置 |
JP6565814B2 (ja) | 2016-07-21 | 2019-08-28 | 株式会社デンソー | 半導体装置 |
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2007
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Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014241433A (ja) * | 2010-05-26 | 2014-12-25 | 三菱電機株式会社 | 半導体装置 |
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JP2012069634A (ja) * | 2010-09-22 | 2012-04-05 | Mitsubishi Electric Corp | 半導体装置 |
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CN109256422A (zh) * | 2017-07-12 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN109256422B (zh) * | 2017-07-12 | 2022-04-29 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN107749420A (zh) * | 2017-11-20 | 2018-03-02 | 电子科技大学 | 一种逆阻型igbt |
CN107749420B (zh) * | 2017-11-20 | 2023-09-01 | 电子科技大学 | 一种逆阻型igbt |
CN108511512A (zh) * | 2018-02-05 | 2018-09-07 | 东南大学 | 一种带有波浪型场限环结构的功率半导体器件及其制备方法 |
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