JP2009049272A - Semiconductor device, and its manufacturing method - Google Patents

Semiconductor device, and its manufacturing method Download PDF

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JP2009049272A
JP2009049272A JP2007215673A JP2007215673A JP2009049272A JP 2009049272 A JP2009049272 A JP 2009049272A JP 2007215673 A JP2007215673 A JP 2007215673A JP 2007215673 A JP2007215673 A JP 2007215673A JP 2009049272 A JP2009049272 A JP 2009049272A
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electrode terminal
semiconductor element
semiconductor device
solder
electrode
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JP5011562B2 (en
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Hiroshi Nishibori
弘 西堀
Kunihiro Yoshihara
邦裕 吉原
Hitoshi Otsu
仁史 大津
Kenji Yasukouchi
健次 安河内
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H01L2224/84815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an area required for being jointed to an electrode terminal in a semiconductor element, and of preventing degradation of reliability; and a manufacturing method of the semiconductor device. <P>SOLUTION: This semiconductor device 100a is provided with the semiconductor element 110, an electrode terminal 120, and solder 151. The electrode terminal 120 has an extension part 120a extending along an extension direction, and jointed to the semiconductor element 110 with a tip surface 121 in the extension direction of the extension part 120a abutting on a surface 110a of the semiconductor element 110. The solder 151 joints the electrode terminal 120, the semiconductor element 110 and the electrode terminal 120. The electrode terminal 120 has a surface 122a being a surface intersecting with the extension direction, and directed on the side opposite to the tip surface 121 in a region 120b of the electrode terminal 120 jointed by the solder 151. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に関し、特にはんだを用いて半導体素子と接続される電極端子を備えた半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including an electrode terminal connected to a semiconductor element using solder and a manufacturing method thereof.

従来、はんだなどを介して電極パターンと電極端子とを接合させる技術は、たとえば特開平５−３１５５１７号公報（特許文献１）、特開平７−１３０９３７号公報（特許文献２）、特開２００２−３３４９６４号公報（特許文献３）および特開平３−４８４５２号公報（特許文献４）に開示されている。特許文献１〜４に開示されている半導体装置においては、電極端子の先端部は電極パターンの表面に沿うように折り曲げられており、その折り曲げられた部分で電極パターンと接合されている。
特開平５−３１５５１７号公報 特開平７−１３０９３７号公報 特開２００２−３３４９６４号公報 特開平３−４８４５２号公報 Conventionally, techniques for joining an electrode pattern and an electrode terminal via solder or the like are disclosed in, for example, Japanese Patent Laid-Open No. 5-315517 (Patent Document 1), Japanese Patent Laid-Open No. 7-130937 (Patent Document 2), and Japanese Patent Laid-Open No. 2002-2002. No. 334964 (Patent Document 3) and JP-A-3-48452 (Patent Document 4). In the semiconductor devices disclosed in Patent Documents 1 to 4, the tip of the electrode terminal is bent along the surface of the electrode pattern, and the bent portion is joined to the electrode pattern.
JP-A-5-315517 JP-A-7-130937 JP 2002-334964 A JP-A-3-48452

しかしながら、上記特許文献１〜４に開示の電極端子が半導体素子などの小さな部品と接合される場合には、その接合強度の低下を抑制しつつ、電極端子との接合面積をさらに小さくすることが望まれている。   However, when the electrode terminal disclosed in Patent Documents 1 to 4 is bonded to a small component such as a semiconductor element, it is possible to further reduce the bonding area with the electrode terminal while suppressing a decrease in the bonding strength. It is desired.

それゆえ本発明の目的は、半導体素子において電極端子と接合されるために要する面積を縮小化し、かつ信頼性の低下を抑制する半導体装置およびその製造方法を提供することである。   SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that reduce an area required for bonding with an electrode terminal in a semiconductor element and suppress a decrease in reliability.

本発明の半導体装置は、半導体素子と、電極端子と、はんだとを備えている。電極端子は、延伸方向に沿って伸びる延伸部分を有し、かつ延伸部分の延伸方向の先端面を半導体素子の表面に対して突き合わせた状態で半導体素子と接合される。はんだは、半導体素子と電極端子とを接合する。電極端子は、電極端子のはんだで接合される領域に、延伸方向に交差する面であって、先端面と反対側に向いた面を有している。   The semiconductor device of the present invention includes a semiconductor element, an electrode terminal, and solder. The electrode terminal has an extended portion extending along the extending direction, and is joined to the semiconductor element in a state where the front end surface of the extended portion in the extending direction is abutted against the surface of the semiconductor element. The solder joins the semiconductor element and the electrode terminal. The electrode terminal has a surface that intersects the extending direction and is directed to the opposite side to the tip surface in a region where the electrode terminal is joined by solder.

本発明の半導体装置の製造方法は、以下の工程を備えている。まず、半導体素子が準備される。そして、延伸方向に沿って伸びる延伸部分と、延伸部分の延伸方向の先端面と、延伸方向に交差する面であって先端面と反対側に向いた面とを有する電極端子が準備される。そして、半導体素子の表面と電極端子の先端面とを突き合わすように配置した状態で半導体素子と電極端子とがはんだを用いて接合される。接合する工程では、反対側に向いた面にはんだが付着するように接合される。   The method for manufacturing a semiconductor device of the present invention includes the following steps. First, a semiconductor element is prepared. And the electrode terminal which has the extending | stretching part extended along an extending | stretching direction, the front-end | tip surface of the extending | stretching direction of an extending | stretching part, and the surface which cross | intersects an extending | stretching direction and faces the other end surface is prepared. And the semiconductor element and the electrode terminal are joined using solder in the state arrange | positioned so that the surface of a semiconductor element and the front end surface of an electrode terminal may be faced | matched. In the bonding step, the bonding is performed so that the solder adheres to the opposite surface.

本発明の半導体装置およびその製造方法によれば、半導体素子の表面に対して先端面が突き合わされた状態で半導体素子と接合されることによって、半導体素子において電極端子と接合されるために要する面積を縮小化できる。また、反対側に向いた面に接合されるはんだにより、電極端子が外される方向に対してはんだが抵抗力として働くので、電極端子と半導体素子との接合強度の低下を抑制できる。そのため、信頼性の低下を抑制できる半導体装置が得られる。   According to the semiconductor device and the method of manufacturing the same of the present invention, the area required for bonding to the electrode terminal in the semiconductor element by bonding the semiconductor element with the front end face being in contact with the surface of the semiconductor element. Can be reduced. In addition, the solder bonded to the surface facing the opposite side acts as a resistance force in the direction in which the electrode terminal is removed, so that a decrease in bonding strength between the electrode terminal and the semiconductor element can be suppressed. Therefore, a semiconductor device that can suppress a decrease in reliability can be obtained.

以下、図面に基づいて本発明の実施の形態を説明する。なお、以下の図面において同一または相当する部分には、同一の参照符号を付し、その説明は繰り返さない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

（実施の形態１）
図１は、本発明の実施の形態１における半導体装置の構成を概略的に示す概略断面図である。図１に示すように、本実施の形態の半導体装置１００ａは、半導体素子１１０と、電極端子１２０と、電極端子１３０と、絶縁基板１４０と、はんだ１５１〜１５６と、ヒートシンク１６０と、封止部材１７０と、ケース１８０とを主に備えている。 (Embodiment 1)
FIG. 1 is a schematic cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100a of this embodiment includes a semiconductor element 110, an electrode terminal 120, an electrode terminal 130, an insulating substrate 140, solders 151 to 156, a heat sink 160, and a sealing member. 170 and a case 180 are mainly provided.

図１に示すように、半導体素子１１０は、たとえばＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）などの大電力のスイッチング制御に用いられるパワー半導体素子（チップ）である。半導体素子１１０は、電極端子１２０、１３０と、はんだ１５１、１５２を用いて電気的に接続されている。   As shown in FIG. 1, the semiconductor element 110 is a power semiconductor element (chip) used for high-power switching control such as an IGBT (insulated gate bipolar transistor). The semiconductor element 110 is electrically connected to the electrode terminals 120 and 130 using solders 151 and 152.

電極端子１２０は、たとえば信号端子である。電極端子１３０は、たとえば主端子である。電極端子１３０において半導体素子１１０の表面に沿った一方端部の側面が半導体素子１１０と接合されている。電極端子１３０は、信号端子としての電極端子１２０よりも径が太く、電流容量が大きい主端子である。そのため、本実施の形態では、電極端子１３０と半導体素子１１０との接合をより高めるために、半導体素子１１０の表面に沿って電極端子１３０の一方端部（電極端子１３０の側面の一部）が接合されている。   The electrode terminal 120 is a signal terminal, for example. The electrode terminal 130 is a main terminal, for example. A side surface of one end portion along the surface of the semiconductor element 110 in the electrode terminal 130 is joined to the semiconductor element 110. The electrode terminal 130 is a main terminal having a larger diameter and a larger current capacity than the electrode terminal 120 as a signal terminal. Therefore, in this embodiment, in order to further enhance the bonding between the electrode terminal 130 and the semiconductor element 110, one end portion of the electrode terminal 130 (a part of the side surface of the electrode terminal 130) is formed along the surface of the semiconductor element 110. It is joined.

絶縁基板１４０は、セラミック基板１４１と、表パターン電極１４２〜１４４と、裏パターン電極１４５とを含んでいる。表パターン電極１４２〜１４４はセラミック基板１４１の表面上に形成され、裏パターン電極１４５はセラミック基板１４１の裏面上に形成されている。表パターン電極１４２〜１４４は、はんだ１５３〜１５５を用いて半導体素子１１０および電極端子１２０、１３０とそれぞれ接続されている。具体的には、電極端子１２０の一方端部（本実施の形態では図２における先端面１２１）は半導体素子１１０と接続され、電極端子１２０の他方端部（本実施の形態では図２における先端面１２１と反対側の端面を含む部分）は封止部材１７０から露出されている。電極端子１２０の一方端部と他方端部との間の部分は、表パターン電極１４３と接続されるとともにはんだ１５４で保持されている。また、電極端子１３０の一方端部は半導体素子１１０と接続され、電極端子１３０の他方端部は封止部材１７０から露出されている。電極端子１３０の一方端部と他方端部との間の部分は表パターン電極１４４と接続されるとともにはんだ１５５で保持されている。   The insulating substrate 140 includes a ceramic substrate 141, front pattern electrodes 142 to 144, and a back pattern electrode 145. The front pattern electrodes 142 to 144 are formed on the surface of the ceramic substrate 141, and the back pattern electrode 145 is formed on the back surface of the ceramic substrate 141. The front pattern electrodes 142 to 144 are connected to the semiconductor element 110 and the electrode terminals 120 and 130 using solders 153 to 155, respectively. Specifically, one end of the electrode terminal 120 (tip surface 121 in FIG. 2 in this embodiment) is connected to the semiconductor element 110, and the other end of the electrode terminal 120 (tip in FIG. 2 in this embodiment). The portion including the end surface opposite to the surface 121) is exposed from the sealing member 170. A portion between one end and the other end of the electrode terminal 120 is connected to the surface pattern electrode 143 and held by the solder 154. One end of the electrode terminal 130 is connected to the semiconductor element 110, and the other end of the electrode terminal 130 is exposed from the sealing member 170. A portion between one end and the other end of the electrode terminal 130 is connected to the surface pattern electrode 144 and is held by the solder 155.

裏パターン電極１４５は、はんだ１５６を介してヒートシンク１６０と接続されている。ヒートシンク１６０は、半導体素子１１０が発生させる熱を取り除くために設けられている。   The back pattern electrode 145 is connected to the heat sink 160 via the solder 156. The heat sink 160 is provided to remove heat generated by the semiconductor element 110.

封止部材１７０は、半導体素子１１０を封止するためのモールドされた樹脂である。封止部材１７０は、ケース１８０の内部に充填されている。封止部材１７０は、半導体素子１１０、電極端子１２０、電極端子１３０および絶縁基板１４０を覆い、電極端子１２０の他方端部と、電極端子１３０の他方端部とを露出している。   The sealing member 170 is a molded resin for sealing the semiconductor element 110. The sealing member 170 is filled in the case 180. The sealing member 170 covers the semiconductor element 110, the electrode terminal 120, the electrode terminal 130, and the insulating substrate 140, and exposes the other end of the electrode terminal 120 and the other end of the electrode terminal 130.

次に、図２〜図６を参照して、本実施の形態の電極端子１２０を説明する。図２〜図５は、図１における領域ＩＩの拡大断面図である。図６は、本発明の実施の形態１における半導体装置の電極端子の構成を示す概略斜視図である。図２〜図６に示すように、電極端子１２０は、延伸方向に沿って伸びる延伸部分１２０ａを有し、かつ延伸部分１２０ａの延伸方向の先端面１２１を半導体素子１１０の表面１１０ａに対して突き合わせた状態で半導体素子１１０と接合されている。電極端子１２０は、電極端子１２０のはんだ１５１で接合される領域１２０ｂに、延伸方向に交差する面であって、先端面１２１と反対側に向いた面１２２ａを有している。   Next, the electrode terminal 120 of this Embodiment is demonstrated with reference to FIGS. 2 to 5 are enlarged sectional views of region II in FIG. FIG. 6 is a schematic perspective view showing the configuration of the electrode terminal of the semiconductor device according to the first embodiment of the present invention. As shown in FIGS. 2 to 6, the electrode terminal 120 has an extended portion 120 a extending along the extending direction, and the front end surface 121 in the extending direction of the extended portion 120 a is abutted against the surface 110 a of the semiconductor element 110. In this state, the semiconductor element 110 is joined. The electrode terminal 120 has a surface 122 a that intersects the extending direction and is opposite to the tip surface 121 in a region 120 b that is joined by the solder 151 of the electrode terminal 120.

図７は、本発明の実施の形態１における半導体装置１００ａにおいて反対側に向いた面１２２ａを説明するための図である。図７中、Ｐ−Ｐ線は電極端子１２０の中心線を示す。「反対側に向いた面１２２ａ」は、図７に示すように、先端面１２１に平行な面であり、かつ先端面１２１の向く方向Ｓ１と反対の方向Ｓ２Ａを向いた面（つまり図７中Ｑ１−Ｑ１線に沿う面）であってもよく、また、先端面１２１に対して傾斜した面であって、かつ先端面１２１の向く方向と反対方向の成分Ｓ２Ｂ１を有する方向Ｓ２Ｂを向いた面（つまり図７中Ｑ２−Ｑ２線に沿う面）であってもよい。また、「反対側に向いた面１２２ａ」は、直線状に限定されず曲線状（たとえば図３６の反対側に向いた面１２３ａ参照）でもよい。曲線状の場合、任意の点における接線が上記Ｑ１−Ｑ１線やＱ２−Ｑ２線に対応する線であればよい。   FIG. 7 is a diagram for explaining a surface 122a facing away from the semiconductor device 100a according to the first embodiment of the present invention. In FIG. 7, the line P-P indicates the center line of the electrode terminal 120. As shown in FIG. 7, the “surface 122a facing the opposite side” is a surface parallel to the tip surface 121 and a surface facing the direction S2A opposite to the direction S1 of the tip surface 121 (that is, in FIG. 7). Q1-Q1 line), and a surface that is inclined with respect to the tip surface 121 and that faces the direction S2B having the component S2B1 in the direction opposite to the direction of the tip surface 121. (That is, the surface along the line Q2-Q2 in FIG. 7). Further, the “surface 122a facing the opposite side” is not limited to a linear shape, and may be a curved shape (for example, refer to the surface 123a facing the opposite side in FIG. 36). In the case of a curved line, the tangent line at an arbitrary point may be a line corresponding to the Q1-Q1 line or the Q2-Q2 line.

また、反対側に向いた面１２２ａは、電極端子１２０が外されるように作用する力（たとえば図２〜６において上向きの引張荷重）が加えられたときにはんだ１５１が抵抗力として働くように構成されている面であってもよい。はんだ１５１の抵抗力とは、電極端子１２０に外力が作用したときに発生するはんだ１５１のせん断力などである。   Further, the surface 122a directed to the opposite side is configured so that the solder 151 works as a resistance force when a force (for example, an upward tensile load in FIGS. 2 to 6) is applied so that the electrode terminal 120 is removed. It may be a configured surface. The resistance force of the solder 151 is a shearing force of the solder 151 generated when an external force is applied to the electrode terminal 120.

また、図２に示すように、電極端子１２０の延伸方向に沿って伸びる側面１２３、１２４には、幅の広がる部分（本実施の形態では図２においてＷ３からＷ４に広がる部分）が形成されている。言い換えると、電極端子１２０は、はんだ１５１のせん断に対する抵抗力が発生するための切欠部としての凹部１２２が形成されている。   Further, as shown in FIG. 2, on the side surfaces 123 and 124 extending along the extending direction of the electrode terminal 120, a widened portion (in this embodiment, a portion extending from W3 to W4 in FIG. 2) is formed. Yes. In other words, the electrode terminal 120 is formed with a recess 122 as a notch for generating a resistance force against the shearing of the solder 151.

なお、図７に示すように、電極端子１２０の先端面１２１の伸びる方向と、電極端子の延伸方向Ｓ１とは交差している（本実施の形態では直交している）。   As shown in FIG. 7, the direction in which the tip surface 121 of the electrode terminal 120 extends intersects the extending direction S1 of the electrode terminal (in the present embodiment, it is orthogonal).

本実施の形態では、電極端子１２０は、延伸部分１２０ａの側面１２３、１２４に凹部１２２が形成され、凹部１２２に反対側に向いた面１２２ａが形成されている。詳細には、延伸部分１２０ａは、互いに対向する２つの側面１２３、１２４を有し、２つの側面１２３、１２４の各々に凹部１２２が形成され、凹部１２２に反対側に向いた面１２２ａが形成されている。   In the present embodiment, the electrode terminal 120 has a recess 122 formed on the side surfaces 123 and 124 of the extended portion 120a, and a surface 122a facing the opposite side is formed on the recess 122. Specifically, the extended portion 120 a has two side surfaces 123 and 124 that face each other, and a concave portion 122 is formed on each of the two side surfaces 123 and 124, and a surface 122 a facing the opposite side is formed on the concave portion 122. ing.

凹部１２２は、半円状を有している。また、図２に示すように、２つの側面１２３、１２４のうちの一方の側面１２３に形成された凹部１２２と先端面１２１との距離は、２つの側面１２３、１２４のうちの他方の側面１２４に形成された凹部１２２と先端面１２１との距離と異なっている。   The recess 122 has a semicircular shape. In addition, as shown in FIG. 2, the distance between the concave portion 122 formed on one side surface 123 of the two side surfaces 123 and 124 and the tip surface 121 is the other side surface 124 of the two side surfaces 123 and 124. This is different from the distance between the concave portion 122 formed at the tip and the tip surface 121.

また、図２に示すように、電極端子１２０の先端面１２１における幅Ｗ１は、延伸部分１２０ａの先端面１２１以外の他の部分の最大の幅Ｗ２以下である。本実施の形態では、電極端子１２０のはんだ１５１で接合される領域において先端面１２１に向けて徐々に幅が狭くなるように形成されている。言い換えると、電極端子１２０は、はんだ１５１で接合される領域における延伸方向に沿って伸びる両側面１２３、１２４の幅が、先端面１２１に向けて狭くなる、先細りの形状を有している。   As shown in FIG. 2, the width W1 of the distal end surface 121 of the electrode terminal 120 is equal to or smaller than the maximum width W2 of other portions other than the distal end surface 121 of the extended portion 120a. In the present embodiment, the electrode terminal 120 is formed so that the width gradually decreases toward the distal end surface 121 in the region joined by the solder 151. In other words, the electrode terminal 120 has a tapered shape in which the widths of both side surfaces 123 and 124 extending along the extending direction in the region joined by the solder 151 become narrower toward the tip surface 121.

なお、本実施の形態では、図２〜図６に示すように、半導体素子１１０は、電極パターン（ボンディングパッド部）１１１と半導体基板１１２とを含んでいる。   In the present embodiment, as shown in FIGS. 2 to 6, the semiconductor element 110 includes an electrode pattern (bonding pad portion) 111 and a semiconductor substrate 112.

図８は、本発明の実施の形態１の変形例１における半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。図９は、本発明の実施の形態１の変形例１における半導体装置の電極端子の構成を概略的に示す斜視図である。図８および図９に示すように、電極端子１２０は、電極端子１２０のはんだ１５１で接合される領域１２０ｂにおいて、延伸方向に沿って伸びる一方側面１２４が延伸方向から先端面１２１に傾斜した面であり、他方側面１２３は延伸方向に沿って延びる、片側先細りの形状を有している。   FIG. 8 is an enlarged cross-sectional view schematically showing a configuration in the vicinity of a region where the electrode terminal and the semiconductor element are joined in the semiconductor device according to Modification 1 of Embodiment 1 of the present invention. FIG. 9 is a perspective view schematically showing a configuration of the electrode terminal of the semiconductor device in Modification 1 of Embodiment 1 of the present invention. As shown in FIGS. 8 and 9, the electrode terminal 120 is a surface in which one side surface 124 extending along the extending direction is inclined from the extending direction to the front end surface 121 in the region 120 b joined by the solder 151 of the electrode terminal 120. And the other side surface 123 has a tapered shape on one side extending along the extending direction.

図１０は、本発明の実施の形態１の変形例２における半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。図１１は、本発明の実施の形態１の変形例２における半導体装置の電極端子を概略的に示す斜視図である。図１０および図１１に示すように、電極端子１２０は、電極端子１２０の先端面１２１の幅Ｗ１は、延伸方向に伸びる幅Ｗ２と同等である。言い換えると、電極端子１２０は、電極端子１２０のはんだ１５１で接合される領域における延伸方向に沿って伸びる両側面１２３、１２４が延伸方向に沿って伸びる、ストレート形状を有している。   FIG. 10 is an enlarged cross-sectional view schematically showing a configuration in the vicinity of a region where the electrode terminal and the semiconductor element are joined in the semiconductor device according to Modification 2 of Embodiment 1 of the present invention. FIG. 11 is a perspective view schematically showing an electrode terminal of the semiconductor device in Modification 2 of Embodiment 1 of the present invention. As shown in FIGS. 10 and 11, in the electrode terminal 120, the width W1 of the tip surface 121 of the electrode terminal 120 is equal to the width W2 extending in the extending direction. In other words, the electrode terminal 120 has a straight shape in which both side surfaces 123 and 124 extending along the extending direction in the region joined by the solder 151 of the electrode terminal 120 extend along the extending direction.

次に、図１〜図１２を参照して、本実施の形態における半導体装置１００ａ、１００ｂ、１００ｃの製造方法について説明する。図１２は、本発明の実施の形態１における半導体装置の製造方法を示すフローチャートである。   Next, with reference to FIGS. 1-12, the manufacturing method of the semiconductor devices 100a, 100b, 100c in this Embodiment is demonstrated. FIG. 12 is a flowchart showing a method for manufacturing a semiconductor device in the first embodiment of the present invention.

まず、図１２に示すように、半導体素子１１０を準備する（ステップＳ１）。半導体素子１１０としては、たとえば上述したＩＧＢＴチップを準備する。ＩＧＢＴチップの表面には、エミッタ電極ボンディング領域とゲート電極ボンディング領域（本実施の形態における電極パターン１１１）とが形成され、その裏面にはコレクタ電極ボンディング領域が形成されている。そして、半導体素子１１０と電極端子１２０、１３０との接続のためにはんだ１５１、１５２を使用するため（後述するステップＳ５）、エミッタ電極ボンディング領域およびゲート電極ボンディング領域の表面にはたとえばニッケル層が形成されている。また、半導体素子１１０の裏面に形成されたコレクタ電極ボンディング領域と表パターン電極１４２との接続のためにはんだ１５３を使用するため（後述するステップＳ４）、コレクタ電極ボンディング領域の表面にはたとえばニッケル層が形成されている。   First, as shown in FIG. 12, the semiconductor element 110 is prepared (step S1). As the semiconductor element 110, for example, the above-described IGBT chip is prepared. An emitter electrode bonding region and a gate electrode bonding region (electrode pattern 111 in the present embodiment) are formed on the surface of the IGBT chip, and a collector electrode bonding region is formed on the back surface thereof. In order to use the solders 151 and 152 for connecting the semiconductor element 110 and the electrode terminals 120 and 130 (step S5 described later), for example, a nickel layer is formed on the surfaces of the emitter electrode bonding region and the gate electrode bonding region. Has been. Further, since the solder 153 is used to connect the collector electrode bonding region formed on the back surface of the semiconductor element 110 and the surface pattern electrode 142 (step S4 described later), for example, a nickel layer is formed on the surface of the collector electrode bonding region. Is formed.

次に、絶縁基板１４０を準備する（ステップＳ２）。絶縁基板１４０は、たとえばセラミック基板１４１を挟んでその表面上に表パターン電極１４２〜１４４が形成されるとともに、裏面上に裏パターン電極１４５が形成された構成となっている。表パターン電極１４２〜１４４および裏面パターン電極１４５は、たとえば銅やアルミニウムの板（箔）からなっている。表および裏パターン電極１４２〜１４５とセラミック基板１４１とは、活性金属などのロウ材により接合されている。また、ステップＳ２では、絶縁基板１４０の表パターン電極１４２における半導体素子１１０を搭載する部分に、クリームはんだなどのはんだ１５３をスクリーン印刷により塗布する。   Next, the insulating substrate 140 is prepared (step S2). The insulating substrate 140 has a configuration in which, for example, front pattern electrodes 142 to 144 are formed on the front surface of the ceramic substrate 141 and a back pattern electrode 145 is formed on the back surface. The front pattern electrodes 142 to 144 and the back surface pattern electrode 145 are made of, for example, a copper (aluminum) plate (foil). The front and back pattern electrodes 142 to 145 and the ceramic substrate 141 are joined by a brazing material such as an active metal. In step S2, solder 153 such as cream solder is applied to the portion of the insulating substrate 140 where the semiconductor element 110 is mounted on the surface pattern electrode 142 by screen printing.

次に、ヒートシンク１６０を準備する（ステップＳ３）。ヒートシンク１６０は、たとえば銅やアルミニウム、またはその合金からなるブロックを用いることができる。また、ステップＳ３では、ヒートシンク１６０の表面、すなわち絶縁基板１４０が搭載される部分に、クリームはんだなどのはんだ１５６をスクリーン印刷により塗布する。   Next, the heat sink 160 is prepared (step S3). As the heat sink 160, for example, a block made of copper, aluminum, or an alloy thereof can be used. In step S3, solder 156 such as cream solder is applied to the surface of the heat sink 160, that is, the portion on which the insulating substrate 140 is mounted, by screen printing.

次に、はんだ１５３が塗布された絶縁基板１４０の表パターン電極１４２上に半導体素子１１０を載置する。次いで、この半導体素子１１０が載置された絶縁基板１４０を、はんだ１５６が塗布されたヒートシンク１６０の表面上に載置する（ステップＳ４）。   Next, the semiconductor element 110 is placed on the surface pattern electrode 142 of the insulating substrate 140 to which the solder 153 is applied. Next, the insulating substrate 140 on which the semiconductor element 110 is placed is placed on the surface of the heat sink 160 to which the solder 156 is applied (step S4).

次に、絶縁基板１４０上に載置された半導体素子１１０表面のエミッタ電極ボンディング領域およびゲート電極ボンディング領域（本実施の形態の電極パターン１１１に相当）上、および電極端子が接続される絶縁基板１４０の表パターン電極上１４３、１４４に、ディスペンサなどを使用して、はんだ１５１、１５２、１５４、１５５を適量塗布する（ステップＳ５）。   Next, the insulating substrate 140 on the emitter electrode bonding region and the gate electrode bonding region (corresponding to the electrode pattern 111 of the present embodiment) on the surface of the semiconductor element 110 placed on the insulating substrate 140 and the electrode terminals are connected. An appropriate amount of solder 151, 152, 154, 155 is applied to the surface pattern electrodes 143, 144 using a dispenser or the like (step S5).

次に、電極端子１２０、１３０を準備する（ステップＳ６）。ここで、電極端子１２０は、図１に示すように信号端子として半導体素子１１０に接続させるもので、延伸方向に沿って伸びる延伸部分１２０ａと、延伸部分１２０ａの延伸方向の先端面１２１と、延伸方向に交差する面であって先端面１２１と反対側に向いた面１２２ａとを有する。そして、半導体素子１１０における接続領域を小さくするため、先端面１２１の幅が延伸部分１２０ａの最大の幅以下である電極端子１２０を準備することが好ましい。本実施の形態では、電極端子１２０は半導体素子１１０のゲート電極ボンディング領域に接続されている。また、電極端子１３０は、図１に示す主端子として半導体素子１１０のエミッタ電極ボンディング領域に接続されている。   Next, electrode terminals 120 and 130 are prepared (step S6). Here, the electrode terminal 120 is connected to the semiconductor element 110 as a signal terminal as shown in FIG. 1, and an extended portion 120a extending along the extending direction, a front end surface 121 of the extending portion 120a in the extending direction, and an extending direction It has a surface 122a that intersects the direction and faces the tip surface 121 and the opposite side. And in order to make the connection area | region in the semiconductor element 110 small, it is preferable to prepare the electrode terminal 120 whose width | variety of the front end surface 121 is below the largest width of the extending | stretching part 120a. In the present embodiment, the electrode terminal 120 is connected to the gate electrode bonding region of the semiconductor element 110. The electrode terminal 130 is connected to the emitter electrode bonding region of the semiconductor element 110 as the main terminal shown in FIG.

たとえば、図６、図９または図１１に示す信号端子としての電極端子１２０は、その材料として銅などの薄板の平板を、金型を用いて打抜くようにして成型する、いわゆる打抜き加工により形成され、電極端子１３０についても同様である。   For example, the electrode terminal 120 as a signal terminal shown in FIG. 6, FIG. 9 or FIG. 11 is formed by a so-called punching process in which a thin flat plate of copper or the like is formed as a material by punching using a mold. The same applies to the electrode terminal 130.

次に、表面にはんだ１５１、１５２、１５４、１５５が適量塗布された半導体素子１１０、および絶縁基板１４０の表パターン電極１４３、１４４上に、電極端子１２０、１３０を載置して、治具などを使用して動かない（位置ズレしない）ように固定する（ステップＳ７）。つまり、電極端子１２０においては、その先端面１２１とその反対側の端面との間の部分を表パターン電極１４３上に配置するとともに、先端面１２１は半導体素子１１０のゲート電極ボンディング領域に配置することで、電極端子１２０の先端面１２１と半導体素子１１０の表面１１０ａとを突き合わすような状態とする。また電極端子１３０においては、一方端部と他方端部との間の部分を表パターン電極１４４上に配置するとともに、一方端部は半導体素子１１０のエミッタ電極ボンディング領域に配置して、その位置が保持されるようにする。   Next, the electrode terminals 120 and 130 are placed on the semiconductor element 110 having a proper amount of solder 151, 152, 154, and 155 coated on the surface, and the surface pattern electrodes 143 and 144 of the insulating substrate 140, and a jig or the like. Is fixed so that it does not move (is not displaced) (step S7). That is, in the electrode terminal 120, a portion between the tip surface 121 and the opposite end surface is disposed on the surface pattern electrode 143, and the tip surface 121 is disposed in the gate electrode bonding region of the semiconductor element 110. Thus, the tip surface 121 of the electrode terminal 120 and the surface 110a of the semiconductor element 110 are brought into contact with each other. In the electrode terminal 130, a portion between one end portion and the other end portion is disposed on the surface pattern electrode 144, and one end portion is disposed in the emitter electrode bonding region of the semiconductor element 110, and the position thereof is To be retained.

次に、上述のようにしてはんだを介して組み立てられ、ヒートシンク１６０、絶縁基板１４０、半導体素子１１０、電極端子１２０、１３０を主要部品とした構成は、リフロー処理により、はんだ１５１〜１５６の溶融を経て、各主要部品を所定の位置に接合・固着する（ステップＳ８）。   Next, assembling via solder as described above, the configuration including the heat sink 160, the insulating substrate 140, the semiconductor element 110, and the electrode terminals 120 and 130 as main components is obtained by melting the solders 151 to 156 by reflow processing. Then, each main part is joined and fixed to a predetermined position (step S8).

なお、このステップＳ８において、少なくとも電極端子１２０における反対側に向いた面１２２ａに、はんだ１５１が付着するように接合させることにより、電極端子１２０に延伸方向の上方（図２において上向き）から引張荷重が加えられたときに、反対側に向いた面１２２ａに付着したはんだ１５１のせん断力を発生させることができる。そして、このような接合状態は、はんだ１５１の塗布量や濡れ性などの特性を調整して、最適化することによって得られる。   In this step S8, at least the surface 122a facing the opposite side of the electrode terminal 120 is joined so that the solder 151 adheres, whereby the tensile load is applied to the electrode terminal 120 from above in the extending direction (upward in FIG. 2). Is applied, it is possible to generate a shearing force of the solder 151 adhering to the opposite surface 122a. Such a joined state can be obtained by adjusting and optimizing characteristics such as the application amount and wettability of the solder 151.

次に、内部に絶縁基板１４０、半導体素子１１０および電極端子１２０、１３０を収容するための樹脂からなるケース１８０をヒートシンク１６０に接続固定し、ケース１８０の内部に封止部材１７０を充填することにより封止する（ステップＳ９）。このとき、電極端子１２０の先端面１２１の反対側の端面、および電極端子１３０の他方端部はケース１８０の外に配置され、封止部材１７０からは露出している。   Next, a case 180 made of resin for housing the insulating substrate 140, the semiconductor element 110, and the electrode terminals 120, 130 is connected and fixed to the heat sink 160, and the sealing member 170 is filled in the case 180. Sealing is performed (step S9). At this time, the end surface of the electrode terminal 120 opposite to the tip surface 121 and the other end of the electrode terminal 130 are disposed outside the case 180 and exposed from the sealing member 170.

なお、上述のようなケース１８０を接着して、これに封止樹脂を充填して封止する方法に代えて、インジェクションモールド法により、ケースを用いず、金型を使って直接封止樹脂によって封止する方法を採用してもよい。   In addition, instead of the method of adhering the case 180 as described above and filling and sealing it with a sealing resin, the injection molding method is used, the case is not used, and the mold is used directly with the sealing resin. You may employ | adopt the method of sealing.

以上の工程（ステップＳ１〜ステップＳ９）を実施することによって、図１〜図５、図８および図１０に示す半導体装置１００ａ、１００ｂ、１００ｃを製造することができる。   By performing the above steps (step S1 to step S9), the semiconductor devices 100a, 100b, and 100c shown in FIGS. 1 to 5, 8, and 10 can be manufactured.

次に、本実施の形態における半導体装置１００ａ、１００ｂ、１００ｃの効果について説明する。図３７および図３８は、上記特許文献１〜３に開示されている先端部がＬ字状に折り曲げられた電極端子を備えた半導体装置を概略的に示す拡大断面図である。まず、図１〜６、図３７および図３８を参照して、半導体素子１１０において電極端子１２０と接合されるために要する面積を縮小化する効果について説明する。   Next, effects of the semiconductor devices 100a, 100b, and 100c in the present embodiment will be described. FIG. 37 and FIG. 38 are enlarged cross-sectional views schematically showing a semiconductor device provided with an electrode terminal whose front end portion disclosed in Patent Documents 1 to 3 is bent in an L shape. First, with reference to FIGS. 1 to 6, FIG. 37, and FIG. 38, an effect of reducing the area required for bonding to the electrode terminal 120 in the semiconductor element 110 will be described.

図３７および図３８に示す半導体装置２００ａは、半導体素子２１０と、上記特許文献１〜３に開示されている電極端子２２０と、はんだ２５１とを備えている。電極端子２２０は、Ｌ字状に折り曲げられた部分（半導体素子２１０の表面に沿った部分）で半導体素子２１０と接合されている。はんだ２５１は、半導体素子２１０と電極端子２２０とを接合している。なお、半導体素子２１０は、電極パターン２１１と半導体基板２１２とを含んでいる。   A semiconductor device 200a shown in FIGS. 37 and 38 includes a semiconductor element 210, an electrode terminal 220 disclosed in Patent Documents 1 to 3, and a solder 251. The electrode terminal 220 is joined to the semiconductor element 210 at a portion bent along an L shape (a portion along the surface of the semiconductor element 210). The solder 251 joins the semiconductor element 210 and the electrode terminal 220. The semiconductor element 210 includes an electrode pattern 211 and a semiconductor substrate 212.

本実施の形態の変形例２の半導体装置１００ｃでは、電極端子１２０がストレート形状であるので、電極端子１２０の正面１２５および背面１２６（図３〜図５参照）において半導体素子１１０へ接合される部分（幅）は図３７および図３８に示す電極端子２２０と同等であるが、電極端子１２０の側面１２３、１２４において半導体素子１１０へ接合される部分（長さ）は図３７および図３８示す電極端子２２０の約５０％にできる。そのため、特許文献１〜３の電極端子２２０の半導体素子２１０への接触面積に対して、変形例２の電極端子１２０の半導体素子１１０への接触面積を約５０％にまで低減できる。その結果、上記特許文献１〜３の半導体素子２１０においてはんだ２５１を用いて電極端子２２０を接合するために要する面積Ｓ２００（図３８参照）を１００％とすると、変形例２の半導体装置１００ｃの半導体素子１１０における電極端子１２０を接合するために要する面積（接合面積）は約５０％まで縮小できる。   In the semiconductor device 100c according to the second modification of the present embodiment, the electrode terminal 120 has a straight shape, and therefore the portion bonded to the semiconductor element 110 on the front surface 125 and the back surface 126 (see FIGS. 3 to 5) of the electrode terminal 120. (Width) is the same as that of the electrode terminal 220 shown in FIGS. 37 and 38, but the portion (length) joined to the semiconductor element 110 on the side surfaces 123 and 124 of the electrode terminal 120 is the electrode terminal shown in FIGS. About 50% of 220. Therefore, the contact area of the electrode terminal 120 of Modification 2 to the semiconductor element 110 can be reduced to about 50% with respect to the contact area of the electrode terminal 220 of Patent Documents 1 to 3 to the semiconductor element 210. As a result, assuming that the area S200 (see FIG. 38) required for joining the electrode terminal 220 using the solder 251 in the semiconductor element 210 of Patent Documents 1 to 3 is 100%, the semiconductor of the semiconductor device 100c of Modification 2 The area (joining area) required for joining the electrode terminals 120 in the element 110 can be reduced to about 50%.

さらに、本実施の形態の変形例１の半導体装置１００ｂの電極端子１２０は片側先細り形状であるので、一方側面１２４の半導体素子１１０への接触位置により、上記特許文献１〜３の電極端子を備える場合と比較して、半導体素子１１０における電極端子１２０を接合するために要する面積を約４４％にまで低減できる。   Furthermore, since the electrode terminal 120 of the semiconductor device 100b according to the first modification of the present embodiment is tapered on one side, the electrode terminals described in Patent Documents 1 to 3 are provided depending on the contact position of the one side surface 124 with the semiconductor element 110. Compared to the case, the area required for joining the electrode terminals 120 in the semiconductor element 110 can be reduced to about 44%.

さらには、本実施の形態の半導体装置１００ａの電極端子１２０は両側先細り形状であるので、両側面１２３、１２４の半導体素子１１０への接触位置により、上記特許文献１〜３の電極端子を備える場合と比較して、半導体素子１１０における電極端子１２０を接合するために要する面積を約３０％にまで低減できる。   Furthermore, since the electrode terminal 120 of the semiconductor device 100a according to the present embodiment is tapered on both sides, the electrode terminals disclosed in Patent Documents 1 to 3 are provided depending on the contact positions of the side surfaces 123 and 124 with the semiconductor element 110. As compared with the above, the area required for joining the electrode terminals 120 in the semiconductor element 110 can be reduced to about 30%.

続いて、図１〜１０および図３９を参照して、電極端子１２０に引張荷重（図２において上向きの力）が加えられたときの効果について説明する。図３９は、比較例を示す半導体装置における電極端子近傍の構成を概略的に示す拡大断面図である。比較例の半導体装置２００ｂは、反対側に向いた面が形成されていない先細り形状の電極端子２２０を備えている。具体的には、比較例の電極端子２２０は本実施の形態の電極端子１２０と同様の構成を備えているが、電極端子２２０において凹部１２２が形成されていない点においてのみ異なる。そのため、比較例の半導体装置２００ｂの半導体素子２１０において電極端子２２０と接合するために要する面積は、本実施の形態の半導体素子１１０において電極端子１２０と接合するために要する面積と同じである。   Subsequently, an effect when a tensile load (upward force in FIG. 2) is applied to the electrode terminal 120 will be described with reference to FIGS. FIG. 39 is an enlarged cross-sectional view schematically showing a configuration in the vicinity of an electrode terminal in a semiconductor device showing a comparative example. The semiconductor device 200b of the comparative example includes a tapered electrode terminal 220 in which a surface facing the opposite side is not formed. Specifically, the electrode terminal 220 of the comparative example has the same configuration as the electrode terminal 120 of the present embodiment, but differs only in that the recess 122 is not formed in the electrode terminal 220. Therefore, the area required for bonding with the electrode terminal 220 in the semiconductor element 210 of the semiconductor device 200b of the comparative example is the same as the area required for bonding with the electrode terminal 120 in the semiconductor element 110 of the present embodiment.

比較例の半導体装置２００ｂにおいて、先端面の幅が０．７ｍｍ、厚み（両側面の厚み）が０．３ｍｍの電極端子２２０とし、Ｓｎ（スズ）−Ａｇ（銀）系の鉛フリーはんだをはんだ２５１とする。この場合、電極端子２２０に引張荷重（図３９において上向きの力）を作用させると、約３０Ｎの荷重で電極端子が抜け落ちる。   In the semiconductor device 200b of the comparative example, an electrode terminal 220 having a tip surface width of 0.7 mm and a thickness (thickness of both side surfaces) of 0.3 mm is used, and Sn (tin) -Ag (silver) -based lead-free solder is soldered. 251. In this case, when a tensile load (upward force in FIG. 39) is applied to the electrode terminal 220, the electrode terminal falls off with a load of about 30N.

一方、図１〜図６に示す本実施の形態の半導体装置１００ａの電極端子１２０の反対側に向いた面１２２ａに付着しているはんだを投影させて、その面積を算出すると、せん断に対する抵抗力が発生するはんだ１５１の面積は、たとえば合計で０．２ｍｍ2となる。そのため、本実施の形態で比較例のはんだ２５１と同じ材料のはんだ１５１を用いると、はんだ１５１の引張強度が７０ＭＰａ（７０Ｎ／ｍｍ2）であるので、算出された面積に引張強度を乗じると、１４Ｎの引張荷重が得られる。すなわち、本実施の形態では、比較例に比べて引張荷重が約４０％増大する。したがって、本実施の形態の電極端子１２０に熱サイクル等により作用する引張荷重（図２において上向きの力）が加えられると、反対側に向いた面１２２ａに付着しているはんだ１５１のせん断力により、半導体素子１１０の表面１１０ａ（はんだ１５１との接合界面）から電極端子１２０が抜け落ちることを抑制できる。 On the other hand, when solder is adhered to the surface 122a facing the opposite side of the electrode terminal 120 of the semiconductor device 100a of the present embodiment shown in FIGS. For example, the total area of the solder 151 in which the above-mentioned is generated is 0.2 mm 2 . Therefore, when the solder 151 of the same material as the solder 251 of the comparative example is used in the present embodiment, the tensile strength of the solder 151 is 70 MPa (70 N / mm 2 ). A 14N tensile load is obtained. That is, in this embodiment, the tensile load is increased by about 40% compared to the comparative example. Therefore, when a tensile load (upward force in FIG. 2) acting on the electrode terminal 120 of the present embodiment due to a thermal cycle or the like is applied, the shearing force of the solder 151 attached to the opposite surface 122a is applied. The electrode terminal 120 can be prevented from falling off from the surface 110a of the semiconductor element 110 (bonding interface with the solder 151).

以上説明したように、本実施の形態における半導体装置１００ａ、１００ｂ、１００ｃによれば、半導体素子１１０と、延伸方向に沿って伸びる延伸部分１２０ａを有し、かつ延伸部分１２０ａの延伸方向の先端面１２１を半導体素子１１０の表面１１０ａに対して突き合わせた状態で半導体素子１１０と接合される電極端子１２０と、半導体素子１１０と電極端子１２０とを接合するはんだ１５１とを備え、電極端子１２０は、電極端子１２０のはんだ１５１で接合される領域１２０ｂに、延伸方向に交差する面であって、先端面１２１と反対側に向いた面１２２ａを有している。   As described above, according to the semiconductor devices 100a, 100b, and 100c in the present embodiment, the semiconductor element 110 has the extended portion 120a extending along the extending direction, and the extending portion 120a has a front end surface in the extending direction. The electrode terminal 120 is bonded to the semiconductor element 110 in a state in which 121 is in contact with the surface 110a of the semiconductor element 110, and the solder 151 is used to bond the semiconductor element 110 and the electrode terminal 120. A region 120b joined by the solder 151 of the terminal 120 has a surface 122a that intersects the extending direction and faces away from the tip surface 121.

本実施の形態における半導体装置１００ａ、１００ｂ、１００ｃは、半導体素子１１０の表面１１０ａに対して電極端子１２０の先端面１２１が突き合わされた状態で電極端子１２０と半導体素子１１０とが接合されることによって、半導体素子１１０における電極端子１２０との接合面積を縮小化できる。本実施の形態では、電極端子１２０は信号端子として用いられ、主端子として用いられる電極端子１３０よりも電流容量が少ない。そのため、接合面積を縮小化した形状の電極端子１２０を用いることにより、性能を維持するとともに、半導体装置１００ａ、１００ｂ、１００ｃにおいて電極端子１２０を接合するために要する面積の縮小化を図ることができる。よって、半導体素子１１０などの小さな部品においてはんだ１５１を用いて電極端子１２０を接合する場合や、半導体素子１１０において電極端子１２０を接合する面積が限られている場合に、本実施の形態の電極端子１２０を用いることにより、接合するための面積を縮小化できる。   The semiconductor devices 100a, 100b, and 100c in the present embodiment are formed by joining the electrode terminal 120 and the semiconductor element 110 in a state where the front end surface 121 of the electrode terminal 120 is abutted against the surface 110a of the semiconductor element 110. In addition, the bonding area of the semiconductor element 110 with the electrode terminal 120 can be reduced. In the present embodiment, the electrode terminal 120 is used as a signal terminal and has a smaller current capacity than the electrode terminal 130 used as a main terminal. Therefore, by using the electrode terminal 120 having a shape in which the bonding area is reduced, performance can be maintained and the area required for bonding the electrode terminal 120 in the semiconductor devices 100a, 100b, and 100c can be reduced. . Therefore, when the electrode terminal 120 is bonded using the solder 151 in a small component such as the semiconductor element 110, or when the area where the electrode terminal 120 is bonded is limited in the semiconductor element 110, the electrode terminal of the present embodiment. By using 120, the area for joining can be reduced.

また、電極端子１２０に引張荷重が作用されたときに、反対側に向いた面１２２ａに付着したはんだ１５１のせん断に対する抵抗力によって、電極端子１２０と半導体素子１１０との接合強度の低下を抑制できる。特に、上記特許文献１〜４は、電極端子を折り曲げてはんだとの接合面積を増加させることにより、半導体素子１１０と電極端子１２０との接合強度を高めている技術であるのに対して、本実施の形態では、電極端子１２０に引張荷重が作用した場合にはんだ１５１にせん断に対する抵抗力が発生するように半導体装置１００ａ、１００ｂ、１００ｃを構成している。また、半導体素子１１０において電極端子１２０を接合するために要する面積を縮小化するために、電極端子の先端部を半導体素子に沿うように接合した場合と比較して、反対側に向いた面１２２ａに付着したはんだ１５１のせん断に対する抵抗力により、電極端子１２０と半導体素子１１０との接合強度を向上できる。よって、電極端子１２０がはんだ１５１との接合界面から抜け落ちることを抑制でき、信頼性の低下を抑制できる半導体装置１００ａ、１００ｂ、１００ｃが得られる。   In addition, when a tensile load is applied to the electrode terminal 120, a decrease in the bonding strength between the electrode terminal 120 and the semiconductor element 110 can be suppressed by the resistance to shearing of the solder 151 attached to the opposite surface 122a. . In particular, the above Patent Documents 1 to 4 are techniques that increase the bonding strength between the semiconductor element 110 and the electrode terminal 120 by bending the electrode terminal to increase the bonding area with the solder. In the embodiment, the semiconductor devices 100 a, 100 b, and 100 c are configured so that a resistance to shearing is generated in the solder 151 when a tensile load is applied to the electrode terminal 120. Further, in order to reduce the area required for joining the electrode terminal 120 in the semiconductor element 110, the surface 122a facing the opposite side compared to the case where the tip end of the electrode terminal is joined along the semiconductor element. The bonding strength between the electrode terminal 120 and the semiconductor element 110 can be improved by the resistance against the shearing of the solder 151 attached to the electrode. Therefore, the semiconductor devices 100a, 100b, and 100c that can suppress the electrode terminal 120 from falling off from the bonding interface with the solder 151 and suppress the decrease in reliability can be obtained.

上記半導体装置１００ａ、１００ｂ、１００ｃにおいて好ましくは、電極端子１２０の先端面１２１における幅Ｗ１は、延伸部分１２０ａの先端面１２１以外の他の部分の最大の幅Ｗ２以下である。これにより、半導体素子１１０において電極端子１２０と接合されるために要する面積をより縮小化できる。   Preferably, in the semiconductor devices 100a, 100b, and 100c, the width W1 of the tip surface 121 of the electrode terminal 120 is equal to or less than the maximum width W2 of other portions other than the tip surface 121 of the extended portion 120a. Thereby, the area required for joining with the electrode terminal 120 in the semiconductor element 110 can be further reduced.

上記半導体装置１００ａ、１００ｂ、１００ｃにおいて好ましくは、延伸部分１２０ａの側面１２３、１２４に凹部１２２が形成され、凹部１２２に反対側に向いた面１２２ａが形成されている。これにより、電極端子１２０と半導体素子１１０との接合強度の低下を抑制できる構成が実現できる。   In the semiconductor devices 100a, 100b, and 100c, the recess 122 is preferably formed on the side surfaces 123 and 124 of the extended portion 120a, and the surface 122a facing the opposite side is formed on the recess 122. Thereby, the structure which can suppress the fall of the joint strength of the electrode terminal 120 and the semiconductor element 110 is realizable.

上記半導体装置１００ａ、１００ｂ、１００ｃにおいて好ましくは、延伸部分１２０ａは、互いに対向する２つの側面１２３、１２４を有し、２つの側面１２３、１２４の各々に凹部１２２が形成され、凹部１２２に反対側に向いた面１２２ａが形成されている。これにより、電極端子１２０と半導体素子１１０との接合強度の低下をさらに抑制できる構成が実現できる。   Preferably, in the semiconductor devices 100a, 100b, and 100c, the extended portion 120a has two side surfaces 123 and 124 that face each other, and a concave portion 122 is formed on each of the two side surfaces 123 and 124, and the opposite side to the concave portion 122. A surface 122a facing toward is formed. Thereby, the structure which can suppress further the fall of the joint strength of the electrode terminal 120 and the semiconductor element 110 is realizable.

上記半導体装置１００ａ、１００ｂ、１００ｃにおいて好ましくは、２つの側面１２３、１２４のうちの一方の側面１２３に形成された凹部１２２と先端面１２１との距離Ｌ１２３は、２つの側面１２３、１２４のうちの他方の側面１２４に形成された凹部１２２と先端面１２１との距離Ｌ１２４と異なっている。これにより、電極端子１２０の強度を維持するとともに、凹部１２２をより大きく設けることができるので、電極端子１２０と半導体素子１１０との接合強度の低下をより抑制できる。   Preferably, in the semiconductor devices 100a, 100b, and 100c, the distance L123 between the concave portion 122 formed on one side surface 123 of the two side surfaces 123 and 124 and the front end surface 121 is the same as that of the two side surfaces 123 and 124. This is different from the distance L124 between the concave portion 122 formed on the other side surface 124 and the tip surface 121. Accordingly, the strength of the electrode terminal 120 can be maintained and the concave portion 122 can be provided larger, so that a decrease in the bonding strength between the electrode terminal 120 and the semiconductor element 110 can be further suppressed.

上記半導体装置１００ａ、１００ｂ、１００ｃにおいて好ましくは、凹部１２２は、半円状である。これにより、電極端子１２０と半導体素子１１０との接合強度の低下を抑制できる構成が実現できる。   In the semiconductor devices 100a, 100b, and 100c, the recess 122 is preferably semicircular. Thereby, the structure which can suppress the fall of the joint strength of the electrode terminal 120 and the semiconductor element 110 is realizable.

本発明の半導体装置１００ａ、１００ｂ、１００ｃの製造方法によれば、半導体素子１１０を準備する工程（ステップＳ１）と、延伸方向に沿って伸びる延伸部分１２０ａと、延伸部分１２０ａの延伸方向の先端面１２１と、延伸方向に交差する面であって先端面１２１と反対側に向いた面１２２ａとを有する電極端子１２０を準備する工程（ステップＳ６）と、半導体素子１１０の表面１１０ａと電極端子１２０の先端面１２１とを突き合わすように配置した状態で半導体素子１１０と電極端子１２０とをはんだ１５１を用いて接合する工程（ステップＳ８）とを備え、接合する工程（ステップＳ８）では、反対側に向いた面１２２ａにはんだ１５１が付着するように接合する。   According to the manufacturing method of the semiconductor devices 100a, 100b, and 100c of the present invention, the step of preparing the semiconductor element 110 (Step S1), the extending portion 120a extending along the extending direction, and the front end surface of the extending portion 120a in the extending direction 121, a step of preparing an electrode terminal 120 having a surface 122a that intersects the extending direction and faces away from the front end surface 121 (step S6), the surface 110a of the semiconductor element 110, and the electrode terminal 120 A step (step S8) of joining the semiconductor element 110 and the electrode terminal 120 using the solder 151 in a state of being disposed so as to face the tip surface 121. In the step of joining (step S8), It joins so that the solder 151 may adhere to the surface 122a which faced.

本実施の形態における半導体装置１００ａ、１００ｂ、１００ｃの製造方法は、接合する工程（ステップＳ８）において半導体素子１１０の表面１１０ａに対して電極端子１２０の先端面１２１が突き合わされた状態で電極端子１２０と半導体素子とを接合することによって、半導体素子１１０における電極端子１２０を接合するために要する面積を縮小化できる。特に、半導体素子１１０などの小さな部品においてはんだ１５１を用いて電極端子１２０を接合する場合や、半導体素子１１０において電極端子１２０を接合する面積が限られている場合に、本実施の形態の接合するための面積を縮小化できる電極端子１２０を好適に用いることができる。   In the manufacturing method of semiconductor devices 100a, 100b, and 100c in the present embodiment, electrode terminal 120 is in a state where tip surface 121 of electrode terminal 120 is abutted against surface 110a of semiconductor element 110 in the bonding step (step S8). By joining the semiconductor element and the semiconductor element, the area required for joining the electrode terminal 120 in the semiconductor element 110 can be reduced. In particular, when the electrode terminal 120 is bonded using the solder 151 in a small component such as the semiconductor element 110 or when the area where the electrode terminal 120 is bonded is limited in the semiconductor element 110, the bonding according to the present embodiment is performed. Therefore, the electrode terminal 120 capable of reducing the area for the purpose can be preferably used.

また、接合する工程（ステップＳ８）において反対側に向いた面１２２ａにはんだ１５１が付着するように接合することによって、反対側に向いた面１２２ａに付着したはんだ１５１のせん断に対する抵抗力を利用できる。すなわち、電極端子１２０に熱ストレス等により引張荷重が作用されたときに、反対側に向いた面１２２ａに付着したはんだ１５１のせん断に対する抵抗力によって、電極端子１２０と半導体素子１１０との接合強度の低下を抑制できる。特に、半導体素子１１０との接合部の面積を縮小化するために、電極端子の先端部を折り曲げずに用いた場合と比較して、電極端子１２０と半導体素子１１０との接合強度を向上できるので、電極端子１２０がはんだ１５１との接合界面から抜け落ちることを抑制できる。よって、信頼性の低下を抑制できる半導体装置１００ａ、１００ｂ、１００ｃが得られる。   Further, by joining so that the solder 151 adheres to the opposite surface 122a in the joining step (step S8), the resistance of the solder 151 attached to the opposite surface 122a to the shearing can be utilized. . That is, when a tensile load is applied to the electrode terminal 120 due to thermal stress or the like, the bonding strength between the electrode terminal 120 and the semiconductor element 110 is reduced by the resistance to shearing of the solder 151 attached to the opposite surface 122a. Reduction can be suppressed. In particular, the bonding strength between the electrode terminal 120 and the semiconductor element 110 can be improved as compared with the case where the tip portion of the electrode terminal is used without being bent in order to reduce the area of the bonding portion with the semiconductor element 110. The electrode terminal 120 can be prevented from falling off from the joint interface with the solder 151. Therefore, semiconductor devices 100a, 100b, and 100c that can suppress a decrease in reliability are obtained.

（実施の形態２）
図１３は、本発明の実施の形態２の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。図１４は、本発明の実施の形態２における半導体装置の電極端子の構成を概略的に示す斜視図である。図１３および図１４を参照して、本実施の形態における半導体装置１００ｄは、基本的には実施の形態１の半導体装置１００ａと同様の構成を備えているが、電極端子１２０が対向する側面１２３、１２４のうちの一方の側面１２３に形成された凹部１２２と先端面１２１との距離Ｌ１２３と、他方の側面１２４に形成された凹部１２２と先端面１２１との距離Ｌ１２４とが同等である点においてのみ異なる。 (Embodiment 2)
FIG. 13 is an enlarged cross-sectional view schematically showing a configuration in the vicinity of a region where the electrode terminal and the semiconductor element are joined in the semiconductor device according to the second embodiment of the present invention. FIG. 14 is a perspective view schematically showing the configuration of the electrode terminal of the semiconductor device according to the second embodiment of the present invention. Referring to FIGS. 13 and 14, semiconductor device 100 d in the present embodiment has basically the same configuration as semiconductor device 100 a in the first embodiment, but has side surface 123 on which electrode terminal 120 faces. , 124, the distance L123 between the concave portion 122 formed on one side surface 123 and the front end surface 121 is equal to the distance L124 between the concave portion 122 formed on the other side surface 124 and the front end surface 121. Only different.

図１５、１７、１９、２１、２３、２５、２７、２９および３１は、本発明の実施の形態２の変形例１〜９の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。図１６、１８、２０、２２、２４、２６、２８、３０および３２は、本発明の実施の形態２の変形例１〜９における半導体装置の電極端子の構成を概略的に示す斜視図である。   15, 17, 19, 21, 23, 25, 27, 29, and 31 show the vicinity of the region where the electrode terminal and the semiconductor element are joined in the semiconductor device of Modifications 1 to 9 of the second embodiment of the present invention. It is an expanded sectional view showing roughly the composition. 16, 18, 20, 22, 24, 26, 28, 30 and 32 are perspective views schematically showing the configuration of the electrode terminals of the semiconductor device in Modifications 1 to 9 of Embodiment 2 of the present invention. .

図１５および図１６に示すように、電極端子１２０はストレート形状であってもよく、片側先細り形状であってもよい（図示せず）。   As shown in FIGS. 15 and 16, the electrode terminal 120 may have a straight shape or a tapered shape on one side (not shown).

また図１７および図１８に示すように、電極端子１２０の凹部１２２は矩形状であってもよい。また、電極端子１２０の凹部１２２は、矩形状と半円状との両方が形成されていてもよい（図示せず）。   As shown in FIGS. 17 and 18, the recess 122 of the electrode terminal 120 may be rectangular. Moreover, both the rectangular shape and the semicircle shape may be formed in the recessed part 122 of the electrode terminal 120 (not shown).

また図１９および図２０に示すように、電極端子１２０は、延伸方向に沿って伸びる対向する側面１２３、１２４のうちの一方の側面１２４のみに凹部１２２が形成されていてもよい。図２１および図２２に示すように、一方の側面１２３のみに凹部が形成されている構成において、片側先細り形状であってもよく、図２３および図２４に示すように、一方の側面１２４のみに凹部が形成されている構成において、ストレート形状であってもよい。また図２５および図２６に示すように、電極端子１２０は、矩形の凹部１２２が一方の側面１２４に形成された片側先細り形状であってもよい。なお、電極端子１２０の凹部１２２が形成される側面は、先細り形状を構成する側面であってもストレート形状を構成する側面であってもよい。   As shown in FIGS. 19 and 20, the electrode terminal 120 may have a concave portion 122 formed only on one side surface 124 of opposing side surfaces 123 and 124 extending in the extending direction. As shown in FIGS. 21 and 22, in a configuration in which a recess is formed only on one side surface 123, it may be tapered on one side, and only on one side surface 124, as shown in FIGS. In the configuration in which the recess is formed, a straight shape may be used. As shown in FIGS. 25 and 26, the electrode terminal 120 may have a one-side tapered shape in which a rectangular recess 122 is formed on one side surface 124. In addition, the side surface in which the recessed part 122 of the electrode terminal 120 is formed may be a side surface forming a tapered shape or a side surface forming a straight shape.

また図２７および図２８に示すように、電極端子１２０は、延伸方向に沿って伸びる対向する側面１２３、１２４の各々に凹部１２２が複数形成されていてもよい。この構成においても、片側先細り形状であってもよく（図示せず）、図２９および図３０に示すように、ストレート形状であってもよい。また、図３１および図３２に示すように、複数の凹部１２２が形成される側面は延伸方向に伸びる側面１２３、１２４の一方の側面１２４のみに形成されていてもよい。   As shown in FIGS. 27 and 28, the electrode terminal 120 may have a plurality of recesses 122 formed on each of the opposing side surfaces 123 and 124 extending in the extending direction. Also in this configuration, the taper may be tapered on one side (not shown), or may be a straight shape as shown in FIGS. Further, as shown in FIGS. 31 and 32, the side surface on which the plurality of recesses 122 are formed may be formed only on one side surface 124 of the side surfaces 123 and 124 extending in the extending direction.

また電極端子１２０は、半円状および矩形状の両方の形状の凹部１２２が形成されていてもよい。さらに電極端子１２０に形成される凹部１２２は、半円状以外の円弧状や楕円形などの形状であってもよい。   Further, the electrode terminal 120 may have a concave portion 122 having both a semicircular shape and a rectangular shape. Further, the recess 122 formed in the electrode terminal 120 may have an arc shape other than a semicircular shape or an elliptical shape.

本実施の形態およびその変形例における半導体装置１００ｄ〜１００ｍの製造方法は、実施の形態１の半導体装置１００ａ、１００ｂ、１００ｃの製造方法と基本的には同様の構成を備えているが、電極端子を準備する工程（ステップＳ６）において図１３〜図３２に示す電極端子１２０を準備する点においてのみ異なる。   The manufacturing method of the semiconductor devices 100d to 100m in the present embodiment and its modifications has basically the same configuration as the manufacturing method of the semiconductor devices 100a, 100b, and 100c in the first embodiment. The only difference is that the electrode terminal 120 shown in FIGS. 13 to 32 is prepared in the step of preparing (Step S6).

以上説明したように、本実施の形態における半導体装置１００ｄ〜１００ｍによれば、電極端子１２０の凹部１２２は、矩形状および半円状のいずれか一方の形状を有している。これにより、半導体素子１１０において電極端子１２０と接合されるために要する面積を縮小化し、かつ信頼性の低下を抑制する構成が実現できる。また、反対側に向いた面１２２ａを容易に形成できる。   As described above, according to semiconductor devices 100d to 100m in the present embodiment, recess 122 of electrode terminal 120 has one of a rectangular shape and a semicircular shape. Thereby, the structure which reduces the area required in order to join with the electrode terminal 120 in the semiconductor element 110, and suppresses the fall of reliability is realizable. Further, the surface 122a facing the opposite side can be easily formed.

（実施の形態３）
図３３は、本発明の実施の形態３の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す断面図である。図３４は、本発明の実施の形態３における半導体装置の電極端子の構成を概略的に示す斜視図である。図３３および図３４に示すように、本実施の形態における１００ｎは、基本的には実施の形態１の半導体装置１００ａと同様の構成を備えているが、延伸部分１２０ａは、延伸部分１２０ａを貫通する貫通孔１２７を有し、貫通孔１２７に反対側に向いた面１２７ａが形成されている点においてのみ異なる。 (Embodiment 3)
FIG. 33 is a cross sectional view schematically showing a configuration in the vicinity of a region where the electrode terminal and the semiconductor element are joined in the semiconductor device according to the third embodiment of the present invention. FIG. 34 is a perspective view schematically showing a configuration of an electrode terminal of the semiconductor device in the third embodiment of the present invention. As shown in FIGS. 33 and 34, 100n in the present embodiment basically has the same configuration as that of semiconductor device 100a in the first embodiment, but extended portion 120a penetrates extended portion 120a. The difference is only in that a through-hole 127 is formed and a surface 127 a facing the opposite side is formed in the through-hole 127.

具体的には、延伸方向に沿って伸びる面としての正面１２５および背面１２６に貫通孔１２７が形成されている。本実施の形態では、正面１２５および背面１２６に貫通するように円形状の貫通孔１２７が形成されているが、側面１２３、１２４に貫通孔１２７が形成されていてもよい。また、貫通孔１２７の形状は、円形状に特に限定されない。また、貫通孔１２７は、複数形成されていてもよい。また、貫通孔１２７は、図３３および図３４に示すように、延伸方向に沿って伸びる面の略中央部に形成されていてもよいし、中央部から離れた側部に形成されていてもよい。   Specifically, through holes 127 are formed in the front surface 125 and the back surface 126 as surfaces extending along the extending direction. In the present embodiment, the circular through hole 127 is formed so as to penetrate the front surface 125 and the back surface 126, but the through hole 127 may be formed on the side surfaces 123 and 124. The shape of the through hole 127 is not particularly limited to a circular shape. A plurality of through holes 127 may be formed. Moreover, as shown in FIG. 33 and FIG. 34, the through-hole 127 may be formed in the substantially center part of the surface extended along an extending | stretching direction, and may be formed in the side part away from the center part. Good.

なお、電極端子１２０に貫通孔１２７が形成されている場合であっても、図３３および図３４に示すストレート形状に特に限定されず、片側先細り形状または先細り形状であってもよい。また、実施の形態１または２のように、延伸方向に沿って伸びる側面１２３、１２４に凹部１２２がさらに形成されていてもよい。   Even when the through-hole 127 is formed in the electrode terminal 120, it is not particularly limited to the straight shape shown in FIGS. 33 and 34, and may be a one-side tapered shape or a tapered shape. Further, as in the first or second embodiment, the concave portion 122 may be further formed on the side surfaces 123 and 124 extending along the extending direction.

本実施の形態における半導体装置１００ｎの製造方法は、実施の形態１の半導体装置１００ａ、１００ｂ、１００ｃの製造方法と基本的に同様の構成を備えているが、電極端子を準備する工程（ステップＳ６）において、図３４に示す電極端子１２０を準備する点においてのみ異なる。   The manufacturing method of the semiconductor device 100n according to the present embodiment has basically the same configuration as the manufacturing method of the semiconductor devices 100a, 100b, and 100c of the first embodiment, but a step of preparing electrode terminals (step S6). ) Only in that the electrode terminal 120 shown in FIG. 34 is prepared.

以上説明したように、本実施の形態の半導体装置１００ｎによれば、延伸部分１２０ａは、延伸部分１２０ａを貫通する貫通孔１２７を有し、貫通孔１２７に反対側に向いた面１２７ａが形成されている。これにより、半導体素子１１０において電極端子１２０と接合されるために要する面積を縮小化し、かつ信頼性の低下を抑制する構成が実現できる。   As described above, according to the semiconductor device 100n of the present embodiment, the extended portion 120a has the through hole 127 that penetrates the extended portion 120a, and the surface 127a that faces the opposite side is formed in the through hole 127. ing. Thereby, the structure which reduces the area required in order to join with the electrode terminal 120 in the semiconductor element 110, and suppresses the fall of reliability is realizable.

（実施の形態４）
図３５は、本発明の実施の形態４の半導体装置において電極端子と半導体装置とが接合されている領域近傍の構成を概略的に示す斜視図である。図３６は、本発明の実施の形態４における電極端子の構成を概略的に示し、（Ａ）は正面図であり、（Ｂ）は（Ａ）において矢印Ｂから見たときの側面図であり、（Ｃ）は斜視図である。図３５および図３６（Ａ）〜（Ｃ）に示すように、本実施の形態における半導体装置１００ｏは、基本的には実施の形態１の半導体装置１００ａと同様の構成を備えているが、延伸方向に沿って伸びる面としての側面１２３が波打つように湾曲している点においてのみ異なる。 (Embodiment 4)
FIG. 35 is a perspective view schematically showing a configuration in the vicinity of a region where the electrode terminal and the semiconductor device are joined in the semiconductor device according to the fourth embodiment of the present invention. FIG. 36 schematically shows a configuration of an electrode terminal according to Embodiment 4 of the present invention, (A) is a front view, and (B) is a side view when viewed from arrow B in (A). , (C) is a perspective view. As shown in FIGS. 35 and 36A to 36C, the semiconductor device 100o in the present embodiment basically has the same configuration as that of the semiconductor device 100a in the first embodiment. It differs only in that the side surface 123 as a surface extending along the direction is curved so as to wave.

具体的には、図３５（Ｂ）の矢印で表わされるように、電極端子１２０において、延伸方向に対して互いに対向する両側面１２３、１２４が同じ方向に突き出すように湾曲している。波打つように湾曲している面としての側面１２３に、先端面１２１と反対側に向いた面１２３ａを有している。電極端子１２０に引張荷重（図３３において上向きの力）が作用すると、反対側に向いた面１２３ａに付着したはんだ１５１のせん断に対する抵抗力により、電極端子１２０が半導体素子１１０の表面１１０ａから向け落ちることを抑制できる。   Specifically, as represented by an arrow in FIG. 35B, in the electrode terminal 120, both side surfaces 123 and 124 facing each other with respect to the extending direction are curved so as to protrude in the same direction. A side surface 123 as a surface that curves so as to wave is provided with a surface 123 a facing away from the front end surface 121. When a tensile load (upward force in FIG. 33) is applied to the electrode terminal 120, the electrode terminal 120 falls from the surface 110a of the semiconductor element 110 due to the resistance force against the shearing of the solder 151 attached to the surface 123a facing the opposite side. This can be suppressed.

なお、半導体装置１００ｏは、実施の形態１または２のように延伸方向に沿って伸びる側面１２３、１２４に凹部がさらに形成されていてもよいし、実施の形態２のように湾曲している面としての側面１２３に貫通孔１２７がさらに形成されていてもよい。   Note that the semiconductor device 100o may further have recesses formed on the side surfaces 123 and 124 extending in the extending direction as in the first or second embodiment, or a curved surface as in the second embodiment. A through hole 127 may be further formed on the side surface 123.

本実施の形態における半導体装置１００ｏの製造方法は、実施の形態１の半導体装置１００ａ、１００ｂ、１００ｃの製造方法と基本的に同様の構成を備えているが、電極端子を準備する工程（ステップＳ６）において、図３５および図３６（Ａ）〜（Ｃ）に示す電極端子１２０を準備する点においてのみ異なる。   The manufacturing method of the semiconductor device 100o in the present embodiment has basically the same configuration as the manufacturing method of the semiconductor devices 100a, 100b, and 100c of the first embodiment, but a step of preparing electrode terminals (step S6). ) Is different only in that the electrode terminal 120 shown in FIGS. 35 and 36A to 36C is prepared.

以上説明したように、本実施の形態における半導体装置１００ｏによれば、電極端子１２０は延伸方向に沿って伸びる面としての側面１２３、１２４が波打つように湾曲し、湾曲した面としての側面１２３、１２４に反対側に向いた面１２３ａが形成されている。これにより、半導体素子１１０において電極端子１２０と接合されるために要する面積を縮小化し、かつ信頼性の低下を抑制する構成が実現できる。   As described above, according to the semiconductor device 100o in the present embodiment, the electrode terminal 120 is curved such that the side surfaces 123 and 124 that extend along the extending direction are waved, and the side surface 123 that is a curved surface is provided. A surface 123 a facing the opposite side is formed on 124. Thereby, the structure which reduces the area required in order to join with the electrode terminal 120 in the semiconductor element 110, and suppresses the fall of reliability is realizable.

また、上述した本発明の実施の形態１〜３の半導体装置１００ａ〜１００ｏにおいて、電極端子１２０のはんだ１５１と接合する領域には、切欠部（凹部１２２）、貫通孔１２７、および凹凸（湾曲している面としての側面１２３、１２４）のうちの少なくともいずれかが形成されていることが好ましい。これにより、本発明の効果を有する構成が実現できる。   Further, in the semiconductor devices 100a to 100o of the first to third embodiments of the present invention described above, in the region where the electrode terminal 120 is joined to the solder 151, the notch (recessed portion 122), the through hole 127, and the unevenness (curved). It is preferable that at least one of the side surfaces 123 and 124) is formed. Thereby, the structure which has the effect of this invention is realizable.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した実施の形態ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

本発明の半導体装置および半導体装置の製造方法によれば、半導体素子において電極端子と接合されるために要する面積を縮小化し、かつ信頼性の低下を抑制することができる。そのため、半導体素子への電極端子の接合部分が限られている場合等に、好適に用いることができる。   According to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, it is possible to reduce the area required for bonding with the electrode terminal in the semiconductor element, and to suppress the decrease in reliability. Therefore, it can be suitably used when the bonding portion of the electrode terminal to the semiconductor element is limited.

本発明の実施の形態１における半導体装置の構成を概略的に示す概略断面図である。1 is a schematic cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. 図１における領域ＩＩの拡大側面図である。It is an enlarged side view of the area | region II in FIG. 図２の線分ＩＶ−ＩＶに沿った断面図である。FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. 図２の線分Ｖ−Ｖでの断面図である。FIG. 5 is a cross-sectional view taken along line VV in FIG. 2. 図１における領域ＩＩの拡大側面図である。It is an enlarged side view of the area | region II in FIG. 本発明の実施の形態１における電極端子の構成を示す概略斜視図である。It is a schematic perspective view which shows the structure of the electrode terminal in Embodiment 1 of this invention. 本発明の実施の形態１における半導体装置において反対側に向いた面を説明するための図である。It is a figure for demonstrating the surface which faced the opposite side in the semiconductor device in Embodiment 1 of this invention. 本発明の実施の形態１の変形例１における半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows schematically the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device in the modification 1 of Embodiment 1 of this invention. 本発明の実施の形態１の変形例１における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the electrode terminal of the semiconductor device in the modification 1 of Embodiment 1 of this invention. 本発明の実施の形態１の変形例２における半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows schematically the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device in the modification 2 of Embodiment 1 of this invention. 本発明の実施の形態１の変形例２における半導体装置の電極端子を概略的に示す斜視図である。It is a perspective view which shows roughly the electrode terminal of the semiconductor device in the modification 2 of Embodiment 1 of this invention. 本発明の実施の形態１における半導体装置の製造方法を示すフローチャートである。3 is a flowchart showing a method for manufacturing the semiconductor device in the first embodiment of the present invention. 本発明の実施の形態２の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of Embodiment 2 of this invention. 本発明の実施の形態２における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the electrode terminal of the semiconductor device in Embodiment 2 of this invention. 本発明の実施の形態２の変形例１の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows schematically the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 1 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例１における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the electrode terminal of the semiconductor device in the modification 1 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例２の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view showing roughly the composition near the field where the electrode terminal and the semiconductor element are joined in the semiconductor device of modification 2 of Embodiment 2 of the present invention. 本発明の実施の形態２の変形例２における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows schematically the structure of the electrode terminal of the semiconductor device in the modification 2 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例３の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows schematically the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 3 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例３における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows schematically the structure of the electrode terminal of the semiconductor device in the modification 3 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例４の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 4 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例４における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows schematically the structure of the electrode terminal of the semiconductor device in the modification 4 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例５の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 5 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例５における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows schematically the structure of the electrode terminal of the semiconductor device in the modification 5 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例６の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 6 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例６における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows schematically the structure of the electrode terminal of the semiconductor device in the modification 6 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例７の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 7 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例７における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the electrode terminal of the semiconductor device in the modification 7 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例８の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 8 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例８における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the electrode terminal of the semiconductor device in the modification 8 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例９の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of the modification 9 of Embodiment 2 of this invention. 本発明の実施の形態２の変形例９における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows schematically the structure of the electrode terminal of the semiconductor device in the modification 9 of Embodiment 2 of this invention. 本発明の実施の形態３の半導体装置において電極端子と半導体素子とが接合されている領域近傍の構成を概略的に示す断面図である。It is sectional drawing which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor element are joined in the semiconductor device of Embodiment 3 of this invention. 本発明の実施の形態３における半導体装置の電極端子の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the electrode terminal of the semiconductor device in Embodiment 3 of this invention. 本発明の実施の形態４の半導体装置において電極端子と半導体装置とが接合されている領域近傍の構成を概略的に示す斜視図である。It is a perspective view which shows roughly the structure of the area | region vicinity where the electrode terminal and the semiconductor device are joined in the semiconductor device of Embodiment 4 of this invention. 本発明の実施の形態４における電極端子の構成を概略的に示し、（Ａ）は正面図であり、（Ｂ）は（Ａ）において矢印Ｂから見たときの側面図であり、（Ｃ）は斜視図である。The structure of the electrode terminal in Embodiment 4 of this invention is shown roughly, (A) is a front view, (B) is a side view when it sees from the arrow B in (A), (C) FIG. 上記特許文献１〜３に開示されている先端部がＬ字状に折り曲げられた電極端子を備えた半導体装置を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the semiconductor device provided with the electrode terminal by which the front-end | tip part currently disclosed by the said patent documents 1-3 was bent by L shape. 上記特許文献１〜３に開示されている先端部がＬ字状に折り曲げられた電極端子を備えた半導体装置を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the semiconductor device provided with the electrode terminal by which the front-end | tip part currently disclosed by the said patent documents 1-3 was bent by L shape. 比較例を示す半導体装置における電極端子近傍の構成を概略的に示す拡大断面図である。It is an expanded sectional view which shows roughly the structure of the electrode terminal vicinity in the semiconductor device which shows a comparative example.

符号の説明Explanation of symbols

１００ａ〜１００ｏ 半導体装置、１１０ 半導体素子、１１０ａ 表面、１１１ 電極パターン、１１２ 半導体基板、１２０，１３０ 電極端子、１２０ａ 延伸部分、１２０ｂ 領域、１２１ 先端面、１２２ 凹部、１２２ａ，１２３ａ，１２７ａ 反対側に向いた面、１２３，１２４ 側面、１２５ 正面、１２６ 側面、１２７ 貫通孔、１４０ 絶縁基板、１４１ セラミック基板、１４２〜１４４ 表パターン電極、１４５ 裏パターン電極、１５１〜１５６ はんだ、１６０ ヒートシンク、１７０ 封止部材、１８０ ケース。   100a to 100o semiconductor device, 110 semiconductor element, 110a surface, 111 electrode pattern, 112 semiconductor substrate, 120, 130 electrode terminal, 120a extended portion, 120b region, 121 tip surface, 122 recess, 122a, 123a, 127a Surface, 123, 124 side surface, 125 front surface, 126 side surface, 127 through-hole, 140 insulating substrate, 141 ceramic substrate, 142-144 surface pattern electrode, 145 back pattern electrode, 151-156 solder, 160 heat sink, 170 sealing member 180 cases.

Claims (8)

半導体素子と、
延伸方向に沿って伸びる延伸部分を有し、かつ前記延伸部分の前記延伸方向の先端面を前記半導体素子の表面に対して突き合わせた状態で前記半導体素子と接合される電極端子と、
前記半導体素子と前記電極端子とを接合するはんだとを備え、
前記電極端子は、前記電極端子の前記はんだで接合される領域に、前記延伸方向に交差する面であって、前記先端面と反対側に向いた面を有する、半導体装置。 A semiconductor element;
An electrode terminal joined to the semiconductor element in a state of having a stretched part extending along the stretched direction, and abutting the front end surface of the stretched part in the stretched direction against the surface of the semiconductor element;
A solder for joining the semiconductor element and the electrode terminal;
The said electrode terminal is a semiconductor device which has a surface which cross | intersected the said extending | stretching direction in the area | region joined by the said solder of the said electrode terminal, and was suitable for the said other end side. 前記電極端子の前記先端面における幅は、前記延伸部分の前記先端面以外の他の部分の最大の幅以下である、請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a width of the electrode terminal at the tip surface is equal to or less than a maximum width of a portion other than the tip surface of the extended portion. 前記延伸部分の側面に凹部が形成され、
前記凹部に前記反対側に向いた面が形成されている、請求項１または２に記載の半導体装置。 A recess is formed on the side surface of the stretched portion,
The semiconductor device according to claim 1, wherein a surface facing the opposite side is formed in the recess. 前記延伸部分は、互いに対向する２つの側面を有し、
前記２つの側面の各々に凹部が形成され、
前記凹部に前記反対側に向いた面が形成されている、請求項１または２に記載の半導体装置。 The stretched portion has two side surfaces facing each other,
A recess is formed on each of the two side surfaces,
The semiconductor device according to claim 1, wherein a surface facing the opposite side is formed in the recess. 前記２つの側面のうちの一方の側面に形成された凹部と前記先端面との距離は、前記２つの側面のうちの他方の側面に形成された凹部と前記先端面との距離と異なっている、請求項４に記載の半導体装置。   The distance between the concave portion formed on one side surface of the two side surfaces and the tip surface is different from the distance between the concave portion formed on the other side surface of the two side surfaces and the tip surface. The semiconductor device according to claim 4. 前記凹部は、矩形状および半円状のいずれか一方の形状を有している、請求項３〜５のいずれかに記載の半導体装置。   The semiconductor device according to claim 3, wherein the recess has one of a rectangular shape and a semicircular shape. 前記延伸部分は、前記延伸部分を貫通する貫通孔を有し、
前記貫通孔に前記反対側に向いた面が形成されている、請求項１または２に記載の半導体装置。 The stretched portion has a through-hole penetrating the stretched portion,
The semiconductor device according to claim 1, wherein a surface facing the opposite side is formed in the through hole. 半導体素子を準備する工程と、
延伸方向に沿って伸びる延伸部分と、前記延伸部分の前記延伸方向の先端面と、前記延伸方向に交差する面であって前記先端面と反対側に向いた面とを有する電極端子を準備する工程と、
前記半導体素子の表面と前記電極端子の前記先端面とを突き合わすように配置した状態で前記半導体素子と前記電極端子とをはんだを用いて接合する工程とを備え、
前記接合する工程では、前記反対側に向いた面に前記はんだが付着するように接合する、半導体装置の製造方法。 Preparing a semiconductor element;
An electrode terminal having a stretched portion extending along the stretch direction, a tip surface in the stretch direction of the stretched portion, and a surface that intersects the stretch direction and faces away from the tip surface is prepared. Process,
A step of joining the semiconductor element and the electrode terminal using solder in a state where the surface of the semiconductor element and the tip surface of the electrode terminal are in contact with each other, and
The method for manufacturing a semiconductor device, wherein, in the bonding step, bonding is performed so that the solder adheres to a surface facing the opposite side.
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