JP4329187B2 - Semiconductor element - Google Patents

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JP4329187B2
JP4329187B2 JP30967799A JP30967799A JP4329187B2 JP 4329187 B2 JP4329187 B2 JP 4329187B2 JP 30967799 A JP30967799 A JP 30967799A JP 30967799 A JP30967799 A JP 30967799A JP 4329187 B2 JP4329187 B2 JP 4329187B2
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terminal
auxiliary
electrode
semiconductor chip
side terminal
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JP2001127226A (en
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秀利 梅本
光政 岩原
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Description

【０００１】
【発明の属する技術分野】
本発明は半導体チップが樹脂封止される半導体素子に関し、特に半導体チップの表裏面が導体と電気的に接続される半導体素子に関する。
【０００２】
【従来の技術】
従来、半導体チップが樹脂封止される半導体素子においては、半導体チップと半導体素子の外部端子との電気的な接続をワイヤボンディングによって行うことが一般的であった。しかし、ワイヤボンディングによる接続では、サージ電流のような大電流が流れた際に断線してしまうという問題点があり、また、サージ電流のような大電流が流れなくても、素子の動作による温度変化を繰り返すことによってワイヤが伸縮し、その応力から生じる金属疲労によってワイヤが断線してしまうという問題点があった。また、これらの弊害を防止するためにワイヤ径を太くすると、ボンディング時におけるループ径を高く採らなければならず、製品外形が大きくなってしまうという問題点があった。さらにリード端子が半導体チップの搭載前に屈曲されているとリード端子にワイヤボンディングのボンディング時の超音波振動が伝わりにくくボンディングしにくいという問題もあった。
【０００３】
このようなワイヤボンディングによる接続の問題点を解決する従来技術として、図５に示す半導体素子１００がある。半導体素子１００は、半導体チップ１０４の下面が接続されるリード端子１０２、及び半導体チップの上面が接続されるリード端子１０１が一対で形成され、それらのリード端子１０１、１０２の間に半導体チップを配置し、半田１０３、１０５で接続するものである。リード端子１０１、１０２は、ワイヤボンディングに用いるワイヤに比べ、その厚み、幅とも十分大きく採ることが可能であるため、大電流が流れた場合、及び温度変化によって伸縮が繰り返された場合においても十分な強度を有し、また、その配置形状を自由に選択できるため、製品外形の小型化を図ることができる。
【０００４】
【発明が解決しようとする課題】
しかし、半導体素子１００では、リード端子１０１が半導体チップ１０４の上面全体を覆うように配置され、このリード端子１０１と半導体チップ１０４との間に配置された半田１０５が溶解し、これらの半田付けが行われることとなるため、半田１０５の溶解時に半田１０５が半導体チップ１０４の上面全体に拡がってしまい、半導体チップ１０１の電極部以外の酸化膜等にも半田が付着してしまう結果、半田成分が半導体チップ内部に浸透し、半導体チップの信頼性を低下させてしまうという問題点がある。
【０００５】
また、リード端子１０１は、リード端子１０２に比べて長く、熱膨張による伸縮が大きいため、この伸縮によって半導体チップ１０４に余計な応力を与えてしまうという問題点もある。
【０００６】
さらに、リード端子１０１を半田付けするには、上から加重をかけて行わないと充分な半田付けができず、このように加重をかけるとリード端子の変形も考えられる。そして、通常リードフレームで多数個連結されたものを同時に処理していくが、全ての素子に一応に加重をかけることは困難である。
【０００７】
本発明はこのような点に鑑みてなされたものであり、半導体チップの電極部以外への半田付着を防止することによって、信頼性を向上させる半導体素子を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明では上記課題を解決するために、半導体チップが樹脂で封止される半導体素子において、導電性を有する下面側端子と、上面電極及び下面電極が設けられ、前記下面側端子の上面に電気的に接続されて配置される半導体チップと、面積が縮少された電極接続部を有し、前記電極接続部が屈曲していることによって前記上面電極との電気的な接続を行う補助端子と、前記補助端子と電気的に接続される補助端子側端子と、を有し、前記下面側端子は、導電性を有する板を上面方向及び下面方向に１回ずつ屈曲させて互いに平行な段違いの２平面が形成された構成を有し、前記下面側端子の上段側の平面の上面に前記半導体チップの前記下面電極が第１の導電性接合媒体を介して電気的に接続され、前記補助端子は、導電性を有する板の一部を上面方向及び下面方向に１回ずつ屈曲させて互いに平行な段違いの２平面が形成された構成を有し、前記補助端子の下段側が前記電極接続部となり、前記電極接続部の下面に前記半導体チップの前記上面電極が第２の導電性接合媒体を介して電気的に接続され、前記電極接続部及び前記第２の導電性接合媒体は、前記上面電極と同じ平面サイズで形成され、前記補助端子側端子は、導電性を有する板を上面方向に１回屈曲させた構成を有し、一端側に前記補助端子が電気的に接続され、前記下面側端子の下段側の平面の下面及び前記補助端子側端子の他端側の下面が同一平面上に配置され、前記下面側端子の前記下段側及び前記補助端子側端子の前記他端側を互いに外側に向け、前記下面側端子の前記下段側の末端部及び前記補助端子側端子の前記他端側の末端部を残して樹脂で封止されていることを特徴とする半導体素子が提供される。
【０００９】
ここで、下面側端子は、半導体チップの下面電極と電気的に接続され、半導体チップは上面電極及び下面電極が設けられ、補助端子は接続位置を選択的に補正しつつ、半導体チップの上面電極と電気的に接続され、補助端子側端子は、補助端子と電気的に接続される。
【００１０】
【発明の実施の形態】
以下、本発明の実施の形態を図面を参照して説明する。
まず、本発明における第１の実施の形態について説明する。
【００１１】
図１は、本形態における半導体素子１の構造を示した構造図である。ここで、（ａ）は透過平面図を示しており、（ｂ）は（ａ）のＡ−Ａ断面図を示している。
【００１２】
半導体素子１は、例えば平均順電流ＩＦが１〜１０Ａのダイオードであり、導電性を有する下面側端子であるリード端子３、上面電極及び下面電極を有し、リード端子３の上面に電気的に接続されて配置される半導体チップ６、面積が縮少された電極接続部を有し、この電極接続部が屈曲していることによって半導体チップ６の上面電極と電気的に接続される補助端子である補助リード端子２、補助リード端子２と電気的に接続される補助端子側端子であるリード端子４、半導体チップ６等を封止する樹脂５、及び半田７、８、９によって構成されている。
【００１３】
半導体チップ６の上下面には、リード端子３、４を接続するための上面電極及び下面電極が形成されている。また、電極が形成されていない部分には絶縁層である酸化シリコン膜等の酸化膜が形成され、外部との耐圧を保っている。
【００１４】
リード端子３は、導電性を有する金属等で構成された厚さ０．２〜０．３ｍｍの長方形の板を、上面方向及び下面方向に１回ずつ屈曲させ、これにより、互いに平行な２平面が段違いに配置されるように構成される。
【００１５】
補助リード端子２も、導電性を有する金属等で構成された厚さ０．１〜０．３ｍｍの板を、上面方向及び下面方向に１回ずつ屈曲させ、これにより、互いに平行な２平面が段違いに配置されるように構成される。ただし、ここで使用される板は長方形ではなく、その一部の横幅が半導体チップ６の上面電極の幅と略同一、或いはそれ以下になるように構成された狭幅部２ａを有する形状の板が用いられる。補助リード端子２における上面方向への屈曲は狭幅部２ａで行われ、なおかつ、狭幅部２ａでの屈曲によって狭幅部２ａに形成された１つの段差部２ａａの形状が、半導体チップ６に形成された上面電極の領域に収まるように行われる。
【００１６】
この狭幅部２ａを屈曲することによって形成された段差部２ａａは、半導体チップ６に形成された上面電極に接続される電極接続部として機能することとなる。そのため、半導体チップ６で発生した熱の放熱効率、及び電気抵抗低減の面から、段差部２ａａの横幅は、半導体チップ６の上面電極の幅を越えない限度で、できるだけ広く採ることが望ましい。
【００１７】
リード端子４は、導電性を有する金属等で構成された厚さ０．２〜０．３ｍｍの長方形の板を、上面方向に１回屈曲させることにより構成される。これらリード端子３，４は一つのリードフレーム中に多数個各対向させて形成し、樹脂で封止後にリード端子を切断するのが製造上好ましい。
【００１８】
なお、リード端子３、４、及び補助リード端子２に用いる材質としては、導電性を有し、ある程度の機械的強度が保持でき、酸化、半田のフラックス等による耐腐食性を有するものであれば、特に制限なく使用できる。
【００１９】
次に、半導体素子１の配置構成について説明する。
リード端子３、４は、リード端子３、４の各１平面が同一平面上に配置され、この同一平面上に配置される各平面の末端が互いに外側を向き、また、この同一平面上に配置される各平面の屈曲がそれぞれ上面方向で後述の樹脂５内となるように配置される。
【００２０】
このように配置することによって、リード端子３の１平面と同一平面上に配置されないリード端子４の１平面の末端は上面方向に向けられて配置されることとなる。そして、このように上面方向に向けられて配置された末端部には、補助リード端子２を構成する段違いに配置された２平面のうち、段差部２ａａではない１平面の下面が、半田９によって半田付けされる。なおここで、補助リード端子２の半田付けは、段差部２ａａが半導体チップ６の上部電極の領域内のみに配置されるよう補助リード端子２の位置を補正しつつ行う。
【００２１】
リード端子４の１平面と同一平面上に配置されないが、その平面と平行に配置されることとなるリード端子３の屈曲後の別平面上部には、半田８が塗布され、その上部には半導体チップ６が配置される。さらに、半導体チップ６の上部電極には半田７が塗布され、その上部には補助リード端子２の段差部２ａａが配置される。そして、半田７、８を溶解させることにより、リード端子３と半導体チップ６の下面電極、及び半導体チップ６の上面電極と補助リード端子２の段差部２ａａとの半田付けが行われる。
【００２２】
このように配置された半導体チップ６等は樹脂５によって封止される。この際、樹脂５下面と同一平面上に配置されるリード端子３、４の各１平面の末端部は、樹脂５の外部に配置され、この外部に配置された末端部によって、外部の配線パターン等との電気的な接続が行われる。
【００２３】
図２は、図１の（ｂ）に示したＢ部の拡大図である。
図２に示すように、半導体チップ６の上面には上面電極６ａ及び酸化膜６ｃが設けられ、下面には下面電極６ｂが設けられる。上述したように、上面電極６ａの上部には、上面電極６ａからはみ出さないように半田７が配置され、さらにその上部には段差部２ａａが同じく上面電極６ａからはみ出さないように配置される。このようにすることにより、半田７が酸化膜６ｃに接触することを回避しつつ、段差部２ａａを上面電極６ａに半田付けすることができる。また、上述したように、下面電極６ｂはリード端子３の上面に半田８によって半田付けされる。
【００２４】
このように、本形態の半導体素子では、リード端子３の上面に半導体チップ６を半田付けし、補助リード端子２を狭幅部２ａにおいて屈曲させて形成した段差部２ａａを、酸化膜６ｃとの接触を避けつつ、半導体チップ６の上面電極６ａに半田付けし、補助リード端子２をリード端子４と半田付けすることとしたため、酸化膜６ｃへの半田付着による半導体チップ６への半田成分の浸透を防止し、信頼性の向上を図ることが可能となる。この時、補助リード端子２は載せて自重のみで半田付けができるので、半田付けが容易であると共に半田付け時のリード端子の変形が生じない。
【００２５】
また、補助リード端子２をリード端子４と独立に設け、補助リード端子２をリード端子４に半田付けして接続することとしたため、半導体素子１の組み立て前にリード端子４が変形した場合であっても、組み立て時に補助リード端子２の位置を補正しつつリード端子４に半田付けすることが可能となり、補助リード端子２の段差部２ａａを上面電極６ａからはみ出すことなく配置できることとなるため、酸化膜６ｃへの半田付着による半導体チップ６への半田成分の浸透を防止し、信頼性の向上を図ることが可能となる。さらに、半田９が応力緩和の役目をするので、リード端子４の熱膨張による伸縮の応力が半導体チップ６に加わるのを低減できる。
【００２６】
なお、本形態では、半導体チップ６の上下面に電極が１カ所ずつ設けられ、それらに対応する補助リード端子２及びリード端子３、４が１つずつ配置される構成としたが、上下面の少なくとも一方に複数の電極が設けられた半導体チップ６を用い、各電極に対応する複数の補助リード端子２及びリード端子３、４を用い、半導体素子を構成することとしてもよい。
【００２７】
また、本形態では、本発明を半導体チップを内蔵した半導体素子に適用したが、半導体チップ以外の素子を用いた電子部品に適用することとしてもよい。
さらに、本形態では、各構成部品の接続を半田によって行うこととしたが、その他の導電性接合媒体を用いることとしてもよい。
【００２８】
また、本形態では、補助リード端子２の狭幅部２ａのみに段差部２ａａを形成することとしたが、リード端子３を屈曲させてリード端子３に段差部を設け、このリード端子３の段差部によって、半導体チップ６の下面電極６ｂに接続される構成としてもよい。
【００２９】
次に、本発明における第２の実施の形態について説明する。
本形態は、第１の実施の形態に対する変形例であり、補助リード端子の形状に相違がある。以下の説明では、第１の実施の形態との相違点を中心に説明を行い、共通する部分については、その説明を省略する。
【００３０】
図３は、本形態における半導体素子１０の構成を示した構成図である。ここで、（ａ）は透過平面図を示しており、（ｂ）は（ａ）のＣ−Ｃ断面図を示している。なお、図３では、第１の実施の形態と共通する構成部分については、第１の実施の形態での説明に用いた符号と同じ符号を付してある。
【００３１】
半導体素子１０は、半導体チップ６、リード端子３、補助リード端子１１、リード端子４、樹脂５、半田７、８、９によって構成されている。
補助リード端子１１は、導電性を有する金属等の板によって構成され、その板の一部をコの字形に切り抜いて残した切り出し部１１ａを有している。切り出し部１１ａは、その付け根において下面方向に屈曲し、さらに、その中程で上面方向に屈曲することにより１つの段差部１１ａａを形成する。ここで、切り出し部１１ａの各屈曲部の角度は、切り出し部１１ａに形成された段差部１１ａａが、切り出し部１１ａが切り出された補助リード端子１１本体と平行に配置されるように選択される。また、切り出し部１１ａの切り出し寸法及び、切り出し部１１ａにおける上面方向への屈曲部の位置は、段差部１１ａａの形状が、半導体チップ６に形成された上面電極の領域に収まるように選択される。ここで、切り出し部１１ａの形成方法としては、切り出しやプレスでの打ち抜き、あるいは化学的エッチング等が採用できる。
【００３２】
この切り出し部１１ａを屈曲することによって形成された段差部１１ａａは、半導体チップ６に形成された上面電極に接続される電極接続部として機能することとなる。そのため、半導体チップ６で発生した熱の放熱効率、及び電気抵抗低減の面から、段差部１１ａａの横幅は、半導体チップ６の上面電極の幅を越えない程度で、できるだけ広く採ることが望ましい。
【００３３】
次に、半導体素子１０の配置構成について説明する。
リード端子３、４、半導体チップ６の配置構成については、第１の実施の形態と同様であるため説明を省略する。
【００３４】
半導体チップ６の上面電極には半田７が塗布され、その上部には補助リード端子１１の段差部１１ａａが配置される。段差部１１ａａは、第１の実施の形態の場合と同様に半導体チップの上面電極の領域内のみに配置され、そこで半田付けされる。なお、補助リード端子１１の一端は、第１の実施の形態と同様に位置補正を行いつつ、リード端子４に半田付けされる。
【００３５】
このような補助リード端子１１を用いることとしても、第１の実施の形態と同様な効果を得られる。
なお、本形態では、半導体チップ６の上下面に電極が１カ所ずつ設けられ、それらに対応する補助リード端子１１及びリード端子３、４が１つずつ配置される構成としたが、上下面の少なくとも一方に複数の電極が設けられた半導体チップ６を用い、各電極に対応する複数の補助リード端子１１及びリード端子３、４を用い、半導体素子を構成することとしてもよい。
【００３６】
また、本形態では、本発明を半導体チップを内蔵した半導体素子に適用したが、半導体チップ以外の素子を用いた電子部品に適用することとしてもよい。
さらに、本形態では、各構成部品の接続を半田によって行うこととしたが、その他の導電性接合媒体を用いることとしてもよい。
【００３７】
また、本形態では、補助リード端子１１の切り出し部１１ａのみに段差部１１ａａを形成することとしたが、リード端子３を屈曲させてリード端子３に段差部を設け、このリード端子３の段差部によって、半導体チップ６の下面電極６ｂに接続される構成としてもよい。
【００３８】
次に、本発明における第３の実施の形態について説明する。
本形態は、第１の実施の形態に対する変形例であり、補助リード端子の形状に相違がある。以下の説明では、第１の実施の形態との相違点を中心に説明を行い、共通する部分については、その説明を省略する。
【００３９】
図４は、本形態における半導体素子２０の構成を示した構成図である。ここで、（ａ）は透過平面図を示しており、（ｂ）は（ａ）のＤ−Ｄ断面図を示している。なお、図４では、第１の実施の形態と共通する構成部分については、第１の実施の形態での説明に用いた符号と同じ符号を付してある。
【００４０】
半導体素子２０は、半導体チップ６、リード端子３、補助リード端子２１、リード端子４、樹脂５、半田７、８、９によって構成されている。
補助リード端子２１は狭幅部２１ａの屈曲による段差部２１ａａを有し、第１の実施の形態における補助リード端子２とほぼ同様な形状となっているが、折り曲げ部２１ｂを有する点のみが異なる。折り曲げ部２１ｂは、補助リード端子２１の狭幅部２１ａ以外のエッジ部を狭幅部２１ａにおける屈曲と平行かつ下面方向に屈曲させることにより形成される。
【００４１】
補助リード端子２１の配置は、第１の実施の形態における補助リード端子２とほぼ同様であるが、折り曲げ部２１ｂをリード端子４に宛がった状態で、補助リード端子２１とリード端子４との接続を行う点のみが異なる。
【００４２】
このような構成としても、第１の実施の形態と同様な効果を得ることができる。
また、本形態では、補助リード端子２１に折り曲げ部２１ｂを形成し、折り曲げ部２１ｂをリード端子４に宛がった状態で、補助リード端子２１のリード端子４への接続を行うこととしたため、補助リード端子２１の位置決めが容易になり、組み立て作業の効率化を図ることが可能となる。
【００４３】
さらに、半田９は折り曲げ部２１ｂの内側とリード端子４にも回り込み、これらの接続を行うこととなるため、補助リード端子２１とリード端子４との接続強度、信頼性を向上させることができる。
【００４４】
なお、本形態では、半導体チップ６の上下面に電極が１カ所ずつ設けられ、それらに対応する補助リード端子２１及びリード端子３、４が１つずつ配置される構成としたが、上下面の少なくとも一方に複数の電極が設けられた半導体チップ６を用い、各電極に対応する複数の補助リード端子２１及びリード端子３、４を用い、半導体素子を構成することとしてもよい。
【００４５】
また、本形態では、本発明を半導体チップを内蔵した半導体素子に適用したが、半導体チップ以外の素子を用いた電子部品に適用することとしてもよい。
さらに、本形態では、各構成部品の接続を半田によって行うこととしたが、その他の導電性接合媒体を用いることとしてもよい。
【００４６】
また、本形態では、補助リード端子２１の狭幅部２１ａのみに段差部２１ａａを形成することとしたが、リード端子３を屈曲させ、リード端子３に段差部を設け、このリード端子３の段差部によって、半導体チップ６の下面電極６ｂに接続される構成としてもよい。
【００４７】
さらに、本形態では、補助リード端子として、第１の実施の形態における補助リード端子２に折り曲げ部を形成したものを用いたが、第２の実施の形態における補助リード端子１１に折り曲げ部を形成したものを用いることとしてもよい。
【００４８】
なお、これら第１〜第３の実施例における樹脂５の外形は縦×横が２．５ｍｍ×４．０ｍｍで厚さが１．２〜１．６ｍｍであり、リード端子３、４の突出部（各０．５ｍｍ）を含めた横の長さが５．０ｍｍである。
【００４９】
【発明の効果】
以上説明したように本発明では、導電性を有する下面側端子の上面に半導体チップを電気的に接続して配置し、半導体チップの上面電極に、面積を縮少させ屈曲させた電極接続部によって補助端子を電気的に接続し、補助端子に補助端子側端子を電気的に接続して半導体素子を構成することとしたため、小型化を図った上で半導体チップの酸化膜への半田の接触を避けつつ、補助端子を半導体チップの上面端子に半田付けすることが可能となり、半導体チップへの半田成分の浸透を防止し、半導体素子の信頼性の向上を図ることが可能となる。
【００５０】
また、補助端子を独立に設けることとしたため、半導体素子の組み立て前に端子が変形した場合であっても、組み立て時に補助端子の位置を補正しつつ半田付けすることが可能となり、半導体チップへの半田成分の浸透を防止し、高い信頼性を確保することが可能となる。さらに半導体チップに加わる応力の低減も図られる。
【図面の簡単な説明】
【図１】半導体素子の構造を示した構造図である。ここで、（ａ）は透過平面図を示しており、（ｂ）は（ａ）のＡ−Ａ断面図を示している。
【図２】図１の（ｂ）に示したＢ部の拡大図である。
【図３】半導体素子の構成を示した構成図である。ここで、（ａ）は透過平面図を示しており、（ｂ）は（ａ）のＣ−Ｃ断面図を示している。
【図４】半導体素子の構成を示した構成図である。ここで、（ａ）は透過平面図を示しており、（ｂ）は（ａ）のＤ−Ｄ断面図を示している。
【図５】従来の半導体素子の構造を示した断面図である。
【符号の説明】
１、１０、２０、１００ 半導体素子
２、１１、２１ 補助リード端子
２ａ、２１ａ 狭幅部
２ａａ、１１ａａ、２１ａａ 段差部
３、４ リード端子
５ 樹脂
６ 半導体チップ
６ａ 上面電極
６ｂ 下面電極
７、８、９ 半田
１１ａ 切り出し部
２１ｂ 折り曲げ部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element in which a semiconductor chip is resin-sealed, and more particularly to a semiconductor element in which front and back surfaces of a semiconductor chip are electrically connected to a conductor.
[0002]
[Prior art]
Conventionally, in a semiconductor element in which a semiconductor chip is resin-sealed, it is common to electrically connect the semiconductor chip and an external terminal of the semiconductor element by wire bonding. However, the connection by wire bonding has a problem that it breaks when a large current such as a surge current flows, and even if a large current such as a surge current does not flow, the temperature due to the operation of the element There is a problem that the wire expands and contracts by repeating the change, and the wire breaks due to metal fatigue resulting from the stress. Further, if the wire diameter is increased in order to prevent these problems, the loop diameter at the time of bonding must be increased, resulting in a problem that the outer shape of the product is increased. Further, if the lead terminal is bent before the semiconductor chip is mounted, there has been a problem that ultrasonic vibration during wire bonding is not easily transmitted to the lead terminal and bonding is difficult.
[0003]
As a prior art for solving such a connection problem by wire bonding, there is a semiconductor element 100 shown in FIG. In the semiconductor element 100, a pair of lead terminals 102 to which the lower surface of the semiconductor chip 104 is connected and a lead terminal 101 to which the upper surface of the semiconductor chip is connected are formed, and the semiconductor chip is arranged between the lead terminals 101 and 102. The solders 103 and 105 are used for connection. The lead terminals 101 and 102 can be sufficiently large in thickness and width as compared with the wire used for wire bonding, so that they are sufficient even when a large current flows and when expansion and contraction is repeated due to temperature changes. Since it has a sufficient strength and the arrangement shape can be freely selected, the outer shape of the product can be reduced.
[0004]
[Problems to be solved by the invention]
However, in the semiconductor element 100, the lead terminal 101 is disposed so as to cover the entire upper surface of the semiconductor chip 104, and the solder 105 disposed between the lead terminal 101 and the semiconductor chip 104 is melted, and the soldering is performed. Therefore, when the solder 105 is melted, the solder 105 spreads over the entire upper surface of the semiconductor chip 104, and the solder adheres to an oxide film other than the electrode portion of the semiconductor chip 101. There is a problem in that it penetrates into the semiconductor chip and reduces the reliability of the semiconductor chip.
[0005]
In addition, since the lead terminal 101 is longer than the lead terminal 102 and greatly expands and contracts due to thermal expansion, there is a problem that extra stress is applied to the semiconductor chip 104 due to the expansion and contraction.
[0006]
Further, in order to solder the lead terminal 101, sufficient soldering cannot be performed unless weight is applied from above, and deformation of the lead terminal can be considered when weight is applied in this way. Usually, a large number of connected lead frames are processed at the same time, but it is difficult to apply a weight to all the elements.
[0007]
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor element that improves reliability by preventing solder adhesion to portions other than the electrode portion of the semiconductor chip.
[0008]
[Means for Solving the Problems]
In the present invention, in order to solve the above problems, in a semiconductor element in which a semiconductor chip is sealed with a resin, a conductive lower surface side terminal, an upper surface electrode, and a lower surface electrode are provided, and the upper surface of the lower surface side terminal is electrically connected. A semiconductor chip that is connected in a connected manner, and an auxiliary terminal that has an electrode connection portion with a reduced area, and that is electrically connected to the upper surface electrode by bending the electrode connection portion; An auxiliary terminal side terminal electrically connected to the auxiliary terminal, and the lower surface side terminal is formed by bending a conductive plate once in the upper surface direction and the lower surface direction, and having different steps parallel to each other. The auxiliary electrode has a configuration in which two planes are formed, the lower surface electrode of the semiconductor chip is electrically connected to the upper surface of the upper surface of the lower surface side terminal via a first conductive bonding medium, and the auxiliary terminal Is one of the conductive plates Is bent once each in the upper surface direction and the lower surface direction, and two parallel flat surfaces are formed. The lower side of the auxiliary terminal is the electrode connection portion, and the semiconductor is formed on the lower surface of the electrode connection portion. The upper surface electrode of the chip is electrically connected via a second conductive bonding medium, and the electrode connection portion and the second conductive bonding medium are formed in the same plane size as the upper surface electrode, and the auxiliary The terminal side terminal has a configuration in which a conductive plate is bent once in the upper surface direction, the auxiliary terminal is electrically connected to one end side, the lower surface of the lower surface of the lower surface side terminal and the lower surface The lower surface of the other end side of the auxiliary terminal side terminal is arranged on the same plane, the lower step side of the lower surface side terminal and the other end side of the auxiliary terminal side terminal face each other outward, and the lower step of the lower surface side terminal Side end and auxiliary terminal side Semiconductor element characterized by leaving the ends of the other end side of the child are sealed with resin is provided.
[0009]
Here, the lower surface side terminal is electrically connected to the lower surface electrode of the semiconductor chip, the semiconductor chip is provided with the upper surface electrode and the lower surface electrode, and the auxiliary terminal selectively corrects the connection position, and the upper surface electrode of the semiconductor chip. The auxiliary terminal side terminal is electrically connected to the auxiliary terminal.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described.
[0011]
FIG. 1 is a structural diagram showing the structure of the semiconductor element 1 in this embodiment. Here, (a) shows a transmission plan view, and (b) shows an AA cross-sectional view of (a).
[0012]
The semiconductor element 1 is, for example, a diode having an average forward current IF of 1 to 10 A, and includes a lead terminal 3 that is a conductive lower surface side terminal, an upper surface electrode, and a lower surface electrode. The semiconductor chip 6 that is connected and has an electrode connection portion with a reduced area, and an auxiliary terminal that is electrically connected to the upper surface electrode of the semiconductor chip 6 by bending the electrode connection portion. An auxiliary lead terminal 2, a lead terminal 4 that is an auxiliary terminal side terminal electrically connected to the auxiliary lead terminal 2, a resin 5 that seals the semiconductor chip 6 and the like, and solders 7, 8, and 9 are included. .
[0013]
Upper and lower electrodes for connecting the lead terminals 3 and 4 are formed on the upper and lower surfaces of the semiconductor chip 6. In addition, an oxide film such as a silicon oxide film, which is an insulating layer, is formed in a portion where the electrode is not formed, and the withstand voltage from the outside is maintained.
[0014]
The lead terminal 3 is formed by bending a 0.2 to 0.3 mm thick rectangular plate made of a conductive metal or the like once in the upper surface direction and the lower surface direction, so that two planes parallel to each other are obtained. Are configured to be arranged in steps.
[0015]
The auxiliary lead terminal 2 is also formed by bending a 0.1 to 0.3 mm thick plate made of conductive metal or the like once in the upper surface direction and the lower surface direction, so that two planes parallel to each other are formed. It is configured to be arranged in steps. However, the plate used here is not a rectangle, and a plate having a shape having a narrow width portion 2a configured such that a part of the width is substantially equal to or less than the width of the upper surface electrode of the semiconductor chip 6. Is used. The auxiliary lead terminal 2 is bent in the upper surface direction at the narrow width portion 2a, and the shape of one stepped portion 2aa formed in the narrow width portion 2a by the bending at the narrow width portion 2a is formed in the semiconductor chip 6. The process is performed so as to fit in the region of the formed upper surface electrode.
[0016]
The stepped portion 2aa formed by bending the narrow width portion 2a functions as an electrode connecting portion connected to the upper surface electrode formed on the semiconductor chip 6. For this reason, it is desirable that the lateral width of the stepped portion 2aa be as wide as possible as long as it does not exceed the width of the upper surface electrode of the semiconductor chip 6 in terms of heat radiation efficiency of the heat generated in the semiconductor chip 6 and reduction of electric resistance.
[0017]
The lead terminal 4 is configured by bending a rectangular plate having a thickness of 0.2 to 0.3 mm made of conductive metal or the like once in the upper surface direction. It is preferable in manufacturing that a large number of these lead terminals 3 and 4 are formed to face each other in one lead frame, and the lead terminals are cut after sealing with resin.
[0018]
The material used for the lead terminals 3 and 4 and the auxiliary lead terminal 2 may be any material as long as it has conductivity, can maintain a certain level of mechanical strength, and has corrosion resistance due to oxidation, solder flux, and the like. Can be used without any particular restrictions.
[0019]
Next, the arrangement configuration of the semiconductor element 1 will be described.
In the lead terminals 3 and 4, one plane of each of the lead terminals 3 and 4 is arranged on the same plane, and the ends of the planes arranged on the same plane face each other and are arranged on the same plane. Each of the planes is arranged so that the bending thereof is in the resin 5 described later in the upper surface direction.
[0020]
By arranging in this way, the end of one plane of the lead terminal 4 that is not arranged on the same plane as the one plane of the lead terminal 3 is arranged facing the upper surface direction. Then, at the end portion arranged so as to face the upper surface in this way, the lower surface of one plane which is not the stepped portion 2aa among the two planes which are arranged at different steps constituting the auxiliary lead terminal 2 is Soldered. Here, the soldering of the auxiliary lead terminal 2 is performed while correcting the position of the auxiliary lead terminal 2 so that the stepped portion 2aa is disposed only in the region of the upper electrode of the semiconductor chip 6.
[0021]
Solder 8 is applied to the upper part of another plane after bending of the lead terminal 3 which is not arranged on the same plane as the one plane of the lead terminal 4 but is arranged in parallel with the plane, and a semiconductor is formed on the upper part. Chip 6 is arranged. Furthermore, the solder 7 is applied to the upper electrode of the semiconductor chip 6, and the stepped portion 2 aa of the auxiliary lead terminal 2 is disposed on the upper portion thereof. Then, by melting the solders 7 and 8, the lead terminal 3 and the lower surface electrode of the semiconductor chip 6, and the upper surface electrode of the semiconductor chip 6 and the stepped portion 2 aa of the auxiliary lead terminal 2 are soldered.
[0022]
The semiconductor chip 6 and the like arranged in this way are sealed with a resin 5. At this time, the end portion of each one plane of the lead terminals 3 and 4 arranged on the same plane as the lower surface of the resin 5 is arranged outside the resin 5, and the outside wiring pattern is formed by the end portion arranged outside the resin 5. Etc. are electrically connected.
[0023]
FIG. 2 is an enlarged view of a portion B shown in FIG.
As shown in FIG. 2, an upper surface electrode 6a and an oxide film 6c are provided on the upper surface of the semiconductor chip 6, and a lower surface electrode 6b is provided on the lower surface. As described above, the solder 7 is disposed above the upper surface electrode 6a so as not to protrude from the upper surface electrode 6a, and further, the stepped portion 2aa is disposed so as not to protrude from the upper surface electrode 6a. . By doing so, the stepped portion 2aa can be soldered to the upper surface electrode 6a while avoiding the solder 7 from contacting the oxide film 6c. Further, as described above, the lower surface electrode 6 b is soldered to the upper surface of the lead terminal 3 by the solder 8.
[0024]
As described above, in the semiconductor element of this embodiment, the step 2aa formed by soldering the semiconductor chip 6 to the upper surface of the lead terminal 3 and bending the auxiliary lead terminal 2 at the narrow width portion 2a is formed with the oxide film 6c. Soldering to the upper surface electrode 6a of the semiconductor chip 6 while avoiding contact and soldering the auxiliary lead terminal 2 to the lead terminal 4, penetration of the solder component into the semiconductor chip 6 due to solder adhesion to the oxide film 6c. Can be prevented and reliability can be improved. At this time, since the auxiliary lead terminal 2 can be mounted and soldered only by its own weight, soldering is easy and the lead terminal is not deformed during soldering.
[0025]
Further, since the auxiliary lead terminal 2 is provided independently of the lead terminal 4 and the auxiliary lead terminal 2 is soldered and connected to the lead terminal 4, the lead terminal 4 is deformed before the assembly of the semiconductor element 1. However, it is possible to solder the lead terminal 4 while correcting the position of the auxiliary lead terminal 2 at the time of assembly, and the stepped portion 2aa of the auxiliary lead terminal 2 can be disposed without protruding from the upper surface electrode 6a. It is possible to prevent the penetration of the solder component into the semiconductor chip 6 due to the solder adhesion to the film 6c and to improve the reliability. Furthermore, since the solder 9 plays a role of stress relaxation, it is possible to reduce the expansion and contraction stress due to the thermal expansion of the lead terminal 4 from being applied to the semiconductor chip 6.
[0026]
In this embodiment, one electrode is provided on each of the upper and lower surfaces of the semiconductor chip 6 and the auxiliary lead terminal 2 and the lead terminals 3 and 4 corresponding to the electrodes are arranged one by one. The semiconductor chip 6 provided with a plurality of electrodes on at least one side and a plurality of auxiliary lead terminals 2 and lead terminals 3 and 4 corresponding to the respective electrodes may be used to constitute a semiconductor element.
[0027]
In the present embodiment, the present invention is applied to a semiconductor element incorporating a semiconductor chip. However, the present invention may be applied to an electronic component using an element other than the semiconductor chip.
Furthermore, in this embodiment, each component is connected by soldering, but other conductive bonding media may be used.
[0028]
In this embodiment, the stepped portion 2aa is formed only in the narrow width portion 2a of the auxiliary lead terminal 2. However, the lead terminal 3 is bent to provide the stepped portion in the lead terminal 3, and the step of the lead terminal 3 is formed. It is good also as a structure connected to the lower surface electrode 6b of the semiconductor chip 6 by a part.
[0029]
Next, a second embodiment of the present invention will be described.
This embodiment is a modification of the first embodiment, and there is a difference in the shape of the auxiliary lead terminal. In the following description, differences from the first embodiment will be mainly described, and description of common parts will be omitted.
[0030]
FIG. 3 is a configuration diagram showing the configuration of the semiconductor element 10 in this embodiment. Here, (a) shows a transmission plan view, and (b) shows a CC cross-sectional view of (a). In FIG. 3, the same reference numerals as those used in the description of the first embodiment are given to the components common to the first embodiment.
[0031]
The semiconductor element 10 includes a semiconductor chip 6, lead terminals 3, auxiliary lead terminals 11, lead terminals 4, resin 5, solders 7, 8, and 9.
The auxiliary lead terminal 11 is made of a conductive metal plate, and has a cutout portion 11a that is obtained by cutting out a portion of the plate into a U-shape. The cutout portion 11a is bent toward the lower surface at the base, and further bent toward the upper surface in the middle to form one step portion 11aa. Here, the angle of each bent portion of the cutout portion 11a is selected so that the stepped portion 11aa formed in the cutout portion 11a is arranged in parallel with the auxiliary lead terminal 11 main body from which the cutout portion 11a is cut out. Further, the cut-out dimension of the cut-out portion 11 a and the position of the bent portion in the upper-surface direction in the cut-out portion 11 a are selected so that the shape of the stepped portion 11 aa falls within the region of the upper-surface electrode formed on the semiconductor chip 6. Here, as a method of forming the cutout portion 11a, cutout, punching with a press, chemical etching, or the like can be employed.
[0032]
The step portion 11aa formed by bending the cutout portion 11a functions as an electrode connection portion connected to the upper surface electrode formed on the semiconductor chip 6. Therefore, it is desirable that the lateral width of the stepped portion 11aa be as wide as possible so as not to exceed the width of the upper surface electrode of the semiconductor chip 6 in terms of heat dissipation efficiency of heat generated in the semiconductor chip 6 and reduction of electric resistance.
[0033]
Next, the arrangement configuration of the semiconductor element 10 will be described.
Since the arrangement of the lead terminals 3 and 4 and the semiconductor chip 6 is the same as that of the first embodiment, the description thereof is omitted.
[0034]
Solder 7 is applied to the upper surface electrode of the semiconductor chip 6, and a stepped portion 11 aa of the auxiliary lead terminal 11 is disposed on the upper surface thereof. The step portion 11aa is arranged only in the region of the upper surface electrode of the semiconductor chip as in the case of the first embodiment, and is soldered there. Note that one end of the auxiliary lead terminal 11 is soldered to the lead terminal 4 while performing position correction as in the first embodiment.
[0035]
Even when such an auxiliary lead terminal 11 is used, the same effect as in the first embodiment can be obtained.
In the present embodiment, one electrode is provided on each of the upper and lower surfaces of the semiconductor chip 6 and the auxiliary lead terminals 11 and the lead terminals 3 and 4 corresponding to the electrodes are arranged one by one. A semiconductor element may be configured by using a semiconductor chip 6 provided with a plurality of electrodes on at least one side and using a plurality of auxiliary lead terminals 11 and lead terminals 3 and 4 corresponding to the respective electrodes.
[0036]
In the present embodiment, the present invention is applied to a semiconductor element incorporating a semiconductor chip. However, the present invention may be applied to an electronic component using an element other than the semiconductor chip.
Furthermore, in this embodiment, each component is connected by soldering, but other conductive bonding media may be used.
[0037]
In this embodiment, the stepped portion 11aa is formed only in the cutout portion 11a of the auxiliary lead terminal 11. However, the lead terminal 3 is bent to provide the stepped portion in the lead terminal 3, and the stepped portion of the lead terminal 3 is provided. Therefore, the semiconductor chip 6 may be connected to the lower surface electrode 6b.
[0038]
Next, a third embodiment of the present invention will be described.
This embodiment is a modification of the first embodiment, and there is a difference in the shape of the auxiliary lead terminal. In the following description, differences from the first embodiment will be mainly described, and description of common parts will be omitted.
[0039]
FIG. 4 is a configuration diagram showing the configuration of the semiconductor element 20 in this embodiment. Here, (a) shows a transmission plan view, and (b) shows a DD sectional view of (a). In FIG. 4, the same reference numerals as those used in the description of the first embodiment are given to the components common to the first embodiment.
[0040]
The semiconductor element 20 includes a semiconductor chip 6, lead terminals 3, auxiliary lead terminals 21, lead terminals 4, resin 5, solders 7, 8, and 9.
The auxiliary lead terminal 21 has a stepped portion 21aa due to the bending of the narrow width portion 21a, and has substantially the same shape as the auxiliary lead terminal 2 in the first embodiment, except that it has a bent portion 21b. . The bent portion 21b is formed by bending the edge portion other than the narrow width portion 21a of the auxiliary lead terminal 21 in parallel with the bending of the narrow width portion 21a and in the lower surface direction.
[0041]
The arrangement of the auxiliary lead terminal 21 is substantially the same as that of the auxiliary lead terminal 2 in the first embodiment. However, the auxiliary lead terminal 21, the lead terminal 4 and the auxiliary lead terminal 21 are arranged with the bent portion 21 b directed to the lead terminal 4. The only difference is that they are connected.
[0042]
Even with such a configuration, the same effects as those of the first embodiment can be obtained.
In the present embodiment, the bent portion 21b is formed in the auxiliary lead terminal 21, and the auxiliary lead terminal 21 is connected to the lead terminal 4 in a state where the bent portion 21b is directed to the lead terminal 4. Positioning of the auxiliary lead terminal 21 becomes easy, and the efficiency of assembly work can be improved.
[0043]
Furthermore, since the solder 9 also goes around the bent portion 21b and the lead terminal 4 to connect them, the connection strength and reliability between the auxiliary lead terminal 21 and the lead terminal 4 can be improved.
[0044]
In the present embodiment, one electrode is provided on each of the upper and lower surfaces of the semiconductor chip 6 and the auxiliary lead terminals 21 and the lead terminals 3 and 4 corresponding to the electrodes are arranged one by one. A semiconductor element may be configured by using a semiconductor chip 6 provided with a plurality of electrodes on at least one side, and using a plurality of auxiliary lead terminals 21 and lead terminals 3 and 4 corresponding to the respective electrodes.
[0045]
In the present embodiment, the present invention is applied to a semiconductor element incorporating a semiconductor chip. However, the present invention may be applied to an electronic component using an element other than the semiconductor chip.
Furthermore, in this embodiment, each component is connected by soldering, but other conductive bonding media may be used.
[0046]
Further, in this embodiment, the stepped portion 21aa is formed only in the narrow width portion 21a of the auxiliary lead terminal 21, but the lead terminal 3 is bent, the stepped portion is provided in the lead terminal 3, and the step of the lead terminal 3 is formed. It is good also as a structure connected to the lower surface electrode 6b of the semiconductor chip 6 by a part.
[0047]
Further, in the present embodiment, the auxiliary lead terminal having the bent portion formed on the auxiliary lead terminal 2 in the first embodiment is used. However, the bent portion is formed on the auxiliary lead terminal 11 in the second embodiment. It is good also as using what was done.
[0048]
The outer shape of the resin 5 in the first to third embodiments is 2.5 mm × 4.0 mm in length × width and 1.2 to 1.6 mm in thickness. The horizontal length including (each 0.5 mm) is 5.0 mm.
[0049]
【The invention's effect】
As described above, in the present invention, the semiconductor chip is electrically connected to the upper surface of the conductive lower surface side terminal, and the upper surface electrode of the semiconductor chip is provided with an electrode connection portion that is reduced in area and bent. Since the semiconductor element is configured by electrically connecting the auxiliary terminal and electrically connecting the auxiliary terminal side terminal to the auxiliary terminal, the contact of the solder to the oxide film of the semiconductor chip is achieved after miniaturization. While avoiding this, it becomes possible to solder the auxiliary terminal to the upper surface terminal of the semiconductor chip, thereby preventing the penetration of the solder component into the semiconductor chip and improving the reliability of the semiconductor element.
[0050]
In addition, since the auxiliary terminal is provided independently, even when the terminal is deformed before the assembly of the semiconductor element, it is possible to perform soldering while correcting the position of the auxiliary terminal during the assembly. It is possible to prevent penetration of the solder component and ensure high reliability. Further, the stress applied to the semiconductor chip can be reduced.
[Brief description of the drawings]
FIG. 1 is a structural diagram showing a structure of a semiconductor element. Here, (a) shows a transmission plan view, and (b) shows an AA cross-sectional view of (a).
FIG. 2 is an enlarged view of a portion B shown in FIG.
FIG. 3 is a configuration diagram showing a configuration of a semiconductor element. Here, (a) shows a transmission plan view, and (b) shows a CC cross-sectional view of (a).
FIG. 4 is a configuration diagram showing a configuration of a semiconductor element. Here, (a) shows a transmission plan view, and (b) shows a DD sectional view of (a).
FIG. 5 is a cross-sectional view showing the structure of a conventional semiconductor device.
[Explanation of symbols]
1, 10, 20, 100 Semiconductor element 2, 11, 21 Auxiliary lead terminal 2a, 21a Narrow width part 2aa, 11aa, 21aa Step part 3, 4, Lead terminal 5 Resin 6 Semiconductor chip 6a Upper surface electrode 6b Lower surface electrode 7, 8, 9 Solder 11a Cutout part 21b Bending part

Claims (5)

半導体チップが樹脂で封止される半導体素子において、
導電性を有する下面側端子と、
上面電極及び下面電極が設けられ、前記下面側端子の上面に電気的に接続されて配置される半導体チップと、
面積が縮少された電極接続部を有し、前記電極接続部が屈曲していることによって前記上面電極との電気的な接続を行う補助端子と、
前記補助端子と電気的に接続される補助端子側端子と、
を有し、
前記下面側端子は、導電性を有する板を上面方向及び下面方向に１回ずつ屈曲させて互いに平行な段違いの２平面が形成された構成を有し、前記下面側端子の上段側の平面の上面に前記半導体チップの前記下面電極が第１の導電性接合媒体を介して電気的に接続され、
前記補助端子は、導電性を有する板の一部を上面方向及び下面方向に１回ずつ屈曲させて互いに平行な段違いの２平面が形成された構成を有し、前記補助端子の下段側が前記電極接続部となり、前記電極接続部の下面に前記半導体チップの前記上面電極が第２の導電性接合媒体を介して電気的に接続され、
前記電極接続部及び前記第２の導電性接合媒体は、前記上面電極と同じ平面サイズで形成され、
前記補助端子側端子は、導電性を有する板を上面方向に１回屈曲させた構成を有し、一端側に前記補助端子が電気的に接続され、
前記下面側端子の下段側の平面の下面及び前記補助端子側端子の他端側の下面が同一平面上に配置され、前記下面側端子の前記下段側及び前記補助端子側端子の前記他端側を互いに外側に向け、前記下面側端子の前記下段側の末端部及び前記補助端子側端子の前記他端側の末端部を残して樹脂で封止されていることを特徴とする半導体素子。In a semiconductor element in which a semiconductor chip is sealed with resin,
A lower surface side terminal having conductivity;
A semiconductor chip provided with an upper surface electrode and a lower surface electrode and electrically connected to the upper surface of the lower surface side terminal;
An auxiliary terminal that has an electrode connection portion with a reduced area and performs electrical connection with the upper surface electrode by bending the electrode connection portion;
An auxiliary terminal side terminal electrically connected to the auxiliary terminal;
Have
The lower surface side terminal has a configuration in which a conductive plate is bent once in the upper surface direction and in the lower surface direction to form two parallel planes that are parallel to each other. The lower surface electrode of the semiconductor chip is electrically connected to the upper surface via a first conductive bonding medium ,
The auxiliary terminal has a configuration in which a part of a conductive plate is bent once each in an upper surface direction and a lower surface direction to form two parallel flat surfaces, and the lower side of the auxiliary terminal is the electrode A connection portion, and the upper surface electrode of the semiconductor chip is electrically connected to the lower surface of the electrode connection portion via a second conductive bonding medium;
The electrode connection portion and the second conductive bonding medium are formed in the same plane size as the upper surface electrode,
The auxiliary terminal side terminal has a configuration in which a conductive plate is bent once in the upper surface direction, and the auxiliary terminal is electrically connected to one end side,
The lower surface of the lower surface of the lower surface side terminal and the lower surface of the other end side of the auxiliary terminal side terminal are arranged on the same plane, and the lower surface side of the lower surface side terminal and the other end side of the auxiliary terminal side terminal. Facing each other, and being sealed with resin, leaving the lower end of the lower surface side terminal and the other end of the auxiliary terminal side terminal. 前記下面側端子と前記補助端子側端子とが前記樹脂内で各屈曲され、かつ、前記下面側端子の前記下段側の平面の下面及び前記補助端子側端子の前記他端側の下面が前記樹脂の下面と面一であることを特徴とする請求項１記載の半導体素子。The lower surface side terminal and the auxiliary terminal side terminal are each bent in the resin, and the lower surface of the lower surface of the lower surface side terminal and the lower surface of the auxiliary terminal side terminal on the other end side are the resin. The semiconductor device according to claim 1, wherein the semiconductor device is flush with a lower surface of the semiconductor device. 前記補助端子は、前記上面電極と同じ幅の狭幅部を有する平面状の板を屈曲させることによって形成され、前記電極接続部は、前記狭幅部での屈曲によって設けられた前記狭幅部における１つの段差部であり、The auxiliary terminal is formed by bending a planar plate having a narrow portion having the same width as the upper surface electrode, and the electrode connecting portion is provided by bending at the narrow portion. One step in
前記補助端子は、前記電極接続部と反対側の端部において前記補助端子側端子の前記一端側と電気的に接続され、前記反対側の端部は、前記補助端子側端子よりも幅広に構成されていることを特徴とする請求項１記載の半導体素子。  The auxiliary terminal is electrically connected to the one end side of the auxiliary terminal side terminal at an end opposite to the electrode connecting portion, and the opposite end is configured to be wider than the auxiliary terminal side terminal. 2. The semiconductor element according to claim 1, wherein the semiconductor element is formed. 前記電極接続部は、平面状の板を、その一部においてコの字形に切り抜き、切り残した部分を屈曲させることによって設けられた１つの段差部であることを特徴とする請求項１記載の半導体素子。2. The electrode connecting portion according to claim 1, wherein the electrode connecting portion is a step portion provided by cutting a planar plate into a U-shape at a part thereof and bending the left portion. Semiconductor element. 前記補助端子は、前記電極接続部と反対側の端部に、下面方向に１回折り曲げられた折り曲げ部を有し、前記折り曲げ部の内側が前記補助端子側端子の前記一端に宛がわれた状態で、前記補助端子側端子に接続されることを特徴とする請求項１記載の半導体素子。The auxiliary terminal has a bent portion bent once in the lower surface direction at the end opposite to the electrode connecting portion, and the inside of the bent portion is assigned to the one end of the auxiliary terminal side terminal. 2. The semiconductor element according to claim 1, wherein the semiconductor element is connected to the auxiliary terminal side terminal in a state.
JP30967799A 1999-10-29 1999-10-29 Semiconductor element Expired - Lifetime JP4329187B2 (en)

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