JP3596388B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3596388B2
JP3596388B2 JP33312499A JP33312499A JP3596388B2 JP 3596388 B2 JP3596388 B2 JP 3596388B2 JP 33312499 A JP33312499 A JP 33312499A JP 33312499 A JP33312499 A JP 33312499A JP 3596388 B2 JP3596388 B2 JP 3596388B2
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JP
Japan
Prior art keywords
semiconductor chip
members
heat radiating
pair
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP33312499A
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Japanese (ja)
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JP2001156219A5 (en
JP2001156219A (en
Inventor
豊 福田
好美 中瀬
和仁 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP33312499A priority Critical patent/JP3596388B2/en
Priority to US09/717,227 priority patent/US6703707B1/en
Priority to FR0015130A priority patent/FR2801423B1/en
Priority to DE10066441A priority patent/DE10066441B4/en
Priority to DE10066442A priority patent/DE10066442B4/en
Priority to DE10066443A priority patent/DE10066443B8/en
Priority to DE10066446A priority patent/DE10066446B4/en
Priority to DE10066445A priority patent/DE10066445B4/en
Priority to DE10058446A priority patent/DE10058446B8/en
Publication of JP2001156219A publication Critical patent/JP2001156219A/en
Priority to US10/321,365 priority patent/US6693350B2/en
Priority to US10/699,744 priority patent/US20040089940A1/en
Priority to US10/699,837 priority patent/US6960825B2/en
Priority to US10/699,746 priority patent/US6998707B2/en
Priority to US10/699,838 priority patent/US6798062B2/en
Priority to US10/699,785 priority patent/US6891265B2/en
Priority to US10/699,954 priority patent/US6967404B2/en
Priority to US10/699,828 priority patent/US6992383B2/en
Priority to US10/699,784 priority patent/US20040089941A1/en
Application granted granted Critical
Publication of JP3596388B2 publication Critical patent/JP3596388B2/en
Publication of JP2001156219A5 publication Critical patent/JP2001156219A5/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, with which heat radiation is improved and a dispersion in positions of packaged semiconductor chips is suppressed, concerning the semiconductor device having a configuration sandwiching both sides of a semiconductor chip with heat radiating members. SOLUTION: A projecting part 6 of a first heat radiating member 3 is bonded with the main electrodes of Si chips 1a and 1b on one side 5a through a solder 2 and the Si chips 1a and 1b are fitted and bonded to a recessed part 8 of a second heat radiating member 4 through the solder 2. Besides, in the state of engaging a spacer 13 to a protruding part 7a of the first heat radiating member 3, protruding parts 7a and 7b formed on the first and second heat radiating members 3 and 4 and protruded on the side of the Si chips 1a and 1b are fitted and caulked to hoes 12a and 12b formed on a lead frame 9.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップの上下から放熱する構成を有する半導体装置に関する。
【０００２】
【従来の技術】
半導体チップの上下から放熱を行っている半導体装置には、例えば、特開平４−２７１４５号公報に記載の発明がある。図１１は、この公報に記載の半導体装置の概略断面図である。図１１に示すように、半導体チップＪ１が下面放熱板Ｊ２に直接接着されており、下面および上面放熱板Ｊ２、Ｊ３が、これらの放熱板Ｊ２、Ｊ３に複数配列された結合ピンＪ４により接合されている。また、半導体チップＪ１とリードフレームＪ５とがワイヤボンドにより形成されたワイヤＪ６により電気的に接続されている。そして、これらの部材Ｊ１〜Ｊ６が樹脂Ｊ７により封止されている。
【０００３】
上記、従来公報に記載の半導体装置では、半導体チップＪ１の上下両側から放熱を行うようにしているものの、半導体チップＪ１の上面と上面放熱板Ｊ３とが直接接着されていない。そのため、半導体チップＪ１の上面から直接、上面放熱板Ｊ３に熱が伝わるのではなく、モールド樹脂Ｊ７を介して伝わることになり、半導体チップＪ１の上面からの放熱性が良くない。
【０００４】
それに対して、特開昭６１−１６６０５１号公報に記載の発明では、半導体チップの上下からモールド樹脂を介すことなく放熱を行っている。図１２は、この公報に記載の半導体装置の概略断面図である。図１２に示すように、半導体チップＪ１１がダイパッドＪ１２に固着されており、半導体チップＪ１１の上面に接着剤Ｊ１３を用いてチップ側放熱板Ｊ１４が接着されている。また、外部リードＪ１５と半導体チップＪ１１とがワイヤボンドにより形成されたワイヤＪ１６により電気的に接続されている。また、ダイパッドＪ１２における半導体チップＪ１１の搭載面とは反対側の面には、ダイパッド側放熱板Ｊ１７が接触しており、これらの部材Ｊ１１〜Ｊ１７が樹脂Ｊ１８により封止されている。
【０００５】
【発明が解決しようとする課題】
この後述の公報に記載の半導体装置は、前者公報に記載の半導体装置と比較して、半導体チップの上側に対しても放熱部材をモールド樹脂を介すことなく接触させているため放熱性が向上している。しかし、この後述の公報に記載の半導体装置では放熱板を接着剤Ｊ１３のみでチップに対して固定しているため、半導体チップを搭載する際に位置ずれ、即ち、半導体チップの搭載位置のばらつきが起こり易いという問題がある。
【０００６】
そのため、例えば、放熱板を電極として兼用し、特に半導体チップとしてパワー素子を用いる場合には、半導体チップの搭載位置がずれることにより、半導体チップの絶縁すべき領域において通電してしまう等の不具合がある。
【０００７】
本発明は、上記問題点に鑑み、半導体チップの両面を放熱部材で挟んでなる構成を有する半導体装置において、放熱性を改善し、半導体チップの搭載位置のばらつきを抑えた半導体装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記目的を達成するため、請求項１に記載の発明では、半導体チップ（１ａ、１ｂ）と、半導体チップ（１ａ、１ｂ）の両面を挟むように熱伝導性を有する接合部材（２）を介して接合した一対の放熱部材（３、４）と、半導体チップ（１ａ）における第１の放熱部材（３）と対向する面には制御電極が形成されており、制御電極と電気的に接続されるリードフレーム（９）とを備え、一対の放熱部材（３、４）は第１の放熱部材（３）と、半導体チップ（１ａ、１ｂ）と対向する面に凹部（８）を形成した第２の放熱部材（４）とよりなり、この凹部（８）内に半導体チップ（１ａ、１ｂ）を嵌め合わしていることを特徴としている。
【０００９】
本発明では、熱伝導性を有する接合部材（２）を介して、一対の放熱部材（３、４）を半導体チップ（１ａ、１ｂ）の両面と接合しているため、放熱性を改善することができる。また、第２の放熱部材（４）の凹部（８）に半導体チップ（１ａ、１ｂ）を嵌め合わせるため、半導体チップ（１ａ、１ｂ）の平面方向において、第２の放熱部材（４）と半導体チップ（１ａ、１ｂ）との相対位置を固定することができ、半導体チップ（１ａ、１ｂ）の搭載位置のばらつきを抑えた半導体装置を提供することができる。さらに、本発明の様に半導体チップ（１ａ）に制御電極が形成されていても、凸部（６）の形状を調節することにより、第１の放熱部材（３）と制御電極とが接触しない様にすることができる。
【００１０】
請求項２に記載の発明では、請求項１に記載の発明において、第１の放熱部材（３）における半導体チップ（１ａ、１ｂ）と対向する部位に、半導体チップ（１ａ、１ｂ）側に突出した凸部（６）を形成し、この凸部（６）を半導体チップ（１ａ、１ｂ）と接合部材（２）を介して接合することを特徴としている。
【００１１】
本発明によれば、第２の放熱部材（４）の凹部（８）により半導体チップ（１ａ、１ｂ）の位置決めを行った状態で、第１の放熱部材（３）に凸部（６）を形成しているため、凸部（６）の形状を調節することにより、第１の放熱部材（３）を半導体チップ（１ａ、１ｂ）の所望の領域のみと適切に接合させることができる。
【００１４】
請求項３に記載の発明では、請求項１又は２に記載の発明において、一対の放熱部材（３、４）における半導体チップ（１ａ、１ｂ）との対向面の少なくとも一方には突起部（７ａ、７ｂ）を形成し、リードフレーム（９）に形成した穴（１２ａ、１２ｂ）と突起部（７ａ、７ｂ）とを嵌め合わせることにより、一対の放熱部材（３、４）の少なくとも一方をリードフレーム（９）に固定することを特徴としている。
【００１５】
本発明によれば、リードフレーム（９）に対して一対の放熱部材（３、４）の少なくとも一方を固定して位置決めでき、放熱部材（３、４）の位置決め精度を向上させることができるため、半導体チップ（１ａ、１ｂ）の平面方向における搭載位置のばらつきを、さらに抑えた半導体装置を提供することができる。特に、一対の放熱部材（３、４）の両方をリードフレーム（９）に対して固定する場合は、このばらつきを確実に抑えることができる。
【００１６】
なお、この固定は、かしめにより行っても良いし、その他、半田などにより固定しても良い。
【００１７】
請求項４に記載の発明では、請求項１又は２に記載の発明において、一対の放熱部材（３、４）における半導体チップ（１ａ、１ｂ）との対向面の少なくとも一方に突起部（７ａ、７ｂ）を形成し、当該放熱部材（３、４）とリードフレーム（９）との間にスペーサ（１３）を介在した状態で、リードフレーム（９）に形成した穴（１２ａ、１２ｂ）と突起部（７ａ、７ｂ）とを嵌め合わせて固定し、スペーサ（１３）によって当該放熱部材（３、４）と半導体チップ（１ａ、１ｂ）との、半導体チップ（１ａ、１ｂ）の厚み方向における位置決めをしていることを特徴としている。
【００１８】
これにより、半導体チップ（１ａ、１ｂ）の平面方向に加えて厚み方向にも位置を固定できるため、半導体チップ（１ａ、１ｂ）の搭載位置のばらつきを、より確実に抑えた半導体装置を提供することができる。
【００１９】
請求項５に記載の発明では、半導体チップ（１ａ、１ｂ）と、半導体チップ（１ａ、１ｂ）の両面を挟むように熱伝導性を有する接合部材（２）を介して接合した一対の放熱部材（３、４）とを設け、一対の放熱部材（３、４）は、半導体チップ（１ａ、１ｂ）と対向する部位に、半導体チップ（１ａ、１ｂ）側に突出した凸部（６）を形成した第１の放熱部材（３）と、第２の放熱部材（４）とよりなり、この凸部（６）が、接合部材（２）を介して半導体チップ（１ａ、１ｂ）に接合し、半導体チップ（１ａ）における第１の放熱部材（３）と対向する面に形成した制御電極と電気的に接続するリードフレーム（９）を設け、一対の放熱部材（３、４）における半導体チップ（１ａ、１ｂ）との対向面の少なくとも一方には突起部（７ａ、７ｂ）を形成していることを特徴としている。
【００２０】
さらに、リードフレーム（９）に形成した穴（１２ａ、１２ｂ）と、突起部（７ａ、７ｂ）とを嵌め合わせて固定することにより、一対の放熱部材（３、４）の少なくとも一方をリードフレーム（９）に固定し、一対の放熱部材（３、４）とリードフレーム（９）との間に生じる隙間にスペーサ（１３）を介在し、このスペーサ（１３）によって一対の放熱部材（３、４）と半導体チップ（１ａ、１ｂ）との、半導体チップ（１ａ、１ｂ）の厚み方向における位置決めをすることを特徴としている。
【００２１】
本発明の様に、第１の放熱部材（３）に形成した凸部（６）を半導体チップ（１ａ、１ｂ）に接合するようにすると、半導体チップ（１ａ、１ｂ）に接続されるリードフレーム（９）と一対の放熱部材（３、４）との間には、凸部（６）の段差によって隙間が生じるが、この隙間にスペーサ（１３）を介在させてリードフレームに形成した穴（１２ａ、１２ｂ）と一対の放熱部材（３、４）の突起部（７ａ、７ｂ）とを嵌め合わせて固定することにより、半導体チップ（１ａ、１ｂ）の平面方向にも厚み方向にも、半導体チップ（１ａ、１ｂ）と一対の放熱部材（３、４）との相対位置のばらつきを抑えた半導体装置を提供することができる。
【００２２】
請求項６に記載の発明では、請求項１ないし５のいずれか１つに記載の発明において、一対の放熱部材（３、４）として、半導体チップ（１ａ、１ｂ）に線膨張率が近似した金属を用いることを特徴としている。
【００２３】
これにより、半導体チップ（１ａ、１ｂ）と各々の放熱部材（３、４）との線膨張率が異なることに起因する熱応力の発生を抑制することができ、接合部材（２）に対する歪みの集中を防止することができる。
【００２４】
請求項７に記載の発明では、請求項１ないし６のいずれか１つに記載の発明において、一対の放熱部材（３、４）として、銅の内部において、インバーおよびモリブデンのうちの少なくとも１つが、部分的に複数配置されているものを用いることを特徴としている。
【００２５】
本発明によれば、銅の内部にインバーやモリブデンを配置した金属は、半導体チップ（１ａ、１ｂ）と線膨張率が近似しているため、請求項６に記載の発明と同様の効果を発揮することができる。また、インバーやモリブデンは銅と比較すると放熱性が劣るが、銅の内部に部分的に配置することにより、放熱性も十分に確保することができる。
【００２６】
請求項８に記載の発明では、請求項１ないし７のいずれか１つに記載の発明において、一対の放熱部材（３、４）の各々の面のうち、半導体チップ（１ａ、１ｂ）と対向する面とは反対側の面が露出した状態で、一対の放熱部材（３、４）および半導体チップ（１ａ、１ｂ）を樹脂封止していることを特徴としている。
【００２７】
これにより、一対の放熱部材（３、４）を構成する第１の放熱部材（３）と第２の放熱部材（４）との絶縁を確実に行うことができる。また、露出した面を冷却することにより、的確に放熱を行うことができる。
【００２８】
請求項９に記載の発明では、請求項１ないし８のいずれか１つに記載の発明において、一対の放熱部材（３、４）が、半導体チップ（１ａ、１ｂ）の電極として用いられることを特徴としている。
【００２９】
一対の放熱部材（３、４）を電極として利用し、各々の放熱部材（３、４）の間の電位差が大きい場合には、各々の放熱部材（３、４）と半導体チップ（１ａ、１ｂ）との相対位置がずれることにより、絶縁されるべき部分が通電してしまう恐れがある。しかし、本発明では、半導体チップ（１ａ、１ｂ）と各々の放熱部材（３、４）との相対位置のばらつきが抑えられているため、各々の放熱部材（３、４）を電極として用いても好適である。
【００３０】
なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。
【００３１】
【発明の実施の形態】
（第１実施形態）
図１は、第１実施形態の半導体装置を上面から見た模式図であり、図２（ａ）は、図１におけるＢ−Ｂ断面を模式的に示す図であり、図２（ｂ）は、図１におけるＤ−Ｄ断面を模式的に示す図である。図１および図２に示すように、平面的に配置された２つの半導体チップとしてのＳｉチップ１ａ、１ｂに対して、それらのＳｉチップ１ａ、１ｂの両面を挟む様にして、熱伝導性を有する接合部材２を介して一対の放熱部材である第１および第２の放熱部材３、４が接合されている。
【００３２】
Ｓｉチップ１ａのワイヤボンドされている側の面である一面５ａに対しては、第１の放熱部材３が接合されており、Ｓｉチップ１ａ、１ｂにおける一面５ａの反対側の面である他面５ｂに対しては、第２の放熱部材４が接合されている。この第２の放熱部材４は、図１においては、一部、他の部材と重なっている部分を二点鎖線で示してある。また、Ｓｉチップ１ａ、１ｂは、図１において他の部材と重なっている部分を一点鎖線で示してある。
【００３３】
ここで、Ｓｉチップ１ａ、１ｂとしては、本例では、図１においてワイヤボンドされているＳｉチップがＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）チップ１ａであり、もう一方のＳｉチップがフライホイールダイオードチップ１ｂである。ＩＧＢＴチップ１ａにおいては、それぞれ、第１の放熱部材３がエミッタ端子、第２の放熱部材４がコレクタ端子となっている。また、ＩＧＢＴチップ１ａにおける第１の放熱部材３と対向する面には、外部との電気的な信号の授受を行うための制御電極（図示せず）がゲートとして形成されており、インナーリード１０とワイヤボンドされている。
【００３４】
ＩＧＢＴチップ１ａの等価回路は、例えば図３に示すようにコレクタＣ、エミッタＥ、ゲートＧ、電流検出用端子Ｉｓ、感温のためのダイオード端子であるアノードＡおよびカソードＫからなる。
【００３５】
図１および図２に示すように、第１の放熱部材３は平面形状は略矩形であり、その対角から相反する方向へ短冊状に伸びている短冊部３ａ、３ｂが２個所設けられている。一方、厚み方向には、各々のＳｉチップ１ａ、１ｂの一面５ａ側の主電極と対向する部位に、Ｓｉチップ１ａ、１ｂ側に突出した凸部６が形成されている。そして、凸部６の先端は平面あるいはＳｉチップ１ａ、１ｂとの接合に支障を来さない程度に平面であり、この平面部の形状は対向するＳｉチップ１ａ、１ｂの主電極の平面形状に対応している。
【００３６】
また、第１の放熱部材３のＳｉチップ１ａ、１ｂとの対向面における各々の短冊部３ａ、３ｂ、および矩形部の各辺のうち短冊部３ａ、３ｂが伸びている方向に平行な辺の内側の計３個所において、Ｓｉチップ１ａ、１ｂ側に突出した突起部７ａが形成されている。
【００３７】
第２の放熱部材４は、平面形状は第１の放熱部材３とほぼ同じである。ただし、第２の放熱部材４における２つの短冊部４ａ、４ｂは、第１の放熱部材３の各々の短冊部３ａ、３ｂと異なる位置に設けられている。一方、厚み方向には、Ｓｉチップ１ａ、１ｂと対向する部分においてＳｉチップ１ａ、１ｂが嵌まるような凹部８が形成されている。この凹部８の深さは、例えば、０．１〜０．３ｍｍ程度にすることができる。
【００３８】
また、第２の放熱部材４のＳｉチップ１ａ、１ｂとの対向面における各々の短冊部４ａ、４ｂ、および矩形部の各辺のうち短冊部４ａ、４ｂが伸びている方向に平行な辺の内側の計３個所において、Ｓｉチップ１ａ、１ｂ側に突出した突起部７ｂが形成されている。ただし、これらの第２の放熱部材４に形成された突起部７ｂは第１の放熱部材３に形成された突起部７ａと上面方向から見た場合に重ならないような位置にある。
【００３９】
また、第１および第２の放熱部材３、４は、例えばＣｕ（銅）等を用いている。接合部材２としては、高熱伝導接着部材を用いており、その様な部材としては、例えば半田やろう材などがある。
【００４０】
そして、各々のＳｉチップ１ａ、１ｂの他面５ｂ側が、第２の放熱部材４に形成された凹部８内に接合部材２を介して嵌め合わされて接合され、各々のＳｉチップ１ａ、１ｂの一面５ａ側の主電極には、接合部材２を介して第１の放熱部材３に形成された凸部６が接合されている。
【００４１】
また、Ｓｉチップ１ａ、１ｂの制御電極とリードフレーム９のインナーリード１０とがワイヤボンドによって形成されたワイヤ１１によって電気的に接続されている。リードフレーム９は図１においては、一部、他の部材と重なっている部分が点線で示されている。
【００４２】
また、リードフレーム９においては、後述のように、第１および第２の放熱部材３、４の突起部７ａ、７ｂと嵌め合わせるための穴１２ａ、１２ｂを有する固定部９ａ、９ｂが６個所に設けられている。ここで、ワイヤ１１としては、Ａｌ（アルミニウム）やＡｕ（金）等を用いることができ、リードフレーム９としては、例えばＣｕやＣｕ合金または４２合金等を用いることができる。
【００４３】
そして、図２（ｂ）に示すように、第２の放熱部材４に形成された突起部７ｂとリードフレーム９の固定部９ｂに形成された穴１２ｂとが嵌め合わされてかしめられている。また、第１の放熱部材３に形成された突起部７ａの全てには、第１の放熱部材３とリードフレーム９の固定部９ａとの間にスペーサ１３が介在されており、この状態で、この固定部９ａに形成された穴１２ａと、第１の放熱部材３に形成された突起部７ａとが嵌め合わされてかしめられている。
【００４４】
ここで、スペーサ１３は、例えばＣｕ等からなる円柱や角柱の金属であって、突起部７ａが貫通するための穴を有するものである。また、このスペーサ１３はＳｉチップ１ａ、１ｂと第１の放熱部材３との、Ｓｉチップ１ａ、１ｂの厚み方向における位置決めを行うためのものである。このスペーサ１３の大きさは、例えば、角柱の場合には、断面が一辺２ｍｍの正方形で厚みが０．６ｍｍ程度のものにすることができる。
【００４５】
そして、図１および図２に示すように、第１および第２の放熱部材３、４の各々の面のうちＳｉチップ１ａ、１ｂと対向する面とは反対側の面が露出した状態で、上述のように固定された各々のＳｉチップ１ａ、１ｂと各々の放熱部材３、４とが樹脂１４により封止されている。図１において、この樹脂１４の外枠が破線で示されている。ここで、第１および第２の放熱部材３、４における各々の短冊部３ａ、３ｂ、４ａ、４ｂのうち、インナーリード１０が形成された方向とは反対の方向に設けられている短冊部３ａ、４ａが樹脂１４の外部に出ており、この外部に出た短冊部３ａ、４ａがＳｉチップ１ａ、１ｂの外部電極となっている。
【００４６】
次に、上記半導体装置の製造方法について述べる。初めに、上述の図１および図２に示すような、リードフレーム９、第１および第２の放熱部材３、４を用意する。リードフレーム９は、例えばパンチング等により所望の形状に加工する。
【００４７】
図４は、第１および第２の放熱部材３、４の形成方法の模式図である。図４（ａ）に示すように、Ｃｕ等よりなるリール形状の部材１５から、プレス加工用のパンチ１６とダイ１７を用いて、パンチ１６を矢印Ｆの方向に動かしてプレス加工することにより第１および第２の放熱部材３、４を切り出し、第１の放熱部材３に対しては凸部６を、第２の放熱部材４に対しては凹部８をそれぞれ形成する。
【００４８】
図４（ｂ）は突起部７ａ、７ｂを形成する工程図であるが、この図に示すように、突起部７ａ、７ｂ形成用のパンチ１８と中央に凹部が形成されたダイ１９を用いて、パンチ１８を矢印Ｈの方向に動かすことにより、押し出し加工を行い突起部７ａ、７ｂを形成する。
【００４９】
次に、Ｓｉチップ１ａ、１ｂと上述の様にして加工したリードフレーム９と第１および第２の放熱部材３、４とを組み付ける。図５は、この組み付けの際に側面方向から見た各々の部材１ａ、１ｂ、２〜４、９の構成を模式的に示す図である。図５に示すように、第２の放熱部材４の突起部７ｂにリードフレーム９の固定部９ｂの穴１２ｂを嵌め合わせてかしめ、各々の凹部８には接合部材としての半田箔２を介してＳｉチップ１ａ、１ｂの他面５ｂ側を嵌め合わせる。
【００５０】
また、各々のＳｉチップ１ａ、１ｂの一面５ａ上に主電極形状に対応した半田箔２を載せ、第１の放熱部材３の突起部７ａにはスペーサ１３をかませて、この突起部７ａとリードフレーム９の固定部９ａの穴１２ａとを嵌め合わせてかしめる。なお、図５は模式図であるため、第１の放熱部材３における凸部６は省略している。
【００５１】
ここで、この組み付けの際のかしめ固定について詳しく述べる。図６はかしめ固定の工程を模式的に示す図である。図６に示すように、第１および第２の放熱部材３、４の突起部７ａ、７ｂとリードフレーム９の固定部９ａ、９ｂの穴１２ａ、１２ｂとを嵌め合わせた後、パンチ２０を矢印Ｉの方向に動かすことにより穴１２ａ、１２ｂから出た突起部７ａ、７ｂをつぶし、第１および第２の放熱部材３、４とリードフレーム９とを固定する。
【００５２】
続いて、上述の様にかしめ固定したＳｉチップ１ａ、１ｂ、各々の放熱部材３、４およびリードフレーム９を、水素炉等に通して半田リフローすることにより、各々の部材１ａ、１ｂ、３、４を半田付け固定する。その後、ＩＧＢＴチップ１ａの一面５ａ側の制御電極とリードフレーム９とのワイヤボンディングを行った後、トランスファーモールドで樹脂１４により封止することにより、第１の放熱部材３と第２の放熱部材４との絶縁を行い、本実施形態の半導体装置が完成する。
【００５３】
ところで、本実施形態によれば、第１および第２の放熱部材３、４を接合部材２を介して、Ｓｉチップ１ａ、１ｂの一面５ａおよび他面５ｂに直接接合させているため放熱性を改善することができる。また、前述の、特開昭６１−１６６０５１号公報に記載の発明では、半導体チップとチップ側の放熱板とが、ポリイミド樹脂やシリコーン樹脂などの樹脂性の接着剤のみで固定されており、この様な接着剤は熱伝導性が悪いため放熱性を阻害するという問題があった。しかし、本実施形態では、接合部材２として半田やろう材などの高熱伝導接着部材を用いているため、放熱性を改善することができる。
【００５４】
また、第２の放熱部材４の凹部８にＳｉチップ１ａ、１ｂを嵌め合わせることにより第２の放熱部材４に対してＳｉチップ１ａ、１ｂを固定し、第１および第２の放熱部材３、４の各々の突起部７ａ、７ｂとリードフレーム９の固定部９ａ、９ｂの穴１２ａ、１２ｂとを嵌め合わせてかしめることにより、各々の放熱部材３、４とリードフレーム９とを固定することができる。その結果、Ｓｉチップ１ａ、１ｂの平面方向におけるこれらの部材の相対位置を固定することができる。
【００５５】
また、第１の放熱部材３の突起部７ａに対してスペーサ１３を介在した状態で、第１の放熱部材３の突起部７ａとリードフレーム９の固定部９ａの穴１２ａとを嵌め合わせてかしめているため、Ｓｉチップ１ａ、１ｂの搭載空間を確保した状態で第１の放熱部材３をリードフレーム９に固定することができ、Ｓｉチップ１ａ、１ｂの厚み方向にも相対位置を固定できる。従って、Ｓｉチップ１ａ、１ｂの平面方向にも厚み方向にも各々の部材の相対位置を固定でき、半導体チップの搭載位置のばらつきを抑えた半導体装置を提供することができる。
【００５６】
また、本実施形態の様に、半導体チップとしてＩＧＢＴなどのパワー素子を用いる場合は、以下に示す絶縁に関する問題がある。図７は、ＩＧＢＴの一例を示す部分断面図である。
【００５７】
図７に示すように、例えばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等のパワー素子には、その端部においてガードリング２１やＥＱＲ（同電位リング）２２が形成されているが、これらはコレクタ電極２３とほぼ同電位となっている。ガードリング２１やＥＱＲ２２はパワー素子のエミッタ電極２４側の面に形成されており、エミッタ電極２４の近傍にコレクタ電極２３と同電位であるガードリング２１やＥＱＲ２２が存在することになる。
【００５８】
従って、エミッタ電極２４とコレクタ電極２３間の電位差が、例えば６００Ｖ程度となるようなパワー素子の場合、ガードリング２１やＥＱＲ２２とエミッタ電極２４との電位差が６００Ｖ程度となる。そのため、半田付けエリアが周囲部におよぶ、例えば、放熱部材２５が図７の白抜き矢印Ｊに示すように、通常の位置よりもガードリング２１やＥＱＲ２２側にずれる等することにより、半田等の接合部材２６や放熱部材２５を介して、直接、あるいは放電によりガードリング２１やＥＱＲ２２とエミッタ電極２４との間で通電してしまう可能性がある。
【００５９】
また、通電を妨げるために、ガードリング２１やＥＱＲ２２の上面にポリイミド等からなる保護膜２７を被覆しても、その膜の厚さは１〜２μｍ程度であり、６００Ｖもの絶縁耐圧は確保できない。
【００６０】
しかし、本実施形態の半導体装置では、上述の様に、Ｓｉチップ１ａ、１ｂ、リードフレーム９、および、第１および第２の放熱部材３、４の相対位置を固定した状態で、第１の放熱部材３に凸部６を設け、この凸部６をＳｉチップ１ａ、１ｂの一面５ａの主電極に接合している。そのため、凸部６の形状を調節して第１の放熱部材３を主電極のみと接合させることができ、さらに、上述のようなＳｉチップ１ａ、１ｂと第１の放熱部材３との相対位置がずれることに起因する絶縁に関する問題も解決することができる。
【００６１】
なお、本実施形態では、スペーサ１３は第１の放熱部材３に形成された突起部７ａにかませる例について示したが、例えば、各々の放熱部材３、４に対して突起部７ａ、７ｂを形成する際に、図４（ｂ）に示す押し出し加工用のダイ１９の凹部を段状にしておく等して、段状の突起部を形成して、スペーサを一体で形成しても良い。
【００６２】
また、スペーサ１３は、第１の放熱部材３の突起部７ａに設けることに限定するものではなく、必要であれば第２の放熱部材４の突起部７ｂに設け、Ｓｉチップ１ａ、１ｂの厚み方向におけるＳｉチップ１ａ、１ｂ、各々の放熱部材３、４およびリードフレーム９の相対位置を決定しても良い。
【００６３】
また、本実施形態のように、第１および第２の放熱部材３、４の両方をそれぞれリードフレーム９に対してかしめ固定すれば、確実に半導体チップの搭載位置のばらつきを抑えることができるが、第１および第２の放熱部材３、４のうち、どちらか一方のみをかしめ固定し、この放熱部材３、４の位置決め精度を向上させ、半導体チップの搭載位置のばらつきを改善できるのであれば、一方の放熱部材３、４のみかしめ固定しても良い。
【００６４】
また、各々の放熱部材３、４のうちのＳｉチップ１ａ、１ｂと対向する面が樹脂１４から露出しているが、例えば、この露出している部分を冷却部材に接触させるなどして放熱を促すことができる。
【００６５】
また、本実施形態では、半導体チップとしてＩＧＢＴチップ１ａを用いる例について示しており、上述のような絶縁に関する問題を解決するために、本実施形態の様な半導体チップの搭載位置のばらつきを抑えることができる構成にすると、その効果が特に発揮されるが、各々の放熱部材３、４を電極として使用しない場合も、放熱性を改善したり、半導体チップの搭載位置のばらつきを抑えるためには、本実施形態の構成が好適である。
【００６６】
また、第１の放熱部材３に形成された突起部７ａの全て（本例では３個所）にスペーサ１３を設ける例について示したが、最低２個所に設ければＳｉチップ１ａ、１ｂの厚み方向における、第１の放熱部材３とＳｉチップ１ａ、１ｂとの相対位置を固定することができる。また、接合部材２として半田箔を用いる例について示したが、半田ペースト等を用いても良い。また、半導体チップ１ａ、１ｂは１つでも良い。
【００６７】
（第２実施形態）
ＩＧＢＴチップ１ａは電流容量が１００Ａ以上のものになるとチップサイズが大きくなり、１０〜１６ｍｍ程度となるものがある。この場合、各々の放熱部材３、４としてＣｕを用いている場合は、Ｃｕの線膨張率がＩＧＢＴチップ１ａを構成するＳｉの線膨張率の５〜６倍であるため、冷熱サイクルにおいて接合部材２である半田が熱疲労し、亀裂が発生して熱抵抗が増大し、熱放散性（放熱性）が悪化することが懸念される。
【００６８】
そこで、この様な不具合を改善するための実施形態が第２実施形態である。図８は、第２実施形態の半導体装置の概略断面図である。本実施形態は、第１および第２の放熱部材３、４として用いられる材料が第１実施形態と異なるものである。以下、主として、図２（ａ）と異なるところについて述べ、同一部分には図８中、同一符号を付して説明を簡略化する。
【００６９】
図８に示すように、第１および第２の放熱部材３、４として、Ｓｉチップ１ａ、１ｂと線膨張率が近似した金属を用い、その一例としてインバーよりなる部材（以下、インバー部材という）２８をＣｕよりなる部材（以下、Ｃｕ部材という）２９で挟んだ構成をなすクラッド材（以下、ＣＩＣという）を用いるものである。そして、ＣＩＣのインバー部材２８とＣｕ部材２９の厚さの比や全体の厚さを調節して、可能な限りＳｉの線膨張率に近くなるようにしている。その他の各々の部材や部材の形状等は、上記、第１実施形態に示すものと同様である。
【００７０】
本実施形態によれば、各々の放熱部材３、４の線膨張率がＳｉチップ１ａ、１ｂの線膨張率に近似しているため、Ｓｉチップ１ａ、１ｂのサイズが大きい場合にも、Ｓｉチップ１ａ、１ｂと各々の放熱部材３、４との線膨張率が異なることに起因する熱応力の発生を抑制することができ、接合部材２に対する歪みの集中を防止することができる。その結果、各々の放熱部材３、４とＳｉチップ１ａ、１ｂとの接合性の低下を防ぐことができるため、放熱性の低下や、各々の放熱部材３、４を電極として用いている場合には電気伝導性の低下も防ぐことができる。
【００７１】
なお、インバーの代わりにＭｏ（モリブデン）を用いても、同様の効果を発揮することができる。また、各々の放熱部材３、４において、Ｃｕ部材２９の間に挟む材料をインバー部材２８あるいはＭｏよりなる部材（以下、Ｍｏ部材という）に統一しなくても、異なっていても良い。また、特に各々の放熱部材３、４としてクラッド材を用いることに限定するものではなく、Ｃｕ−Ｍｏの合金など、Ｓｉと線膨張率が近似した部材を用いれば良い。
【００７２】
ところで、上記、第２実施形態は、各々の放熱部材３、４として線膨張率がＳｉに近似した金属を用いる例について示しており、その一例としてＣＩＣ等のクラッド材を用いている。しかし、インバーやＭｏはＣｕと比較して熱伝導性が劣るため、Ｓｉチップ１ａ、１ｂの厚み方向におけるインバー部材２８やＭｏ部材の存在により放熱性が低下するという問題がある。そこで、この問題を改善するための変形例を以下に示す。
【００７３】
本変形例は、ＣＩＣのインバー部材２８を部分的に複数内層させるものである。図９は、このインバー部材２８を部分的に複数内層させたＣＩＣの模式的な図であり、（ａ）はＣＩＣをインバー部材２８を含む部分において層に対して平行に切断した断面図であり、（ｂ）はＣＩＣをインバー部材２８を含む部分において層に対して垂直に切断した断面図である。
【００７４】
図９に示すように、本変形例では、Ｃｕ部材２９の内部においてインバー部材２８を部分的に複数配置しており、本例では、Ｃｕ部材２９の内部の４個所に、インバー部材２８を配置させている。これにより、各々の放熱部材３、４の厚み方向においてＣｕ部材２９のみからなる部分を設けることができるため、各々の放熱部材３、４の厚み方向における熱伝導性を犠牲にすることはない。従って、放熱性を確保した上でＳｉと線膨張率が近似した放熱部材を提供することができる。
【００７５】
なお、本変形例では、Ｃｕ部材２９の内部の４個所にインバー部材２８を設けているが、各々の寸法が小さいインバー部材を数多く設ける等して、細かいメッシュ状にしても良い。また、インバー部材の代わりにＭｏ部材を用いても良い。また、インバー部材とＭｏ部材とを併用しても良い。
【００７６】
（他の実施形態）
図１０は、他の実施形態の半導体装置の概略断面図である。上記、第１および第２実施形態においては、ＩＧＢＴチップ１ａの一面５ａ側の制御電極とインナーリード１０との電気的な接続をワイヤボンドにより行っているが、図１０に示すように、半田等のバンプ形状の接合部材３０により行っても良い。
【００７７】
これにより、第１および第２の放熱部材３、４とＳｉチップ１ａ、１ｂとを半田付けする際に、このインナーリード１０と制御電極との接続も一括して行うことができるため、製造工程を短縮することができる。
【図面の簡単な説明】
【図１】第１実施形態の半導体装置を上面から見た模式図である。
【図２】第１実施形態の半導体装置の概略断面図である。
【図３】ＩＧＢＴチップの等価回路を示す図である。
【図４】各々の放熱部材の形成方法の模式図である。
【図５】半導体装置の製造過程において側面方向から見た構成を模式的に示す図である。
【図６】かしめ固定の工程を模式的に示す図である。
【図７】ＩＧＢＴチップの一例を示す部分断面図である。
【図８】第２実施形態の半導体装置の概略断面図である。
【図９】第２実施形態の変形例で用いる放熱部材の模式的な断面図である。
【図１０】他の実施形態の半導体装置の概略断面図である。
【図１１】従来公報に記載の半導体装置の概略断面図である。
【図１２】他の従来公報に記載の半導体装置の概略断面図である。
【符号の説明】
１ａ、１ｂ…半導体チップ、２…接合部材、３…第１の放熱部材、
４…第２の放熱部材、６…凸部、７ａ、７ｂ…突起部、８…凹部、
９…リードフレーム、１２ａ、１２ｂ…穴、１３…スペーサ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a structure for radiating heat from above and below a semiconductor chip.
[0002]
[Prior art]
An example of a semiconductor device that dissipates heat from above and below a semiconductor chip is disclosed in Japanese Patent Laid-Open No. 4-27145. FIG. 11 is a schematic cross-sectional view of the semiconductor device described in this publication. As shown in FIG. 11, the semiconductor chip J1 is directly bonded to the lower surface radiator plate J2, and the lower surface and the upper surface radiator plates J2 and J3 are joined by a plurality of coupling pins J4 arranged on these radiator plates J2 and J3. ing. Further, the semiconductor chip J1 and the lead frame J5 are electrically connected by a wire J6 formed by wire bonding. And these members J1-J6 are sealed with resin J7.
[0003]
In the semiconductor device described in the above-mentioned conventional publication, heat is radiated from both the upper and lower sides of the semiconductor chip J1, but the upper surface of the semiconductor chip J1 and the upper surface heat radiating plate J3 are not directly bonded. For this reason, heat is not directly transmitted from the upper surface of the semiconductor chip J1 to the upper surface heat radiating plate J3, but is transmitted through the mold resin J7, and heat dissipation from the upper surface of the semiconductor chip J1 is not good.
[0004]
On the other hand, in the invention described in JP-A-61-166051, heat is radiated from above and below the semiconductor chip without using a mold resin. FIG. 12 is a schematic cross-sectional view of the semiconductor device described in this publication. As shown in FIG. 12, the semiconductor chip J11 is fixed to the die pad J12, and the chip-side heat dissipation plate J14 is bonded to the upper surface of the semiconductor chip J11 using an adhesive J13. Further, the external lead J15 and the semiconductor chip J11 are electrically connected by a wire J16 formed by wire bonding. Further, the die pad side heat radiating plate J17 is in contact with the surface of the die pad J12 opposite to the mounting surface of the semiconductor chip J11, and these members J11 to J17 are sealed with the resin J18.
[0005]
[Problems to be solved by the invention]
Compared with the semiconductor device described in the former publication, the semiconductor device described in this later publication improves heat dissipation because the heat dissipation member is in contact with the upper side of the semiconductor chip without using a mold resin. doing. However, in the semiconductor device described in the later-described publication, since the heat sink is fixed to the chip only with the adhesive J13, the position shift, that is, the variation in the mounting position of the semiconductor chip, occurs when the semiconductor chip is mounted. There is a problem that it is likely to occur.
[0006]
Therefore, for example, when a heat sink is also used as an electrode, and a power element is used as a semiconductor chip, there is a problem such as energization in a region to be insulated of the semiconductor chip due to a shift in the mounting position of the semiconductor chip. is there.
[0007]
In view of the above problems, the present invention provides a semiconductor device having a configuration in which both sides of a semiconductor chip are sandwiched between heat dissipation members, improving the heat dissipation and suppressing variations in the mounting positions of the semiconductor chips. With the goal.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, the semiconductor chip (1a, 1b) and the bonding member (2) having thermal conductivity so as to sandwich both surfaces of the semiconductor chip (1a, 1b) are interposed. A pair of heat dissipation members (3, 4) joined together,A control electrode is formed on a surface of the semiconductor chip (1a) facing the first heat dissipation member (3), and a lead frame (9) electrically connected to the control electrode;The pair of heat radiating members (3, 4) includes a first heat radiating member (3) and a second heat radiating member (4) in which a recess (8) is formed on a surface facing the semiconductor chip (1a, 1b). The semiconductor chip (1a, 1b) is fitted in the recess (8).
[0009]
In the present invention, the heat dissipation is improved because the pair of heat dissipation members (3, 4) are bonded to both surfaces of the semiconductor chip (1a, 1b) via the bonding member (2) having thermal conductivity. Can do. Further, in order to fit the semiconductor chip (1a, 1b) into the recess (8) of the second heat dissipation member (4), the second heat dissipation member (4) and the semiconductor are arranged in the plane direction of the semiconductor chip (1a, 1b). A relative position with respect to the chip (1a, 1b) can be fixed, and a semiconductor device in which variation in the mounting position of the semiconductor chip (1a, 1b) is suppressed can be provided.Furthermore, even if the control electrode is formed on the semiconductor chip (1a) as in the present invention, the first heat radiating member (3) and the control electrode do not come into contact with each other by adjusting the shape of the convex portion (6). Can be done.
[0010]
According to a second aspect of the present invention, in the first aspect of the present invention, the first heat dissipating member (3) protrudes toward the semiconductor chip (1a, 1b) at a portion facing the semiconductor chip (1a, 1b). The protruding portion (6) is formed, and the protruding portion (6) is bonded to the semiconductor chip (1a, 1b) via the bonding member (2).
[0011]
According to the present invention, in the state where the semiconductor chip (1a, 1b) is positioned by the concave portion (8) of the second heat radiating member (4), the convex portion (6) is formed on the first heat radiating member (3). Since it forms, the 1st heat radiating member (3) can be appropriately joined only to the desired area | region of a semiconductor chip (1a, 1b) by adjusting the shape of a convex part (6).
[0014]
Claim 3In the invention described inClaim 1 or 2The protrusions (7a, 7b) are formed on at least one of the surfaces of the pair of heat radiating members (3, 4) facing the semiconductor chip (1a, 1b) and formed on the lead frame (9). The holes (12a, 12b) and the projections (7a, 7b) are fitted together to fix at least one of the pair of heat radiation members (3, 4) to the lead frame (9).
[0015]
According to the present invention, at least one of the pair of heat radiation members (3, 4) can be fixed and positioned with respect to the lead frame (9), and the positioning accuracy of the heat radiation members (3, 4) can be improved. Thus, it is possible to provide a semiconductor device in which variations in mounting positions of the semiconductor chips (1a, 1b) in the planar direction are further suppressed. In particular, when both the pair of heat dissipating members (3, 4) are fixed to the lead frame (9), this variation can be reliably suppressed.
[0016]
This fixing may be performed by caulking, or may be fixed by soldering or the like.
[0017]
Claim 4In the invention described inClaim 1 or 2The protrusions (7a, 7b) are formed on at least one of the opposing surfaces of the pair of heat dissipation members (3, 4) to the semiconductor chip (1a, 1b), and the heat dissipation members (3, 4) With the spacer (13) interposed between the lead frame (9) and the holes (12a, 12b) and the protrusions (7a, 7b) formed in the lead frame (9), The heat radiation member (3, 4) and the semiconductor chip (1a, 1b) are positioned in the thickness direction of the semiconductor chip (1a, 1b) by the spacer (13).
[0018]
Accordingly, since the position can be fixed in the thickness direction in addition to the planar direction of the semiconductor chip (1a, 1b), a semiconductor device in which variation in the mounting position of the semiconductor chip (1a, 1b) is more reliably suppressed is provided. be able to.
[0019]
Claim 5In the invention described in the above, the semiconductor chip (1a, 1b) and a pair of heat radiation members (3, 3) joined via a joining member (2) having thermal conductivity so as to sandwich both surfaces of the semiconductor chip (1a, 1b). 4), and the pair of heat dissipating members (3, 4) are formed with protrusions (6) projecting toward the semiconductor chip (1a, 1b) at portions facing the semiconductor chips (1a, 1b). 1 radiating member (3) and second radiating member (4), and this convex portion (6) is joined to the semiconductor chip (1a, 1b) via the joining member (2). A lead frame (9) electrically connected to the control electrode formed on the surface facing the first heat dissipation member (3) in (1a) is provided, and the semiconductor chip (1a, Protrusions (7a, 7b) on at least one of the surfaces facing 1b) It is characterized in that it is formed.
[0020]
Further, the holes (12a, 12b) formed in the lead frame (9) and the protrusions (7a, 7b) are fitted and fixed, whereby at least one of the pair of heat radiation members (3, 4) is connected to the lead frame. (9), a spacer (13) is interposed in a gap formed between the pair of heat radiation members (3, 4) and the lead frame (9), and the pair of heat radiation members (3, 4) and the semiconductor chip (1a, 1b) are positioned in the thickness direction of the semiconductor chip (1a, 1b).
[0021]
When the convex portion (6) formed on the first heat radiating member (3) is joined to the semiconductor chip (1a, 1b) as in the present invention, the lead frame connected to the semiconductor chip (1a, 1b). A gap is formed between the (9) and the pair of heat radiation members (3, 4) due to the level difference of the convex portion (6). A hole formed in the lead frame with a spacer (13) interposed in the gap ( 12a, 12b) and the protrusions (7a, 7b) of the pair of heat radiating members (3, 4) are fitted and fixed so that the semiconductor chip (1a, 1b) in the planar direction or the thickness direction It is possible to provide a semiconductor device in which variation in relative position between the chip (1a, 1b) and the pair of heat radiation members (3, 4) is suppressed.
[0022]
Claim 6In the invention described inClaims 1 to 5In the invention described in any one of the above, the pair of heat dissipating members (3, 4) is characterized in that a metal whose linear expansion coefficient is similar to that of the semiconductor chip (1a, 1b) is used.
[0023]
Thereby, generation | occurrence | production of the thermal stress resulting from a difference in the linear expansion coefficient of a semiconductor chip (1a, 1b) and each heat radiating member (3, 4) can be suppressed, and distortion of a joining member (2) is suppressed. Concentration can be prevented.
[0024]
Claim 7In the invention described inClaims 1 to 6In the invention described in any one of the above, the pair of heat dissipating members (3, 4) may be one in which at least one of invar and molybdenum is partially disposed inside copper. It is a feature.
[0025]
According to the present invention, the metal in which invar and molybdenum are arranged inside copper has a linear expansion coefficient similar to that of the semiconductor chip (1a, 1b).Claim 6The same effects as those of the invention described in 1) can be exhibited. Invar and molybdenum are inferior in heat dissipation compared to copper, but by disposing them partially inside copper, the heat dissipation can be sufficiently secured.
[0026]
Claim 8In the invention described inClaims 1 to 7In the invention according to any one of the above, in a state where the surface opposite to the surface facing the semiconductor chip (1a, 1b) is exposed among the surfaces of the pair of heat radiation members (3, 4), The pair of heat dissipating members (3, 4) and the semiconductor chips (1a, 1b) are sealed with resin.
[0027]
Thereby, insulation with the 1st heat radiating member (3) and the 2nd heat radiating member (4) which comprise a pair of heat radiating members (3, 4) can be performed reliably. Moreover, heat can be accurately radiated by cooling the exposed surface.
[0028]
Claim 9In the invention described inClaims 1 to 8In the invention described in any one of the above, the pair of heat dissipating members (3, 4) is used as electrodes of the semiconductor chip (1a, 1b).
[0029]
When the pair of heat radiating members (3, 4) are used as electrodes and the potential difference between the heat radiating members (3, 4) is large, each heat radiating member (3, 4) and the semiconductor chip (1a, 1b) ) May be energized in a portion to be insulated. However, in the present invention, since the variation in relative position between the semiconductor chip (1a, 1b) and each heat radiating member (3, 4) is suppressed, each heat radiating member (3, 4) is used as an electrode. Is also suitable.
[0030]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a schematic view of the semiconductor device according to the first embodiment as viewed from above, FIG. 2A is a diagram schematically showing a cross section taken along line BB in FIG. 1, and FIG. FIG. 2 is a diagram schematically showing a DD cross section in FIG. 1. As shown in FIG. 1 and FIG. 2, thermal conductivity is improved by sandwiching both surfaces of the Si chips 1 a and 1 b as two semiconductor chips arranged in a plane. The first and second heat dissipating members 3 and 4 that are a pair of heat dissipating members are joined via the joining member 2 having the same.
[0032]
The first heat dissipating member 3 is bonded to the one surface 5a that is the wire-bonded surface of the Si chip 1a, and the other surface that is the surface opposite to the one surface 5a in the Si chips 1a and 1b. The second heat radiating member 4 is joined to 5b. In FIG. 1, the second heat radiating member 4 is partially indicated by an alternate long and two short dashes line. Further, in the Si chips 1a and 1b, portions overlapping with other members in FIG. 1 are indicated by alternate long and short dash lines.
[0033]
Here, as the Si chips 1a and 1b, in this example, the Si chip wire-bonded in FIG. 1 is an IGBT (Insulated Gate Bipolar Transistor) chip 1a, and the other Si chip is a flywheel diode chip 1b. is there. In the IGBT chip 1a, the first heat radiation member 3 is an emitter terminal, and the second heat radiation member 4 is a collector terminal. In addition, a control electrode (not shown) for exchanging electrical signals with the outside is formed as a gate on the surface of the IGBT chip 1a facing the first heat radiating member 3, and the inner lead 10 And wire bonded.
[0034]
The equivalent circuit of the IGBT chip 1a includes, for example, a collector C, an emitter E, a gate G, a current detection terminal Is, an anode A which is a diode terminal for temperature sensing, and a cathode K as shown in FIG.
[0035]
As shown in FIGS. 1 and 2, the first heat radiating member 3 has a substantially rectangular planar shape, and is provided with two strip portions 3 a and 3 b extending in a strip shape in opposite directions from the diagonal. Yes. On the other hand, in the thickness direction, convex portions 6 projecting toward the Si chips 1a, 1b are formed at portions facing the main electrodes on the one surface 5a side of the respective Si chips 1a, 1b. The tip of the convex portion 6 is a flat surface or a flat surface that does not hinder the bonding with the Si chips 1a and 1b. The shape of the flat surface portion is the flat shape of the main electrode of the opposing Si chips 1a and 1b. It corresponds.
[0036]
Further, of the sides of the first heat radiating member 3 facing the Si chips 1a, 1b, the strips 3a, 3b, and the sides of the rectangular part, the sides parallel to the direction in which the strips 3a, 3b extend. Protrusions 7a projecting toward the Si chips 1a and 1b are formed at a total of three locations inside.
[0037]
The planar shape of the second heat radiating member 4 is substantially the same as that of the first heat radiating member 3. However, the two strip portions 4 a and 4 b in the second heat radiating member 4 are provided at positions different from the respective strip portions 3 a and 3 b of the first heat radiating member 3. On the other hand, in the thickness direction, a recess 8 is formed so that the Si chips 1a and 1b can be fitted in portions facing the Si chips 1a and 1b. The depth of the concave portion 8 can be set to about 0.1 to 0.3 mm, for example.
[0038]
Further, each of the strip portions 4a and 4b on the surface of the second heat radiating member 4 facing the Si chips 1a and 1b, and the side parallel to the direction in which the strip portions 4a and 4b extend among the sides of the rectangular portion. Protrusions 7b projecting toward the Si chips 1a and 1b are formed at a total of three locations inside. However, the protrusions 7b formed on the second heat radiating member 4 are positioned so as not to overlap with the protrusions 7a formed on the first heat radiating member 3 when viewed from above.
[0039]
The first and second heat radiating members 3 and 4 use, for example, Cu (copper). As the joining member 2, a high thermal conductive adhesive member is used, and examples of such a member include solder and brazing material.
[0040]
And the other surface 5b side of each Si chip 1a, 1b is fitted and joined via the joining member 2 in the recessed part 8 formed in the 2nd heat radiating member 4, One surface of each Si chip 1a, 1b A convex portion 6 formed on the first heat radiating member 3 is joined to the main electrode on the 5a side via the joining member 2.
[0041]
In addition, the control electrodes of the Si chips 1a and 1b and the inner leads 10 of the lead frame 9 are electrically connected by wires 11 formed by wire bonding. In FIG. 1, a part of the lead frame 9 that overlaps with other members is indicated by a dotted line.
[0042]
Further, in the lead frame 9, as will be described later, there are six fixing portions 9a, 9b having holes 12a, 12b for fitting with the protruding portions 7a, 7b of the first and second heat radiating members 3, 4. Is provided. Here, Al (aluminum), Au (gold), or the like can be used as the wire 11, and Cu, Cu alloy, 42 alloy, or the like can be used as the lead frame 9, for example.
[0043]
As shown in FIG. 2 (b), the protrusion 7 b formed on the second heat radiating member 4 and the hole 12 b formed on the fixing portion 9 b of the lead frame 9 are fitted together and caulked. In addition, spacers 13 are interposed between the first heat radiating member 3 and the fixing portion 9a of the lead frame 9 in all the protrusions 7a formed on the first heat radiating member 3, and in this state, A hole 12a formed in the fixing portion 9a and a projection 7a formed in the first heat radiating member 3 are fitted together and caulked.
[0044]
Here, the spacer 13 is a columnar or prismatic metal made of Cu or the like, for example, and has a hole through which the protruding portion 7a passes. The spacer 13 is used for positioning the Si chips 1a, 1b and the first heat radiating member 3 in the thickness direction of the Si chips 1a, 1b. For example, in the case of a prism, the size of the spacer 13 can be a square with a cross section of 2 mm and a thickness of about 0.6 mm.
[0045]
And as shown in FIG. 1 and FIG. 2, in the state where the surface opposite to the surface facing the Si chips 1a and 1b is exposed among the surfaces of the first and second heat radiation members 3 and 4, The respective Si chips 1 a and 1 b fixed as described above and the respective heat radiation members 3 and 4 are sealed with a resin 14. In FIG. 1, the outer frame of the resin 14 is indicated by a broken line. Here, among the strip portions 3a, 3b, 4a and 4b in the first and second heat radiation members 3 and 4, the strip portion 3a provided in the direction opposite to the direction in which the inner lead 10 is formed. 4a is exposed to the outside of the resin 14, and the strip portions 3a and 4a which are exposed to the outside are external electrodes of the Si chips 1a and 1b.
[0046]
Next, a method for manufacturing the semiconductor device will be described. First, a lead frame 9 and first and second heat radiating members 3 and 4 as shown in FIGS. 1 and 2 are prepared. The lead frame 9 is processed into a desired shape by, for example, punching.
[0047]
FIG. 4 is a schematic view of a method of forming the first and second heat radiating members 3 and 4. As shown in FIG. 4 (a), by pressing the punch 16 from the reel-shaped member 15 made of Cu or the like in the direction of the arrow F using the punch 16 and the die 17 for press processing, The first and second heat radiating members 3 and 4 are cut out, and a convex portion 6 is formed for the first heat radiating member 3 and a concave portion 8 is formed for the second heat radiating member 4.
[0048]
FIG. 4B is a process diagram for forming the protrusions 7a and 7b. As shown in FIG. 4, a punch 18 for forming the protrusions 7a and 7b and a die 19 having a recess formed in the center are used. By moving the punch 18 in the direction of the arrow H, extrusion is performed to form the protrusions 7a and 7b.
[0049]
Next, the Si chips 1a and 1b, the lead frame 9 processed as described above, and the first and second heat radiating members 3 and 4 are assembled. FIG. 5 is a diagram schematically showing the configuration of each member 1a, 1b, 2-4, and 9 as viewed from the side surface during the assembly. As shown in FIG. 5, the holes 12b of the fixing portions 9b of the lead frame 9 are fitted into the protrusions 7b of the second heat radiating member 4 and caulked, and solder recesses 2 as bonding members are interposed in the respective recesses 8. The other surfaces 5b of the Si chips 1a and 1b are fitted together.
[0050]
Further, a solder foil 2 corresponding to the main electrode shape is placed on one surface 5a of each of the Si chips 1a and 1b, and a spacer 13 is sandwiched between the protrusion 7a of the first heat radiating member 3, and the protrusion 7a and The lead frame 9 is crimped by fitting with the hole 12a of the fixing portion 9a. In addition, since FIG. 5 is a schematic diagram, the convex part 6 in the 1st heat radiating member 3 is abbreviate | omitted.
[0051]
Here, the caulking and fixing during the assembly will be described in detail. FIG. 6 is a diagram schematically showing a caulking and fixing process. As shown in FIG. 6, after fitting the protrusions 7a and 7b of the first and second heat radiating members 3 and 4 with the holes 12a and 12b of the fixing portions 9a and 9b of the lead frame 9, the punch 20 is moved to the arrow. By moving in the direction I, the protrusions 7a and 7b protruding from the holes 12a and 12b are crushed, and the first and second heat radiating members 3 and 4 and the lead frame 9 are fixed.
[0052]
Subsequently, the Si chips 1a and 1b, which are caulked and fixed as described above, the heat dissipating members 3 and 4 and the lead frame 9 are soldered and reflowed through a hydrogen furnace or the like, whereby the respective members 1a, 1b, 4 is fixed by soldering. Then, after wire bonding between the control electrode on the one surface 5a side of the IGBT chip 1a and the lead frame 9, the first heat radiating member 3 and the second heat radiating member 4 are sealed with a resin 14 by transfer molding. The semiconductor device of this embodiment is completed.
[0053]
By the way, according to the present embodiment, the first and second heat radiating members 3 and 4 are directly bonded to the one surface 5a and the other surface 5b of the Si chips 1a and 1b via the bonding member 2, so that heat dissipation is achieved. Can be improved. In the invention described in Japanese Patent Laid-Open No. 61-166051, the semiconductor chip and the heat sink on the chip side are fixed only with a resinous adhesive such as polyimide resin or silicone resin. Such an adhesive has a problem of hindering heat dissipation due to poor thermal conductivity. However, in the present embodiment, since a high thermal conductive adhesive member such as solder or brazing material is used as the joining member 2, the heat dissipation can be improved.
[0054]
Further, the Si chips 1a and 1b are fixed to the second heat radiating member 4 by fitting the Si chips 1a and 1b into the recesses 8 of the second heat radiating member 4, and the first and second heat radiating members 3, 4 to fix the respective heat dissipating members 3 and 4 and the lead frame 9 by fitting the respective projections 7a and 7b 4 and the holes 12a and 12b of the fixing portions 9a and 9b of the lead frame 9 together. Can do. As a result, the relative positions of these members in the planar direction of the Si chips 1a and 1b can be fixed.
[0055]
Also, the protrusion 7 a of the first heat radiating member 3 and the hole 12 a of the fixing portion 9 a of the lead frame 9 are fitted together with the spacer 13 interposed with respect to the protrusion 7 a of the first heat radiating member 3. Therefore, the first heat radiating member 3 can be fixed to the lead frame 9 in a state where the mounting space for the Si chips 1a and 1b is secured, and the relative position can also be fixed in the thickness direction of the Si chips 1a and 1b. Therefore, the relative position of each member can be fixed both in the planar direction and in the thickness direction of the Si chips 1a and 1b, and a semiconductor device in which variations in the mounting positions of the semiconductor chips are suppressed can be provided.
[0056]
In addition, when a power element such as an IGBT is used as a semiconductor chip as in this embodiment, there are problems relating to insulation as described below. FIG. 7 is a partial cross-sectional view showing an example of an IGBT.
[0057]
As shown in FIG. 7, a power ring such as an IGBT (Insulated Gate Bipolar Transistor) has a guard ring 21 and an EQR (equal potential ring) 22 formed at the end thereof. The potential is almost the same. The guard ring 21 and the EQR 22 are formed on the surface of the power element on the emitter electrode 24 side, and the guard ring 21 and the EQR 22 having the same potential as the collector electrode 23 exist near the emitter electrode 24.
[0058]
Therefore, in the case of a power element in which the potential difference between the emitter electrode 24 and the collector electrode 23 is about 600 V, for example, the potential difference between the guard ring 21 or the EQR 22 and the emitter electrode 24 is about 600 V. For this reason, the soldering area extends to the peripheral portion. For example, as shown in the white arrow J in FIG. 7, the heat dissipating member 25 is shifted to the guard ring 21 or the EQR 22 side from the normal position. There is a possibility that the guard ring 21 or the EQR 22 and the emitter electrode 24 may be energized directly or by discharge through the bonding member 26 or the heat dissipation member 25.
[0059]
Further, even if the upper surface of the guard ring 21 or EQR 22 is covered with a protective film 27 made of polyimide or the like to prevent energization, the thickness of the film is about 1 to 2 μm, and a dielectric breakdown voltage of 600 V cannot be secured.
[0060]
However, in the semiconductor device of the present embodiment, as described above, the first positions of the Si chips 1a and 1b, the lead frame 9, and the first and second heat radiating members 3 and 4 are fixed. The heat radiating member 3 is provided with a convex portion 6, and this convex portion 6 is joined to the main electrode of the one surface 5a of the Si chips 1a, 1b. Therefore, the shape of the convex part 6 can be adjusted, and the 1st heat radiating member 3 can be joined only to a main electrode, and also relative position of the above-mentioned Si chip 1a, 1b and the 1st heat radiating member 3 It is also possible to solve the problem relating to insulation caused by the shift.
[0061]
In the present embodiment, the spacer 13 is shown as an example in which the spacer 13 is engaged with the protrusion 7 a formed on the first heat radiating member 3. For example, the protrusions 7 a and 7 b are provided on the heat radiating members 3 and 4. At the time of forming, the spacers may be integrally formed by forming stepped protrusions, for example, by making the recesses of the extrusion die 19 shown in FIG. 4B stepped.
[0062]
The spacer 13 is not limited to being provided on the protrusion 7a of the first heat radiating member 3. If necessary, the spacer 13 is provided on the protrusion 7b of the second heat radiating member 4, and the thickness of the Si chips 1a and 1b. The relative positions of the Si chips 1a, 1b, the heat radiation members 3, 4 and the lead frame 9 in the direction may be determined.
[0063]
Moreover, if both the first and second heat radiating members 3 and 4 are caulked and fixed to the lead frame 9 as in this embodiment, variations in the mounting positions of the semiconductor chips can be reliably suppressed. If only one of the first and second heat radiating members 3 and 4 is caulked and fixed, the positioning accuracy of the heat radiating members 3 and 4 can be improved, and the variation in the mounting position of the semiconductor chip can be improved. Alternatively, only one of the heat radiating members 3 and 4 may be fixed by caulking.
[0064]
Moreover, although the surface facing each Si chip 1a, 1b of each heat radiating member 3, 4 is exposed from the resin 14, for example, the exposed portion is brought into contact with the cooling member to radiate heat. Can be urged.
[0065]
Further, in the present embodiment, an example in which the IGBT chip 1a is used as a semiconductor chip is shown, and in order to solve the above-described problems related to insulation, variation in the mounting position of the semiconductor chip as in the present embodiment is suppressed. The effect is particularly exerted when it is configured so that, even when each of the heat dissipating members 3 and 4 is not used as an electrode, in order to improve heat dissipating property or suppress variation in mounting position of the semiconductor chip, The configuration of this embodiment is suitable.
[0066]
Moreover, although the example which provides the spacer 13 in all the projection parts 7a formed in the 1st heat radiating member 3 (three places in this example) was shown, if it provides at least two places, the thickness direction of Si chip 1a, 1b The relative position between the first heat radiation member 3 and the Si chips 1a and 1b can be fixed. Further, although an example in which a solder foil is used as the joining member 2 has been shown, a solder paste or the like may be used. Further, the number of semiconductor chips 1a and 1b may be one.
[0067]
(Second Embodiment)
The IGBT chip 1a has a chip size of about 10 to 16 mm when the current capacity is 100 A or more. In this case, when Cu is used as each of the heat radiating members 3 and 4, the linear expansion coefficient of Cu is 5 to 6 times the linear expansion coefficient of Si constituting the IGBT chip 1 a, so that in the cooling cycle, the bonding member It is feared that the solder 2 is thermally fatigued, cracks are generated, the thermal resistance is increased, and the heat dissipation (heat dissipation) is deteriorated.
[0068]
Therefore, an embodiment for improving such problems is the second embodiment. FIG. 8 is a schematic cross-sectional view of the semiconductor device of the second embodiment. In the present embodiment, the materials used as the first and second heat radiation members 3 and 4 are different from those in the first embodiment. In the following, the differences from FIG. 2A will be mainly described, and the same portions will be denoted by the same reference numerals in FIG. 8 to simplify the description.
[0069]
As shown in FIG. 8, the first and second heat radiating members 3 and 4 are made of a metal having a linear expansion coefficient similar to that of the Si chips 1a and 1b. As an example, a member made of invar (hereinafter referred to as an invar member). A clad material (hereinafter referred to as CIC) having a configuration in which 28 is sandwiched between members made of Cu (hereinafter referred to as Cu member) 29 is used. The ratio of the thickness of the CIC invar member 28 to the Cu member 29 and the overall thickness are adjusted so as to be as close to the linear expansion coefficient of Si as possible. Other members, the shapes of the members, and the like are the same as those described in the first embodiment.
[0070]
According to the present embodiment, since the linear expansion coefficient of each of the heat dissipation members 3 and 4 approximates the linear expansion coefficient of the Si chips 1a and 1b, the Si chip can be obtained even when the size of the Si chips 1a and 1b is large. It is possible to suppress the generation of thermal stress due to the difference in linear expansion coefficient between 1a and 1b and the respective heat dissipating members 3 and 4, and to prevent the concentration of strain on the joining member 2. As a result, since it is possible to prevent a decrease in the bonding property between each of the heat dissipation members 3 and 4 and the Si chips 1a and 1b, a decrease in the heat dissipation property or when the respective heat dissipation members 3 and 4 are used as electrodes. Can also prevent a decrease in electrical conductivity.
[0071]
It should be noted that the same effect can be achieved even if Mo (molybdenum) is used instead of Invar. Further, in each of the heat radiating members 3 and 4, the material sandwiched between the Cu members 29 may not be unified with the invar member 28 or a member made of Mo (hereinafter referred to as Mo member) or may be different. In addition, it is not particularly limited to using a clad material as each of the heat dissipating members 3 and 4, and a member having a linear expansion coefficient approximate to Si, such as an alloy of Cu—Mo, may be used.
[0072]
By the way, the above-mentioned 2nd Embodiment has shown about the example which uses the metal whose linear expansion coefficient approximated to Si as each heat radiating member 3 and 4, The clad material, such as CIC, is used as the example. However, since Invar and Mo are inferior in thermal conductivity to Cu, there is a problem that heat dissipation is reduced due to the presence of the Invar member 28 and Mo member in the thickness direction of the Si chips 1a and 1b. Therefore, a modification for improving this problem is shown below.
[0073]
In this modification, a plurality of invar members 28 of the CIC are partially formed in an inner layer. FIG. 9 is a schematic view of a CIC in which a plurality of invar members 28 are partially formed in an inner layer. FIG. 9A is a cross-sectional view of the CIC cut in parallel to the layer in a portion including the invar members 28. (B) is sectional drawing which cut | disconnected CIC perpendicularly | vertically with respect to the layer in the part containing the invar member 28. FIG.
[0074]
As shown in FIG. 9, in this modification, a plurality of invar members 28 are partially arranged inside the Cu member 29. In this example, the invar members 28 are arranged at four locations inside the Cu member 29. I am letting. Thereby, since the part which consists only of Cu member 29 in the thickness direction of each heat radiating member 3 and 4 can be provided, the thermal conductivity in the thickness direction of each heat radiating member 3 and 4 is not sacrificed. Therefore, it is possible to provide a heat radiating member having a linear expansion coefficient approximate to that of Si while ensuring heat dissipation.
[0075]
In this modification, the invar members 28 are provided at four locations inside the Cu member 29. However, the invar members 28 may be formed in a fine mesh shape by providing a number of invar members each having a small size. Moreover, you may use Mo member instead of an invar member. Moreover, you may use an Invar member and Mo member together.
[0076]
(Other embodiments)
FIG. 10 is a schematic cross-sectional view of a semiconductor device according to another embodiment. In the first and second embodiments, the control electrode on the one surface 5a side of the IGBT chip 1a and the inner lead 10 are electrically connected by wire bonding. However, as shown in FIG. The bump-shaped bonding member 30 may be used.
[0077]
Thus, when the first and second heat radiating members 3 and 4 and the Si chips 1a and 1b are soldered, the inner lead 10 and the control electrode can be connected together. Can be shortened.
[Brief description of the drawings]
FIG. 1 is a schematic view of a semiconductor device according to a first embodiment as viewed from above.
FIG. 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment.
FIG. 3 is a diagram showing an equivalent circuit of an IGBT chip.
FIG. 4 is a schematic view of a method for forming each heat radiating member.
FIG. 5 is a diagram schematically showing a configuration viewed from a side surface in a manufacturing process of a semiconductor device.
FIG. 6 is a diagram schematically showing a caulking and fixing process.
FIG. 7 is a partial cross-sectional view showing an example of an IGBT chip.
FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.
FIG. 9 is a schematic cross-sectional view of a heat dissipation member used in a modification of the second embodiment.
FIG. 10 is a schematic cross-sectional view of a semiconductor device according to another embodiment.
FIG. 11 is a schematic cross-sectional view of a semiconductor device described in a conventional publication.
FIG. 12 is a schematic cross-sectional view of a semiconductor device described in another conventional publication.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1a, 1b ... Semiconductor chip, 2 ... Joining member, 3 ... 1st thermal radiation member,
4 ... 2nd heat radiating member, 6 ... Convex part, 7a, 7b ... Protrusion part, 8 ... Concave part,
9 ... Lead frame, 12a, 12b ... Hole, 13 ... Spacer.

Claims (9)

半導体チップ（１ａ、１ｂ）と、前記半導体チップ（１ａ、１ｂ）の両面を挟むように熱伝導性を有する接合部材（２）を介して接合された一対の放熱部材（３、４）と、前記半導体チップ（１ａ）における前記第１の放熱部材（３）と対向する面には制御電極が形成されており、前記制御電極と電気的に接続されるリードフレーム（９）とを備え、前記一対の放熱部材（３、４）は、第１の放熱部材（３）と、前記半導体チップ（１ａ、１ｂ）と対向する面に凹部（８）が形成された第２の放熱部材（４）とよりなり、この凹部（８）内に前記半導体チップ（１ａ、１ｂ）が嵌め合わされていることを特徴とする半導体装置。A pair of heat dissipating members (3, 4) joined via a joining member (2) having thermal conductivity so as to sandwich both surfaces of the semiconductor chip (1a, 1b) and the semiconductor chip (1a, 1b) ; A control electrode is formed on a surface of the semiconductor chip (1a) facing the first heat radiating member (3), and a lead frame (9) electrically connected to the control electrode is provided. The pair of heat dissipating members (3, 4) includes a first heat dissipating member (3) and a second heat dissipating member (4) in which a recess (8) is formed on a surface facing the semiconductor chip (1a, 1b). The semiconductor device is characterized in that the semiconductor chip (1a, 1b) is fitted in the recess (8). 前記第１の放熱部材（３）における前記半導体チップ（１ａ、１ｂ）と対向する部位に、前記半導体チップ（１ａ、１ｂ）側に突出した凸部（６）が形成されており、この凸部（６）が前記半導体チップ（１ａ、１ｂ）と前記接合部材（２）を介して接合されていることを特徴とする請求項１に記載の半導体装置。A convex portion (6) projecting toward the semiconductor chip (1a, 1b) is formed at a portion of the first heat radiating member (3) facing the semiconductor chip (1a, 1b). The semiconductor device according to claim 1, wherein (6) is bonded to the semiconductor chip (1a, 1b) via the bonding member (2). 前記一対の放熱部材（３、４）における前記半導体チップ（１ａ、１ｂ）との対向面の少なくとも一方には突起部（７ａ、７ｂ）が形成されており、前記リードフレーム（９）に形成された穴（１２ａ、１２ｂ）と前記突起部（７ａ、７ｂ）とを嵌め合わせることにより、前記一対の放熱部材（３、４）の少なくとも一方が前記リードフレーム（９）に固定されていることを特徴とする請求項１又は２に記載の半導体装置。Protrusions (7a, 7b) are formed on at least one of the surfaces of the pair of heat radiating members (3, 4) facing the semiconductor chip (1a, 1b), and are formed on the lead frame (9). By fitting the holes (12a, 12b) and the protrusions (7a, 7b), at least one of the pair of heat radiating members (3, 4) is fixed to the lead frame (9). The semiconductor device according to claim 1 , wherein the semiconductor device is characterized. 前記一対の放熱部材（３、４）における前記半導体チップ（１ａ、１ｂ）との対向面の少なくとも一方には突起部（７ａ、７ｂ）が形成されており、当該放熱部材（３、４）と前記リードフレーム（９）との間にスペーサ（１３）を介在させた状態で、前記リードフレーム（９）に形成された穴（１２ａ、１２ｂ）と前記突起部（７ａ、７ｂ）とが嵌め合わされて固定されており、前記スペーサ（１３）によって当該放熱部材（３、４）と前記半導体チップ（１ａ、１ｂ）との、前記半導体チップ（１ａ、１ｂ）の厚み方向における位置決めがなされていることを特徴とする請求項１又は２に記載の半導体装置。Protrusions (7a, 7b) are formed on at least one of the surfaces of the pair of heat radiating members (3, 4) facing the semiconductor chip (1a, 1b), and the heat radiating members (3, 4) With the spacer (13) interposed between the lead frame (9) and the lead frame (9), the holes (12a, 12b) and the protrusions (7a, 7b) are fitted together. The heat dissipation member (3, 4) and the semiconductor chip (1a, 1b) are positioned in the thickness direction of the semiconductor chip (1a, 1b) by the spacer (13). The semiconductor device according to claim 1 or 2 . 半導体チップ（１ａ、１ｂ）と、前記半導体チップ（１ａ、１ｂ）の両面を挟むように熱伝導性を有する接合部材（２）を介して接合された一対の放熱部材（３、４）とを備え、前記一対の放熱部材（３、４）は、前記半導体チップ（１ａ、１ｂ）と対向する部位に、前記半導体チップ（１ａ、１ｂ）側に突出した凸部（６）が形成された第１の放熱部材（３）と、第２の放熱部材（４）とよりなり、この凸部（６）が、前記接合部材（２）を介して前記半導体チップ（１ａ、１ｂ）に接合されており、前記半導体チップ（１ａ）における前記第１の放熱部材（３）と対向する面に形成された制御電極と電気的に接続されるリードフレーム（９）を備えており、前記一対の放熱部材（３、４）における前記半導体チップ（１ａ、１ｂ）との対向面の少なくとも一方には突起部（７ａ、７ｂ）が形成されており、前記リードフレーム（９）に形成された穴（１２ａ、１２ｂ）と、前記突起部（７ａ、７ｂ）とを嵌め合わせて固定することにより、前記一対の放熱部材（３、４）の少なくとも一方が前記リードフレーム（９）に固定されており、前記一対の放熱部材（３、４）と前記リードフレーム（９）との間に生じる隙間にスペーサ（１３）を介在させ、前記スペーサ（１３）によって前記一対の放熱部材（３、４）と前記半導体チップ（１ａ、１ｂ）との、前記半導体チップ（１ａ、１ｂ）の厚み方向における位置決めがなされていることを特徴とする半導体装置。A semiconductor chip (1a, 1b) and a pair of heat radiating members (3, 4) joined via a thermally conductive joining member (2) so as to sandwich both surfaces of the semiconductor chip (1a, 1b). And the pair of heat radiation members (3, 4) is provided with a convex portion (6) projecting toward the semiconductor chip (1a, 1b) at a portion facing the semiconductor chip (1a, 1b). 1 radiating member (3) and second radiating member (4), and this convex portion (6) is joined to the semiconductor chip (1a, 1b) via the joining member (2). And a lead frame (9) electrically connected to a control electrode formed on a surface of the semiconductor chip (1a) facing the first heat radiating member (3), and the pair of heat radiating members Pair with the semiconductor chip (1a, 1b) in (3, 4) Projections (7a, 7b) are formed on at least one of the surfaces, and the holes (12a, 12b) formed in the lead frame (9) and the projections (7a, 7b) are fitted together. By fixing, at least one of the pair of heat dissipation members (3, 4) is fixed to the lead frame (9), and the pair of heat dissipation members (3, 4) and the lead frame (9) A spacer (13) is interposed in a gap formed between the pair of heat radiation members (3, 4) and the semiconductor chip (1a, 1b) of the semiconductor chip (1a, 1b) by the spacer (13). A semiconductor device characterized by being positioned in a thickness direction. 前記一対の放熱部材（３、４）として、前記半導体チップ（１ａ、１ｂ）に線膨張率が近似した金属を用いることを特徴とする請求項１ないし５のいずれか１つに記載の半導体装置。6. The semiconductor device according to claim 1 , wherein a metal having a linear expansion coefficient approximate to that of the semiconductor chip (1a, 1b) is used as the pair of heat radiation members (3, 4). . 前記一対の放熱部材（３、４）として、銅の内部において、インバーおよびモリブデンのうちの少なくとも１つが、部分的に複数配置されているものを用いることを特徴とする請求項１ないし６のいずれか１つに記載の半導体装置。Wherein as a pair of heat radiation members (3, 4), one inside the copper, at least one of Invar and molybdenum, claims 1, characterized by using what is partially plurality placement 6 The semiconductor device as described in any one. 前記一対の放熱部材（３、４）の各々の面のうち、前記半導体チップ（１ａ、１ｂ）と対向する面とは反対側の面が露出した状態で、前記一対の放熱部材（３、４）および前記半導体チップ（１ａ、１ｂ）が樹脂封止されていることを特徴とする請求項１ないし７のいずれか１つに記載の半導体装置。Of the surfaces of the pair of heat radiating members (3, 4), the surface opposite to the surface facing the semiconductor chip (1a, 1b) is exposed, and the pair of heat radiating members (3,4) are exposed. 8) and the semiconductor chip (1a, 1b) are sealed with resin. 8. The semiconductor device according to claim 1, wherein the semiconductor chip is sealed with resin. 前記一対の放熱部材（３、４）が、前記半導体チップ（１ａ、１ｂ）の電極として用いられることを特徴とする請求項１ないし８のいずれか１つに記載の半導体装置。9. The semiconductor device according to claim 1, wherein the pair of heat radiation members (3, 4) are used as electrodes of the semiconductor chip (1a, 1b).
JP33312499A 1999-11-24 1999-11-24 Semiconductor device Expired - Lifetime JP3596388B2 (en)

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JP33312499A JP3596388B2 (en) 1999-11-24 1999-11-24 Semiconductor device
US09/717,227 US6703707B1 (en) 1999-11-24 2000-11-22 Semiconductor device having radiation structure
FR0015130A FR2801423B1 (en) 1999-11-24 2000-11-23 SEMICONDUCTOR DEVICE WITH RADIANT STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC INSTRUMENT
DE10066441A DE10066441B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066442A DE10066442B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10066443A DE10066443B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
DE10066446A DE10066446B4 (en) 1999-11-24 2000-11-24 Method for producing an electronic component with two emission components
DE10066445A DE10066445B4 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating structure
DE10058446A DE10058446B8 (en) 1999-11-24 2000-11-24 Semiconductor device with radiating components
US10/321,365 US6693350B2 (en) 1999-11-24 2002-12-18 Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure
US10/699,744 US20040089940A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,837 US6960825B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,746 US6998707B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,838 US6798062B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,785 US6891265B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,954 US6967404B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,828 US6992383B2 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure
US10/699,784 US20040089941A1 (en) 1999-11-24 2003-11-04 Semiconductor device having radiation structure

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