JP4449724B2 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JP4449724B2
JP4449724B2 JP2004355561A JP2004355561A JP4449724B2 JP 4449724 B2 JP4449724 B2 JP 4449724B2 JP 2004355561 A JP2004355561 A JP 2004355561A JP 2004355561 A JP2004355561 A JP 2004355561A JP 4449724 B2 JP4449724 B2 JP 4449724B2
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chip
signal line
metal plate
chips
semiconductor module
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JP2006165322A (en
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信之 加藤
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Denso Corp
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Denso Corp
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Description

本発明は、半導体モジュールに関するものである。   The present invention relates to a semiconductor module.

半導体モジュールとして、パワースイッチング素子を作り込んだチップと、外部接続端子とを一体化したものがある。この場合において、チップをリードフレームのチップ搭載部に搭載するとともに、チップのパッドとリードフレームのパッド部とをワイヤーにてボンディングして電気的に接続している（例えば、特許文献１等）。
特開平５−２９５３９号公報 As a semiconductor module, a chip in which a power switching element is built and an external connection terminal are integrated. In this case, the chip is mounted on the chip mounting portion of the lead frame, and the pad of the chip and the pad portion of the lead frame are bonded with a wire and electrically connected (for example, Patent Document 1).
JP-A-5-29539

ところが、チップのパッドとリードフレームのパッド部とをワイヤーにてボンディングして電気的に接続しているために接続信頼性という観点から、より信頼性の向上が望まれている。特に、パッドの数が多い場合にはワイヤーボンディングが複雑になる問題がある。   However, since the pads of the chip and the pad portions of the lead frame are bonded and electrically connected by a wire, further improvement in reliability is desired from the viewpoint of connection reliability. In particular, when the number of pads is large, there is a problem that wire bonding becomes complicated.

本発明は、上記問題点に着目してなされたものであり、その目的は、外部接続端子の接続信頼性が高い半導体モジュールを提供することにある。   The present invention has been made paying attention to the above problems, and an object thereof is to provide a semiconductor module having high connection reliability of external connection terminals.

請求項１の記載の発明は、パワースイッチング素子が作り込まれており、少なくとも一方の面が放熱面となるとともに、片方の面において複数の信号線用パッドを有するチップ
と、前記チップの放熱面に固着されたヒートシンクと、前記チップの各信号線用パッドに対応する外部接続端子を構成し、当該信号線用パッドに直接接合された金属板と、前記各信号線用パッドに直接接合された各金属板をその裏面から一括して前記各信号線用パッドとの間に挟む態様で配されて、それら金属板が共通に固着された絶縁性ベース部材と、を備えたことを特徴とする半導体モジュールをその要旨としている。 According to the first aspect of the present invention, a power switching element is formed, at least one surface is a heat dissipation surface, and a chip having a plurality of signal line pads on one surface, and the heat dissipation surface of the chip A heat sink fixed to the chip, external connection terminals corresponding to the signal line pads of the chip, a metal plate directly bonded to the signal line pads, and a direct bond to the signal line pads And an insulating base member that is arranged in such a manner that the respective metal plates are collectively sandwiched between the respective signal line pads from the back surface thereof, and the metal plates are fixed to each other in common. The gist is semiconductor modules.

よって、ワイヤーボンディングによらずに信号線用パッドと直接接合により外部接続端子の引き出しが行われ、接続信頼性が高い。また、チップの放熱面からヒートシンクを通して放熱が行われる。そして、前記チップの各信号線用パッドに対応する外部接続端子を構成する各金属板は、各金属板に共通の絶縁性ベース部材に固着されているため、各金属板の位置決めが容易になる。 Therefore, the external connection terminal is pulled out by direct bonding to the signal line pad without using wire bonding, and the connection reliability is high. Also, heat is radiated from the heat radiating surface of the chip through the heat sink. And since each metal plate which comprises the external connection terminal corresponding to each signal line pad of the said chip is being fixed to the insulating base member common to each metal plate, positioning of each metal plate becomes easy. .

請求項２に記載のように、請求項１に記載の半導体モジュールにおいて、前記絶縁性ベース部材の材料は、セラミックまたは樹脂であるとよい。
請求項３に記載の発明は、パワースイッチング素子が作り込まれており、一方の面が第１の放熱面となるとともに、他方の面の一部領域が第２の放熱面となり、かつ、当該他方の面での他の領域において複数の信号線用パッドを有するチップと、前記チップの第１の放熱面に固着された第１のヒートシンクと、前記チップの第２の放熱面側に配置され、貫通孔を有する絶縁性基板と、前記絶縁性基板に固着され、前記チップの各信号線用パッドに対応する外部接続端子を構成し、当該信号線用パッドに直接接合された金属板と、前記絶縁性基板の貫通孔内に配置され、前記チップの第２の放熱面に固着された第２のヒートシンクと、を備えたことを特徴とする半導体モジュールをその要旨としている。 As described in claim 2 , in the semiconductor module according to claim 1 , the material of the insulating base member may be ceramic or resin.
In the invention according to claim 3 , the power switching element is built in, and one surface serves as the first heat radiating surface, and part of the other surface serves as the second heat radiating surface, and A chip having a plurality of signal line pads in another region on the other surface; a first heat sink fixed to the first heat dissipation surface of the chip; and a second heat dissipation surface side of the chip. An insulating substrate having a through-hole, a metal plate fixed to the insulating substrate, constituting an external connection terminal corresponding to each signal line pad of the chip, and a metal plate directly bonded to the signal line pad; The gist of the semiconductor module is provided with a second heat sink disposed in the through hole of the insulating substrate and fixed to the second heat radiation surface of the chip.

よって、ワイヤーボンディングによらずに信号線用パッドと直接接合により外部接続端子の引き出しが行われ、接続信頼性が高い。また、チップの両面での第１および第２の放熱面から第１および第２のヒートシンクを通して放熱が行われる。このとき、第２のヒートシンクが絶縁性基板の貫通孔内においてチップの第２の放熱面に固着されており、絶縁性基板の貫通孔にて第２のヒートシンクとの接触が回避される。   Therefore, the external connection terminal is pulled out by direct bonding to the signal line pad without using wire bonding, and the connection reliability is high. Further, heat is radiated from the first and second heat radiating surfaces on both sides of the chip through the first and second heat sinks. At this time, the second heat sink is fixed to the second heat radiating surface of the chip in the through hole of the insulating substrate, and contact with the second heat sink is avoided in the through hole of the insulating substrate.

請求項４に記載のように、請求項３に記載の半導体モジュールにおいて前記絶縁性基板の材料は、セラミックまたは樹脂であるとよい。
請求項５に記載の発明は、請求項３または４に記載の半導体モジュールにおいて、チップを複数具備し、各チップを当該各チップに共通の第１のヒートシンクに固着するとともに、前記金属板を各チップに共通の絶縁性基板に固着し、当該金属板により各チップに共通の外部接続端子を構成するとともに各チップの同じ機能の信号線用パッドをつなぐ配線を構成したことを特徴としている。よって、配線の簡素化を図ることができる。 As described in claim 4 , in the semiconductor module according to claim 3 , the material of the insulating substrate may be ceramic or resin.
According to a fifth aspect of the present invention, in the semiconductor module according to the third or fourth aspect , the semiconductor module includes a plurality of chips, each chip is fixed to a first heat sink common to each chip, and each of the metal plates is attached to each chip. The chip is fixed to an insulating substrate common to the chip, and the metal plate constitutes a common external connection terminal for each chip, and wiring for connecting signal line pads of the same function of each chip. Therefore, wiring can be simplified.

請求項６に記載のように、請求項６に記載の半導体モジュールにおいて、前記金属板は、配線としての長さが各チップで等しいと、チップ毎の配線抵抗を等しくすることができる。 According to a sixth aspect of the present invention, in the semiconductor module according to the sixth aspect of the present invention, when the metal plate has the same length as the wiring in each chip, the wiring resistance for each chip can be made equal.

請求項７に記載の発明は、請求項６に記載の半導体モジュールにおいて、前記複数のチップは一対のチップよりなり、この一対のチップでの信号線用パッドを配した辺同士が対向するように一対のチップを第１のヒートシンク上に配置するとともに、一対のチップにおける信号線用パッドの列の並びとして同じ機能を有する信号線用パッド同士を対向させたことを特徴としている。よって、チップ毎の配線の長さを短くすることができ、これにより配線抵抗を小さくすることができる。 According to a seventh aspect of the present invention, in the semiconductor module according to the sixth aspect , the plurality of chips are composed of a pair of chips, and the sides of the pair of chips on which the signal line pads are arranged face each other. A pair of chips are arranged on a first heat sink, and signal line pads having the same function as an array of signal line pad rows in the pair of chips are opposed to each other. Therefore, the length of the wiring for each chip can be shortened, and thereby the wiring resistance can be reduced.

（比較例）
以下、本発明を具体化した実施の形態の説明に先立ち、その比較例を図面に従って説明する。
図１には本実施形態における半導体モジュール１の平面図を示す。図２には本比較例における半導体モジュール１の縦断面図を示す。図１，２に示すように、本比較例における半導体モジュール１は、チップ１０を具備しており、当該チップ１０には縦型パワースイッチング素子が作り込まれている。このチップ１０はモールド樹脂２にて封止されている。図１でのモールド樹脂２の無い状態を図３に示す。即ち、図３にはモールド樹脂２の無い状態での半導体モジュール１の平面図を示す。また、図２でのモールド樹脂２の無い状態を図４に示す。即ち、図４にはモールド樹脂２の無い状態での半導体モジュール１の縦断面図を示す。また、図５にはモールド樹脂２の無い状態での半導体モジュール１の分解斜視図を示す。図７には、本実施形態における半導体モジュール１を用いた負荷駆動回路の電気的構成を示す。 ( Comparative example )
Hereinafter, prior to the description of the implementation of embodying the present invention will be described with reference to the drawings the comparative example.
FIG. 1 shows a plan view of a semiconductor module 1 in the present embodiment. FIG. 2 is a longitudinal sectional view of the semiconductor module 1 in this comparative example . As shown in FIGS. 1 and 2, the semiconductor module 1 in this comparative example includes a chip 10, and a vertical power switching element is built in the chip 10. This chip 10 is sealed with a mold resin 2. The state without the mold resin 2 in FIG. 1 is shown in FIG. That is, FIG. 3 shows a plan view of the semiconductor module 1 without the mold resin 2. Moreover, the state without the mold resin 2 in FIG. 2 is shown in FIG. That is, FIG. 4 shows a vertical cross-sectional view of the semiconductor module 1 without the mold resin 2. FIG. 5 shows an exploded perspective view of the semiconductor module 1 without the mold resin 2. FIG. 7 shows an electrical configuration of a load driving circuit using the semiconductor module 1 in the present embodiment.

図３，４に示すように、チップ１０において四角板状のチップ本体１１には縦型パワースイッチング素子が作り込まれている。縦型パワースイッチング素子として、具体的には、ＩＧＢＴやＭＯＳＦＥＴやサイリスタを挙げることができる。以下の説明においてはＭＯＳＦＥＴを用いた場合について説明することとし、ゲート端子（ゲート電極）とソース端子（ソース電極）とドレイン端子（ドレイン電極）を有する。なお、ＩＧＢＴを用いた場合には、ゲート端子（ゲート電極）とエミッタ端子（エミッタ電極）とコレクタ端子（コレクタ電極）を有し、また、サイリスタを用いた場合には、ゲート端子（ゲート電極）とカソード端子（カソード電極）とアノード端子（アノード電極）を有することになる。   As shown in FIGS. 3 and 4, a vertical power switching element is formed in a chip body 11 having a square plate shape in the chip 10. Specific examples of the vertical power switching element include an IGBT, a MOSFET, and a thyristor. In the following description, a case where a MOSFET is used will be described, which includes a gate terminal (gate electrode), a source terminal (source electrode), and a drain terminal (drain electrode). When an IGBT is used, it has a gate terminal (gate electrode), an emitter terminal (emitter electrode), and a collector terminal (collector electrode). When a thyristor is used, a gate terminal (gate electrode). And a cathode terminal (cathode electrode) and an anode terminal (anode electrode).

また、チップ１０においてはトランジスタセル群のうちの一つのトランジスタセルを過電流検出用トランジスタ（カレントミラートランジスタ）として用いており、高機能化している。詳しい説明を、図７を用いて行う。   Further, in the chip 10, one transistor cell in the transistor cell group is used as an overcurrent detection transistor (current mirror transistor), so that the function is enhanced. Detailed description will be given with reference to FIG.

図７に示すように、チップ１０において、主パワートランジスタＱ１と過電流検出用トランジスタ（カレントミラートランジスタ）Ｑ２とが作り込まれている。主パワートランジスタＱ１はドレイン端子Ｄとソース端子Ｓとの間において負荷３０と電源３１とが直列に接続される。ソース端子Ｓから分岐したソース端子Ｓ１がドライブ回路３２と接続され、ドライブ回路３２により主パワートランジスタＱ１のゲート端子Ｇ１および過電流検出用トランジスタＱ２のゲート端子Ｇ２を通してトランジスタＱ１，Ｑ２のゲート・ソース間電圧が調整され、両トランジスタＱ１，Ｑ２が同期してオン／オフ制御される。前述のソース端子Ｓおよび過電流検出用トランジスタＱ２のソース端子Ｓ２には過電流検出回路３３が接続される。過電流検出回路３３は電流検出抵抗３４と比較回路３５と基準電源３６からなり、過電流検出用トランジスタ（カレントミラートランジスタ）Ｑ２の通電電流が電流検出抵抗３４にて電圧に変換され、その電圧値が比較回路３５において基準電源３６による基準値と比較され、基準値よりも大きいと制御回路３７に過電流検出信号を送出する。制御回路３７は過電流検出信号を入力すると、負荷３０の通電電流を下げるような指令をドライブ回路３２に送出する。   As shown in FIG. 7, in the chip 10, a main power transistor Q1 and an overcurrent detection transistor (current mirror transistor) Q2 are formed. In the main power transistor Q1, a load 30 and a power source 31 are connected in series between a drain terminal D and a source terminal S. The source terminal S1 branched from the source terminal S is connected to the drive circuit 32. The drive circuit 32 causes the gate terminal G1 of the main power transistor Q1 and the gate terminal G2 of the overcurrent detection transistor Q2 to be connected between the gate and source of the transistors Q1 and Q2. The voltage is adjusted, and both transistors Q1 and Q2 are controlled on / off in synchronization. An overcurrent detection circuit 33 is connected to the source terminal S and the source terminal S2 of the overcurrent detection transistor Q2. The overcurrent detection circuit 33 includes a current detection resistor 34, a comparison circuit 35, and a reference power source 36. The current flowing through the overcurrent detection transistor (current mirror transistor) Q2 is converted into a voltage by the current detection resistor 34, and the voltage value thereof. Is compared with a reference value by the reference power supply 36 in the comparison circuit 35, and if it is larger than the reference value, an overcurrent detection signal is sent to the control circuit 37. When the overcurrent detection signal is input, the control circuit 37 sends a command to the drive circuit 32 to lower the energization current of the load 30.

このように、チップ１０には信号線として、主パワートランジスタＱ１のゲート信号線（ゲート端子Ｇ１）と、過電流検出用トランジスタＱ２のゲート信号線（ゲート端子Ｇ２）と、過電流検出用トランジスタＱ２による過電流検出信号線（ソース端子Ｓ２）と、ドライブ回路３２へのソース信号線（電位引き出し用ソース端子Ｓ１）を有している。   As described above, the chip 10 has signal lines including the gate signal line (gate terminal G1) of the main power transistor Q1, the gate signal line (gate terminal G2) of the overcurrent detection transistor Q2, and the overcurrent detection transistor Q2. And an overcurrent detection signal line (source terminal S2) and a source signal line (potential extraction source terminal S1) to the drive circuit 32.

図３，４において、チップ本体１１の下面全面にはドレイン電極１２が形成され、ドレイン電極１２（チップ下面）が放熱面となっている。一方、チップ本体１１の上面において右寄りの部位には平面形状が四角形のソース電極１３が形成されている。また、チップ本体１１の上面において左側の部位には信号線用パッド１４が４つ形成されている。４つの信号線用パッド１４は図７でのＧ１，Ｇ２，Ｓ１，Ｓ２端子用のパッドである。   3 and 4, a drain electrode 12 is formed on the entire lower surface of the chip body 11, and the drain electrode 12 (chip lower surface) serves as a heat dissipation surface. On the other hand, a square-shaped source electrode 13 is formed on the right side of the upper surface of the chip body 11. Further, four signal line pads 14 are formed on the left side of the upper surface of the chip body 11. The four signal line pads 14 are pads for the G1, G2, S1, and S2 terminals in FIG.

このようにして、チップ１０は、パワースイッチング素子としての主パワートランジスタＱ１および高機能化用素子としての過電流検出用トランジスタＱ２が作り込まれており、一方の面（下面）が放熱面となるとともに、片方の面（上面）において複数の信号線用パッド１４を有している。   In this way, the chip 10 has the main power transistor Q1 as a power switching element and the overcurrent detection transistor Q2 as a high-performance element, and one surface (lower surface) serves as a heat dissipation surface. In addition, a plurality of signal line pads 14 are provided on one surface (upper surface).

チップ１０は四角板状のヒートシンク２０の上に配置され、半田２１によりヒートシンク２０の上面とチップ１０のドレイン電極１２（放熱面）とが接合（固着）されている。ヒートシンク２０は、放熱板として機能するとともにドレイン取出導体として機能する。また、ソース取出金属板２２が備えられている。ソース取出金属板２２は、四角板部２２ａと帯板部２２ｂからなり、四角板部２２ａの一辺から帯板部２２ｂが直線的に延設された構造をなしている。そして、ソース取出金属板２２の四角板部２２ａがチップ１０のソース電極１３の上に配置され、半田２３により接合されている。   The chip 10 is disposed on a square plate heat sink 20, and the upper surface of the heat sink 20 and the drain electrode 12 (heat radiating surface) of the chip 10 are joined (fixed) by solder 21. The heat sink 20 functions as a heat sink and also functions as a drain extraction conductor. A source extraction metal plate 22 is also provided. The source extraction metal plate 22 includes a square plate portion 22a and a strip plate portion 22b, and has a structure in which the strip plate portion 22b is linearly extended from one side of the square plate portion 22a. The square plate portion 22 a of the source extraction metal plate 22 is disposed on the source electrode 13 of the chip 10 and is joined by the solder 23.

図５に示すように、チップ１０の各信号線用パッド１４に対応するように帯板状の金属板２４が用意されている。この帯板状の各金属板２４は各信号線用パッド１４に対応する信号線取り出し用の外部接続端子となる（外部接続端子を構成している）。チップ１０の各信号線用パッド１４の上には信号線取出金属板２４の一端部がそれぞれ配置され、図４に示すように、半田２５により接合されている（直接接合されている）。信号線取出金属板２４としては、例えば、厚さが１ｍｍ程度の銅板を用いることができる。   As shown in FIG. 5, a strip-shaped metal plate 24 is prepared so as to correspond to each signal line pad 14 of the chip 10. Each strip-shaped metal plate 24 serves as an external connection terminal for taking out a signal line corresponding to each signal line pad 14 (constitutes an external connection terminal). One end of a signal line extraction metal plate 24 is disposed on each signal line pad 14 of the chip 10 and is joined (directly joined) by solder 25 as shown in FIG. As the signal line extraction metal plate 24, for example, a copper plate having a thickness of about 1 mm can be used.

さらには、この構造体が図１，２に示すように樹脂２にてモールドされている。詳しくは、ヒートシンク２０の下面と、ソース取出金属板２２の帯板部２２ｂの先端部と、信号線取出金属板２４の一端部が露出する状態で、チップ１０とヒートシンク２０とソース取出金属板２２と信号線取出金属板２４を封止している。   Further, this structure is molded with resin 2 as shown in FIGS. Specifically, the chip 10, the heat sink 20, and the source extraction metal plate 22 are exposed in a state where the lower surface of the heat sink 20, the tip of the strip plate portion 22 b of the source extraction metal plate 22, and one end of the signal line extraction metal plate 24 are exposed. The signal line extraction metal plate 24 is sealed.

このモジュール１が図２に示すように取付部材２６に装着される。この状態においては、ヒートシンク２０の下面が取付部材２６と接触している。そして、縦型パワースイッチング素子を作り込んだチップ１０において駆動により熱が発生し、その熱はヒートシンク２０を通して取付部材２６側に逃がされる。即ち、チップ１０は下面が放熱面となっており、チップ１０の放熱面からヒートシンク２０を通して放熱される。   The module 1 is mounted on the mounting member 26 as shown in FIG. In this state, the lower surface of the heat sink 20 is in contact with the mounting member 26. Then, heat is generated by driving in the chip 10 in which the vertical power switching element is formed, and the heat is released to the mounting member 26 side through the heat sink 20. That is, the lower surface of the chip 10 is a heat radiating surface, and heat is radiated from the heat radiating surface of the chip 10 through the heat sink 20.

製造の際には次のようにする。
図６に示すように、ヒートシンク２０の上にチップ１０を半田２１により接合する（半田付けする）。そして、チップ１０のソース電極１３の上にペースト状の半田（半田ペースト）２３を塗布するとともに信号線用パッド１４の上にペースト状の半田（半田ペースト）２５を塗布する。その後、チップ１０のソース電極１３の上にペースト状の半田（半田ペースト）２３を介してソース取出金属板２２の四角板部２２ａを搭載するとともに信号線用パッド１４の上にペースト状の半田（半田ペースト）２５を介して信号線取出金属板２４の一端部を搭載し、この状態で加熱して半田２３，２５を溶融し接合する。なお、半田ペーストの代わりに半田板を用いて半田付けしてもよい。 At the time of manufacture, it is as follows.
As shown in FIG. 6, the chip 10 is joined (soldered) on the heat sink 20 with solder 21. Then, paste solder (solder paste) 23 is applied on the source electrode 13 of the chip 10 and paste solder (solder paste) 25 is applied on the signal line pad 14. Thereafter, the square plate portion 22a of the source extraction metal plate 22 is mounted on the source electrode 13 of the chip 10 via the paste-like solder (solder paste) 23 and the paste-like solder (on the signal line pad 14). One end of the signal line extraction metal plate 24 is mounted via the solder paste) 25 and heated in this state to melt and bond the solders 23 and 25. In addition, you may solder using a solder plate instead of a solder paste.

その後、樹脂２にてモールドする。これによって、図１，２に示すモジュール１が完成する。
このように、本比較例においては、金属板２４は、チップ１０の各信号線用パッド１４に対応する外部接続端子を構成しており、信号線用パッド１４に直接接合されているので、ワイヤーボンディングによらずに信号線用パッド１４と直接接合により外部接続端子の引き出しが行われ、接続信頼性が高い。特に、ワイヤーボンディングでは高温にしたときに信頼性低下を招きやすいが、本比較例ではそれが防止できる。また、大電流化に対応すべくソース電極１３についてもソース取出金属板２２と直接接合しており（ワイヤーボンディングではなく半田付けにて電気的に接続しているため）、信号線に加えてソース電極１３も半田付けにすることでプロセスの簡素化を図ることができる。 Thereafter, the resin 2 is molded. As a result, the module 1 shown in FIGS. 1 and 2 is completed.
Thus, in this comparative example , the metal plate 24 constitutes an external connection terminal corresponding to each signal line pad 14 of the chip 10 and is directly joined to the signal line pad 14. The external connection terminals are pulled out by direct bonding to the signal line pads 14 without using bonding, and the connection reliability is high. In particular, wire bonding tends to cause a decrease in reliability when the temperature is raised, but this comparative example can prevent this. Further, the source electrode 13 is also directly joined to the source extraction metal plate 22 in order to cope with an increase in current (because it is electrically connected by soldering instead of wire bonding), and in addition to the signal line, the source The process can be simplified by soldering the electrode 13 as well.

なお、チップ１０は下面が放熱面となっているが、放熱面は少なくとも一方の面、即ち、下面のみ、上面のみ、上下面とも放熱面となっている場合に適用してもよい。
（第１の実施の形態）
次に、本発明を具体化した第１の実施の形態を、比較例との相違点を中心に説明する。 Note that the lower surface of the chip 10 is a heat dissipation surface, but the heat dissipation surface may be applied to at least one surface, that is, only the lower surface, only the upper surface, and both the upper and lower surfaces.
(First Embodiment)
Next, a first embodiment embodying the present invention will be described focusing on differences from the comparative example .

図８は本実施の形態における半導体モジュールの平面図である。図９は半導体モジュールの縦断面図である。図８，９においてモールド樹脂２を一点鎖線で示す。
本実施形態においては、絶縁性ベース部材としての絶縁性板材４０を具備している。この絶縁性板材４０は長方形状をなしており、材料としてはセラミックや樹脂を挙げることができる。 FIG. 8 is a plan view of the semiconductor module in the present embodiment. FIG. 9 is a longitudinal sectional view of the semiconductor module. 8 and 9, the mold resin 2 is indicated by a one-dot chain line.
In the present embodiment, an insulating plate 40 as an insulating base member is provided. The insulating plate 40 has a rectangular shape, and examples of the material include ceramic and resin.

図１０に示すように、絶縁性板材４０の下面に各信号線取出金属板２４が固着されており、この状態で各信号線取出金属板２４が信号線用パッド１４の上面に半田付けされている。詳しくは次のように製造する。   As shown in FIG. 10, each signal line extraction metal plate 24 is fixed to the lower surface of the insulating plate member 40. In this state, each signal line extraction metal plate 24 is soldered to the upper surface of the signal line pad 14. Yes. Specifically, it is manufactured as follows.

図１１に示すように、予め、絶縁性板材４０の下面に各信号線取出金属板２４を位置合わせした状態で固着しておく。一方、ヒートシンク２０の上にチップ１０を半田付けするとともに、チップ１０のソース電極１３の上にペースト状の半田（半田ペースト）２３を塗布する。同様に、信号線用パッド１４の上にペースト状の半田（半田ペースト）２５を塗布する。そして、チップ１０のソース電極１３の上にペースト状の半田（半田ペースト）２３を介してソース取出金属板２２の四角板部２２ａを搭載する。また、信号線用パッド１４の上にペースト状の半田（半田ペースト）２５を介して、絶縁性板材４０に固着された信号線取出金属板２４の一端部を搭載する。この状態で加熱して半田２３，２５を溶融し接合する。なお、半田ペーストの代わりに半田板を用いて半田付けしてもよい。   As shown in FIG. 11, each signal line extraction metal plate 24 is fixed to the lower surface of the insulating plate member 40 in advance in an aligned state. On the other hand, the chip 10 is soldered on the heat sink 20, and paste solder (solder paste) 23 is applied on the source electrode 13 of the chip 10. Similarly, paste solder (solder paste) 25 is applied on the signal line pad 14. Then, the square plate portion 22 a of the source extraction metal plate 22 is mounted on the source electrode 13 of the chip 10 via paste-like solder (solder paste) 23. Further, one end of the signal line extraction metal plate 24 fixed to the insulating plate member 40 is mounted on the signal line pad 14 via a paste-like solder (solder paste) 25. In this state, heating is performed to melt and bond the solders 23 and 25. In addition, you may solder using a solder plate instead of a solder paste.

その後、樹脂２にてモールドする。これによって、図８，９に示すモジュールが完成する。
このように、本実施形態においては、チップ１０の各信号線用パッド１４に対応する外部接続端子を構成する各金属板２４は、各金属板２４に共通の絶縁性板材４０に固着され
ているので、各金属板２４の位置決めが容易になる。詳しくは、導体としての信号線取出金属板２４が絶縁性ベース部材としての絶縁性板材４０に固着されており、これにより信号線取出金属板２４を信号線用パッド１４に半田付けする際において１本ずつの位置精度が不要となる。
（第２の実施の形態）
次に、第２の実施の形態を、第１の実施の形態との相違点を中心に説明する。 Thereafter, the resin 2 is molded. As a result, the modules shown in FIGS. 8 and 9 are completed.
As described above, in the present embodiment, each metal plate 24 constituting the external connection terminal corresponding to each signal line pad 14 of the chip 10 is fixed to the insulating plate 40 common to each metal plate 24. Therefore, positioning of each metal plate 24 becomes easy. More specifically, the signal line extraction metal plate 24 as a conductor is fixed to an insulating plate member 40 as an insulating base member, so that when the signal line extraction metal plate 24 is soldered to the signal line pad 14, 1 is used. Position accuracy for each book becomes unnecessary.
(Second Embodiment)
Next, the second embodiment will be described focusing on the differences from the first embodiment.

図１２は本実施の形態における半導体モジュールの平面図である。図１３は半導体モジュールの縦断面図である。図１２，１３においてモールド樹脂２を一点鎖線で示す。図１４にはモジュールの分解斜視図を示す。   FIG. 12 is a plan view of the semiconductor module in the present embodiment. FIG. 13 is a longitudinal sectional view of the semiconductor module. 12 and 13, the mold resin 2 is indicated by a one-dot chain line. FIG. 14 shows an exploded perspective view of the module.

本実施形態においてもチップ１０には、パワースイッチング素子としての主パワートランジスタＱ１および高機能化用素子としての過電流検出用トランジスタＱ２が作り込まれている。また、同チップ１０は、下面（一方の面）が第１の放熱面となるとともに、上面（他方の面）の一部領域であるソース電極１３が第２の放熱面となり、かつ、当該上面での他の領域において複数の信号線用パッド１４を有している。   Also in the present embodiment, the chip 10 is provided with a main power transistor Q1 as a power switching element and an overcurrent detection transistor Q2 as a function enhancement element. The chip 10 has a lower surface (one surface) serving as a first heat dissipation surface, a source electrode 13 that is a partial region of the upper surface (other surface) serving as a second heat dissipation surface, and the upper surface. In other areas, a plurality of signal line pads 14 are provided.

また、本実施形態においては、絶縁性基板（板材）４５と、ソース取出導体を兼ねるヒートシンク５０，５１を具備している。チップ１０のソース電極１３の上には、四角板状のヒートシンク５０が半田２３により接合されている。前述したように、ヒートシンク（第１のヒートシンク）２０は、チップ１０の下面（第１の放熱面）に固着され、放熱板として機能するとともにドレイン取出導体として機能する。   In the present embodiment, an insulating substrate (plate material) 45 and heat sinks 50 and 51 that also serve as source extraction conductors are provided. On the source electrode 13 of the chip 10, a square plate-like heat sink 50 is joined by solder 23. As described above, the heat sink (first heat sink) 20 is fixed to the lower surface (first heat radiating surface) of the chip 10 and functions as a heat radiating plate and also as a drain extraction conductor.

一方、図１４に示すように、絶縁性基板４５はチップ１０の上面側（第２の放熱面側）に配置される。絶縁性基板４５の材料としてセラミックや樹脂を挙げることができる。この絶縁性基板４５は中央部に貫通孔４５ａを有し、全体形状として四角枠状をなしている。貫通孔４５ａはヒートシンク５０よりも若干大きい。絶縁性基板４５の下面に各信号線取出金属板２４が固着されており、この状態で各信号線取出金属板２４がチップ１０の信号線用パッド１４の上面に半田２５により接合されている。つまり、チップ１０の各信号線用パッド１４に対応する外部接続端子を構成する金属板２４が信号線用パッド１４に直接接合されている。このとき、図１３に示すように、絶縁性基板４５の貫通孔４５ａ内に第２のヒートシンク５０が配置され、ヒートシンク５０はチップ１０のソース電極１３（第２の放熱面）に固着されており、貫通孔４５ａにより絶縁性基板４５とヒートシンク５０との接触が回避されている。   On the other hand, as shown in FIG. 14, the insulating substrate 45 is disposed on the upper surface side (second heat radiation surface side) of the chip 10. Examples of the material for the insulating substrate 45 include ceramics and resins. This insulating substrate 45 has a through-hole 45a at the center, and has a square frame shape as a whole. The through hole 45 a is slightly larger than the heat sink 50. Each signal line extraction metal plate 24 is fixed to the lower surface of the insulating substrate 45, and in this state, each signal line extraction metal plate 24 is joined to the upper surface of the signal line pad 14 of the chip 10 by solder 25. That is, the metal plate 24 constituting the external connection terminal corresponding to each signal line pad 14 of the chip 10 is directly bonded to the signal line pad 14. At this time, as shown in FIG. 13, the second heat sink 50 is disposed in the through hole 45 a of the insulating substrate 45, and the heat sink 50 is fixed to the source electrode 13 (second heat radiation surface) of the chip 10. The contact between the insulating substrate 45 and the heat sink 50 is avoided by the through hole 45a.

また、図１３に示すように、絶縁性基板４５の上面よりもヒートシンク５０の上面の方が高くなっており、このヒートシンク５０の上面には四角板状のヒートシンク５１が接合されている。また、図１３に示すように、ヒートシンク５１の上面が露出する状態でモールド樹脂２にて封止されている。   As shown in FIG. 13, the upper surface of the heat sink 50 is higher than the upper surface of the insulating substrate 45, and a square plate-shaped heat sink 51 is joined to the upper surface of the heat sink 50. Moreover, as shown in FIG. 13, it seals with the mold resin 2 in the state which the upper surface of the heat sink 51 is exposed.

このように本実施形態においては、ワイヤーボンディングによらずに信号線用パッド１４と直接接合により外部接続端子の引き出しが行われ、接続信頼性が高い。また、チップ１０の両面での第１および第２の放熱面から第１および第２のヒートシンク２０，５０を通して放熱が行われる。このとき、第２のヒートシンク５０が絶縁性基板４５の貫通孔４５ａ内においてチップ１０の第２の放熱面（ソース電極１３）に固着されており、絶縁性基板４５の貫通孔４５ａにて第２のヒートシンク５０との接触が回避される。
（第３の実施の形態）
次に、第３の実施の形態を、第２の実施の形態との相違点を中心に説明する。 As described above, in this embodiment, the external connection terminal is drawn out by direct bonding to the signal line pad 14 without using wire bonding, and the connection reliability is high. Further, heat is radiated from the first and second heat radiating surfaces on both surfaces of the chip 10 through the first and second heat sinks 20 and 50. At this time, the second heat sink 50 is fixed to the second heat radiating surface (source electrode 13) of the chip 10 in the through hole 45a of the insulating substrate 45, and the second heat sink 50 is fixed to the second through the through hole 45a of the insulating substrate 45. Contact with the heat sink 50 is avoided.
( Third embodiment)
Next, the third embodiment will be described with a focus on differences from the second embodiment.

図１５は本実施の形態における半導体モジュールの平面図である。図１６は半導体モジュールの縦断面図である。図１５，１６においてモールド樹脂２を一点鎖線で示す。図１７にはモジュールの分解斜視図を示す。   FIG. 15 is a plan view of the semiconductor module in the present embodiment. FIG. 16 is a longitudinal sectional view of the semiconductor module. 15 and 16, the mold resin 2 is indicated by a one-dot chain line. FIG. 17 shows an exploded perspective view of the module.

本実施形態の半導体モジュールはマルチチップモジュールであり、図７でのチップ１０を２つ具備し、この両チップ１０ａ，１０ｂを並列接続した状態で樹脂モールドしている。両チップ１０ａ，１０ｂを並列接続することにより大電流化を図っている。より詳しくは、１チップ当たりの面積を増やして電流を流しやすくする場合には歩留まりが悪くなる。そこで、１チップ当たりのセル数は同じにしてチップ数を増やすことにより電流を流しやすくし、かつ、複数のチップ１０ａ，１０ｂを並列接続している。   The semiconductor module of this embodiment is a multi-chip module, which includes two chips 10 in FIG. 7, and is resin-molded in a state where both the chips 10a and 10b are connected in parallel. Large current is achieved by connecting both the chips 10a and 10b in parallel. More specifically, the yield decreases when the area per chip is increased to facilitate the flow of current. Therefore, by increasing the number of chips with the same number of cells per chip, it is easy to flow current, and a plurality of chips 10a and 10b are connected in parallel.

以下、詳しく説明する。
２つのチップ１０ａ，１０ｂが各チップ１０ａ，１０ｂに共通のヒートシンク（ドレイン取出導体を兼ねる）２０の上面に搭載され、半田２１により接合（固着）されている。さらに、チップ１０ａ，１０ｂのソース電極１３の上には、それぞれ、四角板状のヒートシンク（ソース取出導体を兼ねる）５０が半田２３により接合されている。 This will be described in detail below.
Two chips 10a and 10b are mounted on the upper surface of a heat sink (also serving as a drain extraction conductor) 20 common to the chips 10a and 10b, and are joined (fixed) by solder 21. Further, on the source electrodes 13 of the chips 10a and 10b, square plate-shaped heat sinks (also serving as source extraction conductors) 50 are joined by solder 23, respectively.

一方、絶縁性基板４６は各チップ１０ａ，１０ｂに共通であり、平面形状として長方形をなしている。絶縁性基板４６の材料としてセラミックや樹脂を挙げることができる。絶縁性基板４６の左右には貫通孔４６ａ，４６ｂが形成されている。貫通孔４６ａ，４６ｂはヒートシンク（ソース取出金属板）５０よりも若干大きい。図１５，１６に示すように、絶縁性基板４６の下面に各信号線取出金属板６０が固着されており、図１８にはこの状態での絶縁性基板４６の下面および正面の構成を示す。   On the other hand, the insulating substrate 46 is common to the chips 10a and 10b, and has a rectangular shape as a planar shape. Examples of the material for the insulating substrate 46 include ceramics and resins. Through holes 46 a and 46 b are formed on the left and right sides of the insulating substrate 46. The through holes 46 a and 46 b are slightly larger than the heat sink (source extraction metal plate) 50. As shown in FIGS. 15 and 16, each signal line extraction metal plate 60 is fixed to the lower surface of the insulating substrate 46, and FIG. 18 shows the configuration of the lower surface and the front surface of the insulating substrate 46 in this state.

図１８において、絶縁性基板４６の一方の面には４つの金属板６０が固着されている。この金属板６０は、両チップ１０ａ，１０ｂに共通の外部接続端子に加えて両チップ１０ａ，１０ｂの同じ機能の信号線用パッド１４をつなぐ配線を兼ねている。詳しくは次のように構成されている。   In FIG. 18, four metal plates 60 are fixed to one surface of the insulating substrate 46. The metal plate 60 also serves as a wiring for connecting the signal line pads 14 of the same function of both the chips 10a and 10b in addition to the external connection terminals common to both the chips 10a and 10b. Specifically, the configuration is as follows.

４つの金属板６０は所定の形状をなしており（パターニングされており）、４つの信号線用パッド１４に対応している。詳しくは、４つの金属板６０は全体の形状として帯状に延びており、長方形状の外部接続端子部６１と、幅広部６２と、幅広部６３を有している。各金属板６０は、外部接続端子部６１と幅広部６２と幅広部６３をつなぐようにパターニングされている。幅広部６２は第２のチップ１０ｂにおける信号線用パッド１４の形成位置に配置されている。幅広部６３は第１のチップ１０ａにおける信号線用パッド１４の形成位置に配置されている。   The four metal plates 60 have a predetermined shape (patterned) and correspond to the four signal line pads 14. Specifically, the four metal plates 60 extend in a strip shape as a whole, and have a rectangular external connection terminal portion 61, a wide portion 62, and a wide portion 63. Each metal plate 60 is patterned so as to connect the external connection terminal portion 61, the wide portion 62, and the wide portion 63. The wide portion 62 is disposed at the position where the signal line pad 14 is formed in the second chip 10b. The wide portion 63 is disposed at the position where the signal line pad 14 is formed in the first chip 10a.

そして、各金属板６０の幅広部６２が第２のチップ１０ｂの信号線用パッド１４に、また、幅広部６３が第１のチップ１０ａの信号線用パッド１４に半田付けされている。このとき、図１６に示すように、絶縁性基板４６の貫通孔４６ａ，４６ｂ内にヒートシンク５０が配置され、貫通孔４６ａ，４６ｂにより絶縁性基板４６とヒートシンク５０が接触するのを回避している。   The wide portion 62 of each metal plate 60 is soldered to the signal line pad 14 of the second chip 10b, and the wide portion 63 is soldered to the signal line pad 14 of the first chip 10a. At this time, as shown in FIG. 16, the heat sink 50 is disposed in the through holes 46a and 46b of the insulating substrate 46, and the insulating substrate 46 and the heat sink 50 are prevented from coming into contact with each other through the through holes 46a and 46b. .

また、図１６に示すように、絶縁性基板４６の上面よりもヒートシンク５０の上面の方が高くなっており、このヒートシンク５０の上面には四角板状のヒートシンク５２が接合されている。また、図１６に示すように、ヒートシンク５２の上面が露出する状態でモールド樹脂２にて封止されている。   As shown in FIG. 16, the upper surface of the heat sink 50 is higher than the upper surface of the insulating substrate 46, and a square plate-like heat sink 52 is bonded to the upper surface of the heat sink 50. Further, as shown in FIG. 16, the heat sink 52 is sealed with the mold resin 2 with the upper surface exposed.

ヒートシンク５０，５１は、放熱板として機能するとともにソース取出導体として機能する。
このように本実施形態においては、金属板６０により、各チップ１０ａ，１０ｂに共通の外部接続端子を構成するとともに各チップ１０ａ，１０ｂの同じ機能の信号線用パッド１４をつなぐ配線を構成したので、配線の簡素化を図ることができる。詳しくは、大電流化を図るべく複数のチップ１０ａ，１０ｂを並列接続する際に、チップ共通の信号線用取出端子を用いることにより取出端子数が増加するのを防止できるとともに、絶縁性基板４６に配線および接続端子用の金属板６０を固着することにより配線の簡素化を図ることができる。 The heat sinks 50 and 51 function as heat sinks and function as source extraction conductors.
As described above, in the present embodiment, the metal plate 60 constitutes the external connection terminal common to the chips 10a and 10b and the wiring for connecting the signal line pads 14 having the same function of the chips 10a and 10b. The wiring can be simplified. Specifically, when a plurality of chips 10a and 10b are connected in parallel in order to increase the current, it is possible to prevent an increase in the number of extraction terminals by using the signal line extraction terminals common to the chips, and the insulating substrate 46. Simplification of the wiring can be achieved by fixing the metal plate 60 for the wiring and connection terminals.

より詳しく説明する。
モータ制御用等のインバータの高出力化に伴いパワーデバイスは大面積化をする必要があるが歩留まりが低下し、コストが高くなってしまう。その対策として複数のチップを並列に接続することにより対応することが考えられる。この場合、ゲート信号線などの信号線のワイヤーボンディングが複雑になる。また、次世代のデバイスであるＳｉＣデバイスを用いた場合、ＳｉＣデバイスは高温動作可能であるが、高温（２００℃以上）での信号線のワイヤーボンディング部において信頼性確保が難しい。 This will be described in more detail.
Along with the increase in the output of an inverter for motor control or the like, the power device needs to have a large area, but the yield decreases and the cost increases. As a countermeasure, it may be possible to cope by connecting a plurality of chips in parallel. In this case, wire bonding of signal lines such as gate signal lines becomes complicated. Further, when a SiC device, which is a next-generation device, is used, the SiC device can operate at a high temperature, but it is difficult to ensure reliability in the wire bonding portion of the signal line at a high temperature (200 ° C. or higher).

これに対し本実施形態においては、ワイヤーボンディングを廃止し、セラミック基板または樹脂基板（４６）に固着した金属板６０を、チップ１０ａ，１０ｂの信号線用パッド１４に直接半田付けしたので、ワイヤーボンディングが無いため信頼性が高い。また、セラミック基板または樹脂基板（４６）に回路配線用の金属板６０を設けることによりマルチチップ実装することができる。さらに、金属板６０が、外部接続線用端子に加えて各チップの信号線用パッドに延設された配線を兼ねるものであるので、配線の簡素化を図ることができる。
（第４の実施の形態）
次に、第４の実施の形態を、第３の実施の形態との相違点を中心に説明する。 On the other hand, in this embodiment, wire bonding is abolished, and the metal plate 60 fixed to the ceramic substrate or the resin substrate (46) is directly soldered to the signal line pads 14 of the chips 10a and 10b. Because there is no, it is highly reliable. Further, by providing a metal plate 60 for circuit wiring on a ceramic substrate or a resin substrate (46), multichip mounting can be performed. Furthermore, since the metal plate 60 also serves as a wiring extended to the signal line pad of each chip in addition to the external connection line terminal, the wiring can be simplified.
( Fourth embodiment)
Next, the fourth embodiment will be described focusing on the differences from the third embodiment.

図１９は、図１８に代わる本実施形態における絶縁性基板（板材）４６の下面図である。
絶縁性基板４６の一方の面には、外部接続端子および配線としての４つの金属板７０が固着され、４つの金属板７０は４つの信号線用パッド１４に対応している。図１９において金属板７０のパターンが、図１８の金属板６０のパターンとは異なっている。詳しくは、金属板７０のパターンに関して、チップ１０ｂの信号線用パッドに対応する幅広部７２とチップ１０ａの信号線用パッドに対応する幅広部７３との間においてその中間の位置から外部接続端子部７１に向かって延びている。 FIG. 19 is a bottom view of an insulating substrate (plate material) 46 in the present embodiment, which replaces FIG.
Four metal plates 70 as external connection terminals and wirings are fixed to one surface of the insulating substrate 46, and the four metal plates 70 correspond to the four signal line pads 14. In FIG. 19, the pattern of the metal plate 70 is different from the pattern of the metal plate 60 of FIG. Specifically, with respect to the pattern of the metal plate 70, the external connection terminal portion is located from an intermediate position between the wide portion 72 corresponding to the signal line pad of the chip 10 b and the wide portion 73 corresponding to the signal line pad of the chip 10 a. It extends toward 71.

よって、金属板７０に関して、両チップ１０ａ，１０ｂの配線抵抗、即ち、信号線用パッド１４と外部接続端子部７１との間の配線抵抗として、各チップ１０ａ，１０ｂで同じになる。これにより、各チップ１０ａ，１０ｂでゲート抵抗の不均一によるスイッチングの遅れを防止でき、電流の偏りなどをなくすことができる。   Therefore, regarding the metal plate 70, the wiring resistance of both the chips 10a and 10b, that is, the wiring resistance between the signal line pad 14 and the external connection terminal portion 71 is the same in each chip 10a and 10b. As a result, switching delays due to non-uniform gate resistance can be prevented in each of the chips 10a and 10b, and current bias and the like can be eliminated.

このように本実施形態においては、金属板７０は、配線としての長さが各チップ１０ａ，１０ｂで等しいので、チップ毎の配線抵抗を等しくすることができる。
（第５の実施の形態）
次に、第５の実施の形態を、第４の実施の形態との相違点を中心に説明する。 Thus, in this embodiment, since the metal plate 70 has the same length as the wiring in each of the chips 10a and 10b, the wiring resistance for each chip can be made equal.
( Fifth embodiment)
Next, the fifth embodiment will be described with a focus on differences from the fourth embodiment.

図２０は、図１９に代わる本実施形態における絶縁性基板４６の下面図である。図２１には両チップ１０ａ，１０ｂおよびヒートシンク２０の平面および側面構造を示す。
図２１において、両チップ１０ａ，１０ｂにおける共通の信号線用パッド１４ａ，１４ｂ，１４ｃ，１４ｄの配置として、次のようにしている。 FIG. 20 is a bottom view of an insulating substrate 46 in the present embodiment that replaces FIG. FIG. 21 shows the planar and side structures of both the chips 10a and 10b and the heat sink 20.
In FIG. 21, the arrangement of common signal line pads 14a, 14b, 14c and 14d in both chips 10a and 10b is as follows.

チップ１０ｂでの一つの辺Ｓｃ１において、４つの信号線用パッド１４ａ〜１４ｄが一列に設けられている。一方、チップ１０ａでの一つの辺Ｓｃ２において、４つの信号線用パッド１４ａ〜１４ｄが一列に設けられている。そして、ヒートシンク２０の上にチップ１０ａとチップ１０ｂが半田付けされるが、このとき、チップ１０ｂでの一つの辺（パッド１４ａ〜１４ｄを配した辺）Ｓｃ１と、チップ１０ａでの一つの辺（パッド１４ａ〜１４ｄを配した辺）Ｓｃ２とが対向するように配置されている。また、チップ１０ｂの一つの辺Ｓｃ１において、４つの信号線用パッド１４ａ〜１４ｄの配置順として左から右に信号線用パッド１４ａ→信号線用パッド１４ｂ→信号線用パッド１４ｃ→信号線用パッド１４ｄで並んでいる。同様に、チップ１０ａの一つの辺Ｓｃ２において、４つの信号線用パッド１４ａ〜１４ｄの配置順として左から右に信号線用パッド１４ａ→信号線用パッド１４ｂ→信号線用パッド１４ｃ→信号線用パッド１４ｄで並んでいる。   In one side Sc1 of the chip 10b, four signal line pads 14a to 14d are provided in a line. On the other hand, on one side Sc2 of the chip 10a, four signal line pads 14a to 14d are provided in a line. Then, the chip 10a and the chip 10b are soldered on the heat sink 20, and at this time, one side of the chip 10b (side where the pads 14a to 14d are arranged) Sc1 and one side of the chip 10a ( The side where the pads 14a to 14d are arranged is arranged so as to face the Sc2. Further, in one side Sc1 of the chip 10b, the signal line pad 14a → the signal line pad 14b → the signal line pad 14c → the signal line pad from left to right as the arrangement order of the four signal line pads 14a to 14d. It is lined up in 14d. Similarly, in one side Sc2 of the chip 10a, the signal line pad 14a → the signal line pad 14b → the signal line pad 14c → the signal line order from left to right as the arrangement order of the four signal line pads 14a to 14d. It is lined up with the pad 14d.

図２０に示すように、絶縁性基板４６の一方の面には、外部接続端子および配線としての４つの金属板８０が固着され、４つの金属板８０は４つの信号線用パッド１４ａ〜１４ｄに対応している。図２０における金属板８０のパターンについて説明する。絶縁性基板４６の一方の面での貫通孔４６ａと貫通孔４６ｂとの間の領域において貫通孔４６ｂに近い部位には左右に幅広部８２ａ，８２ｂ，８２ｃ，８２ｄが一列に並ぶようにパターニングされている。一方、絶縁性基板４６の一方の面での貫通孔４６ａと貫通孔４６ｂとの間の領域において貫通孔４６ａに近い部位には左右に幅広部８３ａ，８３ｂ，８３ｃ，８３ｄが一列に並ぶようにパターニングされている。また、幅広部８２ａと幅広部８３ａとが直線的につながるようにパターニングされている。同様に、幅広部８２ｂと幅広部８３ｂ、幅広部８２ｃと幅広部８３ｃ、幅広部８２ｄと幅広部８３ｄがそれぞれ直線的につながるようにパターニングされている。さらに、幅広部８２ａ，８３ａ間においてその中間の位置から外部接続端子部８１に向かって延びるようにパターニングされている。同様に、幅広部８２ｂ，８３ｂ間、幅広部８２ｃ，８３ｃ間、幅広部８２ｄ，８３ｄ間においてその中間の位置から外部接続端子部８１に向かって延びるようにパターニングされている。   As shown in FIG. 20, four metal plates 80 as external connection terminals and wiring are fixed to one surface of the insulating substrate 46, and the four metal plates 80 are attached to the four signal line pads 14a to 14d. It corresponds. The pattern of the metal plate 80 in FIG. 20 will be described. In a region between the through hole 46a and the through hole 46b on one surface of the insulating substrate 46, a portion close to the through hole 46b is patterned so that wide portions 82a, 82b, 82c, and 82d are arranged in a line on the left and right. ing. On the other hand, in the region between the through hole 46a and the through hole 46b on one surface of the insulating substrate 46, the wide portions 83a, 83b, 83c, and 83d are arranged in a line in the left and right in the portion close to the through hole 46a. Patterned. The wide portion 82a and the wide portion 83a are patterned so as to be connected linearly. Similarly, the wide portion 82b and the wide portion 83b, the wide portion 82c and the wide portion 83c, and the wide portion 82d and the wide portion 83d are linearly connected. Further, the wide portions 82 a and 83 a are patterned so as to extend from an intermediate position toward the external connection terminal portion 81. Similarly, patterning is performed so as to extend from the intermediate position toward the external connection terminal portion 81 between the wide portions 82b and 83b, between the wide portions 82c and 83c, and between the wide portions 82d and 83d.

このように本実施形態においては、複数のチップは一対のチップ１０ａ，１０ｂよりなり、この一対のチップ１０ａ，１０ｂでの信号線用パッドを配した辺Ｓｃ１，Ｓｃ２同士が対向するように一対のチップ１０ａ，１０ｂを第１のヒートシンク２０上に配置するとともに、一対のチップ１０ａ，１０ｂにおける信号線用パッドの列の並びとして同じ機能を有する信号線用パッド同士を対向させた。よって、チップ毎の配線長さを短くすることができ、これにより配線抵抗を小さくすることができる。つまり、チップ１０ａ，１０ｂの信号線用パッドの配置を対称に製作し、絶縁性基板４６上の配線を短くすることができる。これにより、絶縁性基板４６上の配線を簡略にすることで、絶縁性基板４６上の配線部付近で応力が発生し、破壊が生じることを防止できる。   As described above, in the present embodiment, the plurality of chips includes the pair of chips 10a and 10b, and the pair of chips Sc and Sc2 on which the signal line pads are disposed in the pair of chips 10a and 10b are opposed to each other. The chips 10a and 10b are disposed on the first heat sink 20, and the signal line pads having the same function as the row of signal line pads in the pair of chips 10a and 10b are opposed to each other. Therefore, the wiring length for each chip can be shortened, thereby reducing the wiring resistance. That is, the signal line pads of the chips 10a and 10b can be manufactured symmetrically, and the wiring on the insulating substrate 46 can be shortened. Thereby, by simplifying the wiring on the insulating substrate 46, it is possible to prevent stress from being generated in the vicinity of the wiring portion on the insulating substrate 46, and destruction.

これまでの説明においては高機能化のために１チップ内に過電流検出用トランジスタ（カレントミラー素子）を形成した場合について説明したが、他にも温度検出用素子を１チップ内に形成する等の形態にて実施してもよい。また、高機能化素子としての過電流検出素子や温度検出素子が無い場合に適用してよく、この場合には図７においてチップ１０には信号線として、主パワートランジスタＱ１のゲート信号線（ゲート端子Ｇ１）と、ドライブ回路３２へのソース信号線（電位引き出し用ソース端子Ｓ１）を有していることになる。   In the above description, the case where an overcurrent detection transistor (current mirror element) is formed in one chip for higher functionality has been described. However, other temperature detection elements are formed in one chip. You may implement in the form. Further, the present invention may be applied to the case where there is no overcurrent detecting element or temperature detecting element as a highly functional element. In this case, the gate signal line (gate gate) of the main power transistor Q1 is used as a signal line in the chip 10 in FIG. Terminal G1) and a source signal line (potential extraction source terminal S1) to the drive circuit 32 are provided.

また、Ｇ１，Ｇ２，Ｓ１，Ｓ２端子の４つの端子を信号線用端子として用いる場合について説明してきたが、Ｇ１端子とＧ２端子を共通化して３つの端子（Ｇ１，Ｇ２共通端子、Ｓ１端子、Ｓ２端子の３つ）を信号線用端子として用いる場合について適用してもよいことは言うまでもない。   Moreover, although the case where the four terminals of the G1, G2, S1, and S2 terminals are used as the signal line terminals has been described, the G1 terminal and the G2 terminal are shared, and the three terminals (G1, G2 common terminal, S1 terminal, Needless to say, the present invention may be applied to the case where three of the S2 terminals are used as signal line terminals.

また、金属板２４，６０，７０，８０として銅板を使用してもよいが、銅板以外の金属板を用いてもよい。
また、チップ１０ａ，１０ｂの２つのチップを並列接続してモジュール（マルチチップモジュール）としたが、３つ以上のチップをモジュール化してもよい。 Moreover, although a copper plate may be used as the metal plates 24, 60, 70, 80, a metal plate other than the copper plate may be used.
Further, although two chips of the chips 10a and 10b are connected in parallel to form a module (multi-chip module), three or more chips may be modularized.

比較例における半導体モジュールの平面図。 The top view of the semiconductor module in a comparative example . 図１のＡ−Ａ線での縦断面図。The longitudinal cross-sectional view in the AA line of FIG. 比較例におけるモールド樹脂の無い状態での半導体モジュールの平面図。 The top view of the semiconductor module in the state without mold resin in a comparative example . 図３のＡ−Ａ線での縦断面図。FIG. 4 is a longitudinal sectional view taken along line AA in FIG. 3. 比較例におけるモールド樹脂の無い状態での半導体モジュールの分解斜視図。The disassembled perspective view of the semiconductor module in the state without mold resin in a comparative example . 比較例における半導体モジュールの製造工程を説明するための分解図。The exploded view for demonstrating the manufacturing process of the semiconductor module in a comparative example . 比較例および実施形態における半導体モジュールを用いた負荷駆動回路の電気的構成を示す回路構成図。 The circuit block diagram which shows the electrical structure of the load drive circuit using the semiconductor module in a comparative example and embodiment. 第１の実施形態における半導体モジュールの平面図。The top view of the semiconductor module in a 1st embodiment. 図８のＡ−Ａ線での縦断面図。The longitudinal cross-sectional view in the AA line of FIG. 第１の実施形態における半導体モジュールの分解斜視図。The disassembled perspective view of the semiconductor module in 1st Embodiment. 第１の実施形態における半導体モジュールの製造工程を説明するための分解図。The exploded view for demonstrating the manufacturing process of the semiconductor module in 1st Embodiment. 第２の実施形態における半導体モジュールの平面図。The top view of the semiconductor module in 2nd Embodiment. 図１２のＡ−Ａ線での縦断面図。The longitudinal cross-sectional view in the AA line of FIG. 第２の実施形態における半導体モジュールの分解斜視図。The disassembled perspective view of the semiconductor module in 2nd Embodiment. 第３の実施形態における半導体モジュールの平面図。The top view of the semiconductor module in 3rd Embodiment. 図１５のＡ−Ａ線での縦断面図。The longitudinal cross-sectional view in the AA line of FIG. 第３の実施形態における半導体モジュールの分解斜視図。The disassembled perspective view of the semiconductor module in 3rd Embodiment. 第３の実施形態における絶縁性基板の下面および正面構造を示す図。The figure which shows the lower surface and front structure of an insulating board | substrate in 3rd Embodiment. 第４の実施形態における絶縁性基板の下面図。The bottom view of the insulating board | substrate in 4th Embodiment. 第５の実施形態における絶縁性基板の下面図。The bottom view of the insulating board | substrate in 5th Embodiment. 第５の実施形態におけるチップおよびヒートシンクの平面および側面構造を示す図。The figure which shows the plane and side surface structure of a chip | tip and a heat sink in 5th Embodiment.

符号の説明Explanation of symbols

１０…チップ、１０ａ…チップ、１０ｂ…チップ、１４…信号線用パッド、２０…ヒートシンク、２４…金属板、４０…絶縁性板材、４５…絶縁性基板、４５ａ…貫通孔、４６…絶縁性基板、５０…ヒートシンク、６０…金属板、７０…金属板、８０…金属板、Ｑ１…主パワートランジスタ。   DESCRIPTION OF SYMBOLS 10 ... Chip, 10a ... Chip, 10b ... Chip, 14 ... Signal line pad, 20 ... Heat sink, 24 ... Metal plate, 40 ... Insulating plate, 45 ... Insulating substrate, 45a ... Through hole, 46 ... Insulating substrate 50 ... heat sink, 60 ... metal plate, 70 ... metal plate, 80 ... metal plate, Q1 ... main power transistor.

Claims (7)

パワースイッチング素子（Ｑ１）が作り込まれており、少なくとも一方の面が放熱面となるとともに、片方の面において複数の信号線用パッド（１４）を有するチップ（１０）と、
前記チップ（１０）の放熱面に固着されたヒートシンク（２０）と、
前記チップ（１０）の各信号線用パッド（１４）に対応する外部接続端子を構成し、当該信号線用パッド（１４）に直接接合された金属板（２４）と、
前記各信号線用パッド（１４）に直接接合された各金属板（２４）をその裏面から一括して前記各信号線用パッド（１４）との間に挟む態様で配されて、それら金属板（２４）が共通に固着された絶縁性ベース部材（４０）と、
を備えたことを特徴とする半導体モジュール。 A power switching element (Q1) is built in, a chip (10) having at least one surface as a heat dissipation surface and a plurality of signal line pads (14) on one surface;
A heat sink (20) fixed to the heat dissipation surface of the chip (10);
A metal plate (24) that constitutes an external connection terminal corresponding to each signal line pad (14) of the chip (10) and is directly bonded to the signal line pad (14);
Wherein is arranged in a manner sandwiching between the respective metal plate bonded directly to the pad (14) for each signal line (24) in chunks from the back surface each signal line pad (14), which metal plate An insulating base member (40) to which (24) is fixed in common;
A semiconductor module comprising: 前記絶縁性ベース部材（４０）の材料は、セラミックまたは樹脂であることを特徴とする請求項１に記載の半導体モジュール。 The material of the insulating base member (40), the semiconductor module according to claim 1, wherein the ceramic or resin der Rukoto. パワースイッチング素子（Ｑ１）が作り込まれており、一方の面が第１の放熱面となるとともに、他方の面の一部領域が第２の放熱面となり、かつ、当該他方の面での他の領域において複数の信号線用パッド（１４）を有するチップ（１０）と、
前記チップ（１０）の第１の放熱面に固着された第１のヒートシンク（２０）と、
前記チップ（１０）の第２の放熱面側に配置され、貫通孔（４５ａ）を有する絶縁性基板（４５）と、
前記絶縁性基板（４５）に固着され、前記チップ（１０）の各信号線用パッド（１４）に対応する外部接続端子を構成し、当該信号線用パッド（１４）に直接接合された金属板（２４）と、
前記絶縁性基板（４５）の貫通孔（４５ａ）内に配置され、前記チップ（１０）の第２の放熱面に固着された第２のヒートシンク（５０）と、
を備えたことを特徴とする半導体モジュール。 The power switching element (Q1) is built in, and one surface becomes the first heat radiating surface, and part of the other surface becomes the second heat radiating surface, and the other surface is the other surface. A chip (10) having a plurality of signal line pads (14) in the region of
A first heat sink (20) secured to a first heat dissipation surface of the chip (10);
An insulating substrate (45) disposed on the second heat dissipation surface side of the chip (10) and having a through hole (45a);
A metal plate that is fixed to the insulating substrate (45), constitutes an external connection terminal corresponding to each signal line pad (14) of the chip (10), and is directly bonded to the signal line pad (14). (24)
A second heat sink (50) disposed in the through hole (45a) of the insulating substrate (45) and fixed to the second heat dissipation surface of the chip (10);
A semiconductor module comprising: 前記絶縁性基板（４５）の材料は、セラミックまたは樹脂であることを特徴とする請求項３に記載の半導体モジュール。 The semiconductor module according to claim 3, wherein the material of the insulating substrate is a ceramic or a resin . 前記チップを複数具備し、各チップ（１０ａ，１０ｂ）を当該各チップ（１０ａ，１０ｂ）に共通の第１のヒートシンク（２０）に固着するとともに、前記金属板（６０）を各チップ（１０ａ，１０ｂ）に共通の絶縁性基板（４６）に固着し、当該金属板（６０）により各チップ（１０ａ，１０ｂ）に共通の外部接続端子を構成するとともに各チップ（１０ａ，１０ｂ）の同じ機能の信号線用パッド（１４）をつなぐ配線を構成したことを特徴とする請求項３または４に記載の半導体モジュール。 A plurality of the chips are provided, and the chips (10a, 10b) are fixed to the first heat sink (20) common to the chips (10a, 10b), and the metal plate (60) is attached to the chips (10a, 10b). 10b) is fixed to a common insulating substrate (46), and the metal plate (60) constitutes an external connection terminal common to each chip (10a, 10b) and has the same function of each chip (10a, 10b). 5. The semiconductor module according to claim 3 , wherein a wiring for connecting the signal line pads (14) is formed . 前記金属板（７０）は、配線としての長さが各チップ（１０ａ，１０ｂ）で等しいことを特徴とする請求項５に記載の半導体モジュール。 The semiconductor module according to claim 5 wherein the metal plate (70), the length of the wiring, characterized in that equal at each chip (10a, 10b). 前記複数のチップは一対のチップ（１０ａ，１０ｂ）よりなり、この一対のチップ（１０ａ，１０ｂ）での信号線用パッドを配した辺（Ｓｃ１，Ｓｃ２）同士が対向するように一対のチップ（１０ａ，１０ｂ）を第１のヒートシンク（２０）上に配置するとともに、一対のチップ（１０ａ，１０ｂ）における信号線用パッドの列の並びとして同じ機能を有する信号線用パッド同士を対向させたことを特徴とする請求項６に記載の半導体モジュール。 Before SL plurality of chips consists of a pair of chips (10a, 10b), a pair of chip like this pair of chips (10a, 10b) edges arranged a signal line pad in (Sc1, Sc2) to each other to face (10a, 10b) are arranged on the first heat sink (20), and signal line pads having the same function as the row of signal line pads in the pair of chips (10a, 10b) are opposed to each other. The semiconductor module according to claim 6.
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