JP2007035913A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2007035913A
JP2007035913A JP2005216887A JP2005216887A JP2007035913A JP 2007035913 A JP2007035913 A JP 2007035913A JP 2005216887 A JP2005216887 A JP 2005216887A JP 2005216887 A JP2005216887 A JP 2005216887A JP 2007035913 A JP2007035913 A JP 2007035913A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
semiconductor element
lead frame
surface electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005216887A
Other languages
Japanese (ja)
Inventor
Masakatsu Takashita
正勝 高下
Yukishige Kanesaka
幸重 金坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2005216887A priority Critical patent/JP2007035913A/en
Publication of JP2007035913A publication Critical patent/JP2007035913A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37012—Cross-sectional shape
    • H01L2224/37013—Cross-sectional shape being non uniform along the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101—Structure
    • H01L2224/4103—Connectors having different sizes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To realize high reliability without degrading effects for reducing resistance owing to an enlargement of a connector area. <P>SOLUTION: A semiconductor element provided on a semiconductor device has a gate electrode 8 and a source electrode 151 which are surrounded by an insulation layer 121. A surface electrode is divided into a plurality of electrode pieces like the source electrode 151, thereby dispersing stress applied to the semiconductor element among the respective divided surface electrodes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子の電極とリードフレームをコネクタで接続する半導体装置に関するものである。   The present invention relates to a semiconductor device in which an electrode of a semiconductor element and a lead frame are connected by a connector.

半導体装置は、半導体素子とこれを設置するためのリードフレームを有し、従来はこの半導体素子とリードフレームをＡｌやＡｕ等から成るボンディングワイヤにより接合していた。しかし、半導体装置の低抵抗化の要請により、組み立て材料であるボンディングワイヤ部分の抵抗も無視できなくなってきている（特許文献１参照）。このため、ボンディングワイヤに代わり、平板状に成形された金属製のコネクタにより半導体素子とリードフレームを接続する方法が用いられるようになってきている。また、この方法を用いた際、コネクタと接する半導体素子の表面電極面積を大きくすることによって、半導体装置の更なる低抵抗化を図ることができる。   2. Description of the Related Art A semiconductor device has a semiconductor element and a lead frame for installing the semiconductor element. Conventionally, the semiconductor element and the lead frame are joined by a bonding wire made of Al, Au, or the like. However, the resistance of the bonding wire portion, which is an assembly material, cannot be ignored due to the demand for lower resistance of the semiconductor device (see Patent Document 1). For this reason, a method of connecting a semiconductor element and a lead frame by a metal connector formed in a flat plate shape instead of a bonding wire has been used. In addition, when this method is used, the resistance of the semiconductor device can be further reduced by increasing the surface electrode area of the semiconductor element in contact with the connector.

このように、半導体表面電極面積を増大させ、金属製のコネクタとの接続面積を増大させることで、半導体装置における抵抗を低減することができる。しかしながら、半導体装置は、表面電極材と半導体基材（例えばシリコン）、複数の電極材の場合は表面電極材料間、電極材と接するコネクタ等、線膨張係数の異なる材料の接合体であることから、半導体装置の温度変化に対し、表面電極面積が大きくなると、表面電極終端部に発生する熱応力が増大する。これにより、温度サイクル試験などの信頼性評価において電気特性上の性能劣化を引き起こし、電気的特性が安定しない等の問題が生じている。   Thus, the resistance in the semiconductor device can be reduced by increasing the semiconductor surface electrode area and increasing the connection area with the metal connector. However, a semiconductor device is a joined body of materials having different linear expansion coefficients, such as a surface electrode material and a semiconductor substrate (for example, silicon), in the case of a plurality of electrode materials, between surface electrode materials, a connector in contact with the electrode material, and the like. When the surface electrode area increases with respect to the temperature change of the semiconductor device, the thermal stress generated at the surface electrode termination portion increases. As a result, in the reliability evaluation such as the temperature cycle test, there is a problem that the electrical characteristics are deteriorated and the electrical characteristics are not stable.

また、表面電極面積の増大に伴い、温度変化を伴わなくとも、半導体装置の製造時に表面電極の残留応力によりウェーハが反って従来の装置では搬送できない、製造時の温度ストレスでも半導体の電気的特性を劣化させる等の問題点があった。このように、従来技術では低抵抗かつ高信頼性の両立を実現することは困難であった。
特開２００４−１１１７４５号公報、段落００１２〜００１４、図１〜図４ In addition, with the increase in surface electrode area, even if the temperature does not change, the wafer warps due to the residual stress of the surface electrode during manufacturing of the semiconductor device and cannot be transported by conventional devices. There was a problem such as degrading. As described above, it has been difficult to achieve both low resistance and high reliability in the prior art.
JP 2004-111745 A, paragraphs 0012 to 0014, FIGS.

本発明は、表面電極面積増大に伴う低抵抗化の効果を損なわずに、高信頼性を実現する半導体装置を提供することを目的とする。   An object of this invention is to provide the semiconductor device which implement | achieves high reliability, without impairing the effect of the low resistance accompanying the surface electrode area increase.

本発明に係る半導体装置は、半導体素子と、前記半導体素子を載置するように構成され外部への出力のための端子を備えたリードフレームと、前記半導体素子の表面電極と前記リードフレームを電気的に接合するコネクタとを備えた半導体装置であって、前記表面電極は複数の電極片に分割され、該複数の電極片が１つの前記コネクタに接続されるように構成されたことを特徴とする。   A semiconductor device according to the present invention electrically connects a semiconductor element, a lead frame configured to mount the semiconductor element and provided with a terminal for output to the outside, a surface electrode of the semiconductor element, and the lead frame. A semiconductor device comprising a connector for jointing, wherein the surface electrode is divided into a plurality of electrode pieces, and the plurality of electrode pieces are connected to one connector. To do.

本発明によれば、表面電極面積増大に伴う低抵抗化の効果を損なわずに、高信頼性を実現する半導体装置を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which implement | achieves high reliability can be provided, without impairing the effect of low resistance accompanying the surface electrode area increase.

以下図面を参照して、本発明の実施の形態を説明する。図１は、本発明の実施形態に係る半導体装置１００の構成を示す上面図である。図２は、同じく図１のＣ−Ｃ’面における断面図である。この実施形態では、半導体装置１００は、一例としてＴＯ−２２０パッケージの表面側にソース、裏面側にドレインが形成された縦型のＭＯＳＦＥＴである。半導体素子１とリードフレーム２とが、ソース側コネクタ３及びゲート側コネクタ４によって電気的に接合されている。半導体素子１には、ソース電極７とゲート電極８が配されている。また半導体素子１，リードフレーム２，ソース側コネクタ３及びゲート側コネクタ４の間の各接合部は、半田９によって接着されている。またソース側コネクタ３はリードフレーム２が有するリードフレーム端子２ａに、ゲート側コネクタ２ｂはリードフレーム２が有するリードフレーム端子２ｂにそれぞれ接続されている。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a top view showing a configuration of a semiconductor device 100 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the C-C ′ plane of FIG. 1. In this embodiment, the semiconductor device 100 is, for example, a vertical MOSFET in which a source is formed on the front surface side and a drain is formed on the back surface side of the TO-220 package. The semiconductor element 1 and the lead frame 2 are electrically joined by the source side connector 3 and the gate side connector 4. The semiconductor element 1 is provided with a source electrode 7 and a gate electrode 8. Each joint between the semiconductor element 1, the lead frame 2, the source side connector 3, and the gate side connector 4 is bonded by solder 9. The source side connector 3 is connected to a lead frame terminal 2a of the lead frame 2, and the gate side connector 2b is connected to a lead frame terminal 2b of the lead frame 2.

次に同装置の形成工程の一例を説明する。まず、リードフレーム２のダイパッド２ｃ上に半田９を用いて半導体素子１をマウントして、リードフレーム２とドレインを接続する。次にリードフレーム端子２ａをソース側コネクタ３を介してソース電極７に半田９を用いて接合する。同様に、リードフレーム端子２ｂをゲート側コネクタ４を介してゲート電極６に半田９を用いて接合する。更に、モールド樹脂１０で全体を封止後リードカットし、半導体装置１００を得る。   Next, an example of the formation process of the apparatus will be described. First, the semiconductor element 1 is mounted on the die pad 2c of the lead frame 2 using the solder 9, and the lead frame 2 and the drain are connected. Next, the lead frame terminal 2 a is joined to the source electrode 7 using the solder 9 via the source side connector 3. Similarly, the lead frame terminal 2 b is joined to the gate electrode 6 using the solder 9 via the gate side connector 4. Further, the whole is sealed with the mold resin 10 and then lead-cut and the semiconductor device 100 is obtained.

次に、同装置の半導体素子１が有するソース電極７について以下説明する。図３は、従来の半導体素子１の構成を示す上面図である。図４は、同じく図３におけるＤ−Ｄ’面での断面図である。半導体素子１のソース電極７は、Ａｌ電極１３の上にＮｉ電極１４が配され、さらにその上にＡｕ電極１５がメッキされている。また、表面電極であるＮｉ電極１４及びＡｕ電極１５は絶縁層１２によって囲まれている。   Next, the source electrode 7 included in the semiconductor element 1 of the apparatus will be described below. FIG. 3 is a top view showing a configuration of a conventional semiconductor element 1. FIG. 4 is a cross-sectional view taken along the D-D ′ plane in FIG. 3. The source electrode 7 of the semiconductor element 1 has a Ni electrode 14 disposed on an Al electrode 13 and an Au electrode 15 plated thereon. Further, the Ni electrode 14 and the Au electrode 15 which are surface electrodes are surrounded by the insulating layer 12.

図５は、本発明の第１の実施形態である半導体素子１の構成を示す上面図である。図６は、同じく図５におけるＥ−Ｅ’面での断面図である。従来の構成との相違点は、表面電極であるＮｉ電極１４１及びＡｕ電極１５１が、メッシュ状に形成された仕切層としての絶縁層１２１によって複数の電極片に分割されている点である。絶縁層１２１は、熱膨張係数に優れた材質であれば様々なものが利用できるが、例えばポリイミド等が好適である。また、熱膨張係数に優れた材質である限りにおいて、仕切層として導電性のものを用いても差し支えない。   FIG. 5 is a top view showing the configuration of the semiconductor element 1 according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view taken along the plane E-E ′ in FIG. 5. The difference from the conventional configuration is that the Ni electrode 141 and the Au electrode 151 as surface electrodes are divided into a plurality of electrode pieces by an insulating layer 121 as a partition layer formed in a mesh shape. A variety of materials can be used for the insulating layer 121 as long as the material has an excellent thermal expansion coefficient. For example, polyimide is preferable. In addition, as long as the material has an excellent thermal expansion coefficient, a conductive layer may be used as the partition layer.

このように、表面電極であるＮｉ電極１４１及びＡｕ電極１５１を仕切層である絶縁層１２１によって分割することにより、温度変化に対する応力が、分割された各電極間の絶縁層に分散され、従来起こっていた電極内の温度差による熱ひずみが減少し、温度サイクル試験などの信頼性レベルが向上させることができる。   As described above, by dividing the Ni electrode 141 and the Au electrode 151 which are the surface electrodes by the insulating layer 121 which is the partition layer, the stress with respect to the temperature change is dispersed in the insulating layer between the divided electrodes, which occurs in the past. The thermal strain due to the temperature difference in the electrode has been reduced, and the reliability level of the temperature cycle test and the like can be improved.

また、半導体装置製作時に発生する熱応力も低減され、電気的特性の劣化を防ぐことも可能となる。   In addition, thermal stress generated at the time of manufacturing a semiconductor device is reduced, and it is possible to prevent deterioration of electrical characteristics.

更に、分割された個々の電極片の表面積は従来の表面電極の面積より小さいため、従来に比べ表面電極の反りを軽減することが可能となった。また、個々の分割された電極片の表面積を合計した全体の表面電極面積は、従来の表面電極面積とほぼ等しいため、従来の表面電極面積増大に伴う低抵抗性を十分に備えている。   Furthermore, since the surface area of each divided electrode piece is smaller than the area of the conventional surface electrode, the warpage of the surface electrode can be reduced as compared with the conventional case. Further, the total surface electrode area obtained by summing the surface areas of the individual electrode pieces is almost equal to the conventional surface electrode area, and thus sufficiently has low resistance accompanying an increase in the conventional surface electrode area.

図７及び図８は、本実施形態の性能評価として行ったシミュレーション結果である。図７は、本実施形態に従った半導体装置，従来の表面電極が小さいタイプの半導体装置，従来の表面電極が大きいタイプの半導体装置における電流と各半導体装置の消費電力との関係である。これによると、従来の表面電極が大きいタイプと本実施形態が、従来の表面電極が小さいタイプと比較し消費電力が小さいことがわかる。また、本実施形態における消費電力は従来の表面電極が大きいタイプと比較するとわずかに大きくなっているが、これは各電極間に仕切層を設置するため、仕切層の分だけ従来の表面電極が大きいタイプに比べ表面電極面積が小さくなるためである。   7 and 8 show simulation results performed as performance evaluation of this embodiment. FIG. 7 shows the relationship between the current and the power consumption of each semiconductor device in the semiconductor device according to the present embodiment, a conventional semiconductor device with a small surface electrode, and a conventional semiconductor device with a large surface electrode. According to this, it can be seen that the power consumption of the conventional type with a large surface electrode and the present embodiment is smaller than that of the conventional type with a small surface electrode. In addition, the power consumption in this embodiment is slightly larger than the type with a large conventional surface electrode, but this is because a partition layer is installed between each electrode, so that the conventional surface electrode is equivalent to the partition layer. This is because the surface electrode area is smaller than that of the larger type.

図８は、本実施形態に従った半導体装置及び従来の表面電極が大きいタイプの半導体装置における、温度サイクル試験時の初期リーク電流とリーク電流との関係を示すグラフである。温度サイクル試験は、半導体装置を製品として実装する際の温度サイクルを想定し、温度を繰り返し負荷することによって半導体装置のリーク電流の変化を調べるものである。温度を負荷する前の初期リーク電流を横軸に、温度サイクルを負荷していったときのリーク電流を縦軸にとっている。これによると、従来の表面電極が大きいタイプは、温度サイクルの回数が多くなるに従いリーク電流が大きくなっていくが、本実施形態では、温度サイクルを負荷していってもリーク電流が変化しない。この結果から、本実施形態は低抵抗性を保持しながら、高信頼性を実現することが可能であることがわかる。   FIG. 8 is a graph showing the relationship between the initial leakage current and the leakage current in the temperature cycle test in the semiconductor device according to the present embodiment and the conventional semiconductor device with a large surface electrode. The temperature cycle test assumes a temperature cycle when a semiconductor device is mounted as a product, and examines a change in leakage current of the semiconductor device by repeatedly applying temperature. The horizontal axis represents the initial leakage current before loading the temperature, and the vertical axis represents the leakage current when the temperature cycle is loaded. According to this, in the conventional type with a large surface electrode, the leakage current increases as the number of temperature cycles increases, but in this embodiment, the leakage current does not change even when the temperature cycle is loaded. From this result, it can be seen that this embodiment can achieve high reliability while maintaining low resistance.

次に、本発明の実施例における製造方法を説明する。従来の半導体装置の製造方法は、Ａｌ電極１３上全面にポリイミド膜１２を堆積し、マスクパターンを用いてポリイミド膜１２をエッチング後、メッキ等でＮｉ電極１４及びＡｕ電極１５を形成する。本実施形態は、この従来の半導体素子製造過程において、マスクパターンを変更するだけで本実施例を実現することが可能であり、生産手順や生産コストを付加せずに実施することが可能である。   Next, the manufacturing method in the Example of this invention is demonstrated. In a conventional method for manufacturing a semiconductor device, a polyimide film 12 is deposited on the entire surface of an Al electrode 13, and after etching the polyimide film 12 using a mask pattern, a Ni electrode 14 and an Au electrode 15 are formed by plating or the like. This embodiment can be realized by simply changing the mask pattern in this conventional semiconductor element manufacturing process, and can be carried out without adding production procedures and production costs. .

また、他の実施例として、図９及び図１０の様に絶縁層１２をストライプ形状にしたり、図１１及び図１２のように他材料による仕切層を設置せず、表面電極１４４，１５４を複数の電極片に分割形成するだけでもよい。例えば、電極１４４，１５４をＡｌ電極１３上全面に形成した後、これをマスクパターンを用いてエッチングして分割を行うことができる。   As another embodiment, a plurality of surface electrodes 144 and 154 are provided without forming the insulating layer 12 in a stripe shape as shown in FIGS. 9 and 10 or installing a partition layer made of other materials as shown in FIGS. It is also possible to divide and form the electrode pieces. For example, after the electrodes 144 and 154 are formed on the entire surface of the Al electrode 13, they can be divided by etching using a mask pattern.

本実施例では、半導体表面電極部はメッキにてＮｉ電極及びＡｕ電極を形成しているが、スパッタや蒸着などの製造方法を用いても、半導体表面電極部を形成することが可能である。   In the present embodiment, the semiconductor surface electrode portion is formed with the Ni electrode and the Au electrode by plating, but the semiconductor surface electrode portion can be formed even by using a manufacturing method such as sputtering or vapor deposition.

また、本実施例では接着材料として半田を用いたが、導電性硬化材料を用いることも可能である。   In this embodiment, solder is used as the adhesive material, but a conductive curable material can also be used.

本発明のひとつの実施形態に係る半導体装置の全体構造を示す上面図である。It is a top view which shows the whole structure of the semiconductor device which concerns on one Embodiment of this invention. 同装置の断面図である。It is sectional drawing of the same apparatus. 同装置における従来の半導体素子の構造を示す上面図である。It is a top view which shows the structure of the conventional semiconductor element in the apparatus. 同装置の図３におけるＤ−Ｄ’面の断面図である。It is sectional drawing of the D-D 'surface in FIG. 3 of the same apparatus. 同装置における本発明の第１の実施形態に係る半導体素子の構成を示す上面図である。It is a top view which shows the structure of the semiconductor element which concerns on the 1st Embodiment of this invention in the apparatus. 同装置における図５のＥ−Ｅ’面の断面図である。It is sectional drawing of the E-E 'surface of FIG. 5 in the same apparatus. 電流と消費電力との関係を示すグラフである。It is a graph which shows the relationship between an electric current and power consumption. 温度サイクル試験における初期リーク電流とリーク電流の関係を示すグラフである。It is a graph which shows the relationship between the initial leakage current in a temperature cycle test, and leakage current. 本発明の他の実施の形態を示す上面図である。It is a top view which shows other embodiment of this invention. 本発明の更に他の実施の形態を示す上面図である。It is a top view which shows other embodiment of this invention. 本発明の更に他の実施の形態を示す上面図である。It is a top view which shows other embodiment of this invention. 同装置における図１１のＦ−Ｆ’面の断面図である。It is sectional drawing of the F-F 'surface of FIG. 11 in the same apparatus.

符号の説明Explanation of symbols

１…半導体素子、２…リードフレーム、３…ソース側コネクタ、４…ゲート側コネクタ、７…ソース電極、８…ゲート電極、９…半田、１０…モールド樹脂、１２，１２１，１２２，１２３，１２４…絶縁層、１３…Ａｌ電極、１４，１４１，１４４…Ｎｉ電極、１５，１５１，１５２，１５３，１５４…Ａｕ電極。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Lead frame, 3 ... Source side connector, 4 ... Gate side connector, 7 ... Source electrode, 8 ... Gate electrode, 9 ... Solder, 10 ... Mold resin, 12, 121, 122, 123, 124 ... Insulating layer, 13 ... Al electrode, 14, 141, 144 ... Ni electrode, 15, 151, 152, 153, 154 ... Au electrode.

Claims (5)

半導体素子と、
前記半導体素子を載置するように構成され外部への出力のための端子を備えたリードフレームと、
前記半導体素子の表面電極と前記リードフレームを電気的に接合するコネクタと
を備えた半導体装置であって、
前記表面電極は複数の電極片に分割され、該複数の電極片が１つの前記コネクタに接続されるように構成された
ことを特徴とする半導体装置。 A semiconductor element;
A lead frame configured to place the semiconductor element and provided with a terminal for output to the outside;
A semiconductor device comprising a surface electrode of the semiconductor element and a connector for electrically joining the lead frame,
The semiconductor device, wherein the surface electrode is divided into a plurality of electrode pieces, and the plurality of electrode pieces are connected to one connector. 前記複数の電極片を仕切るよう前記電極片の間に介在された仕切層を更に備えたことを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, further comprising a partition layer interposed between the electrode pieces so as to partition the plurality of electrode pieces. 前記仕切層は、メッシュ又はストライプ形状に成形され、前記複数の電極片は前記仕切層によって分割されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the partition layer is formed in a mesh or stripe shape, and the plurality of electrode pieces are divided by the partition layer. 前記仕切層は絶縁体から構成されるものであることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the partition layer is made of an insulator. 前記仕切層は、ポリイミドから構成されるものであることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the partition layer is made of polyimide.
JP2005216887A 2005-07-27 2005-07-27 Semiconductor device Withdrawn JP2007035913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005216887A JP2007035913A (en) 2005-07-27 2005-07-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005216887A JP2007035913A (en) 2005-07-27 2005-07-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2007035913A true JP2007035913A (en) 2007-02-08

Family

ID=37794802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005216887A Withdrawn JP2007035913A (en) 2005-07-27 2005-07-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2007035913A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9059153B2 (en) 2012-03-21 2015-06-16 Kabushiki Kaisha Toshiba Semiconductor device
US10128345B2 (en) 2016-12-09 2018-11-13 Fuji Electric Co., Ltd. Semiconductor device
US10332845B2 (en) 2016-12-09 2019-06-25 Fuji Electric Co., Ltd. Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9059153B2 (en) 2012-03-21 2015-06-16 Kabushiki Kaisha Toshiba Semiconductor device
US10128345B2 (en) 2016-12-09 2018-11-13 Fuji Electric Co., Ltd. Semiconductor device
US10332845B2 (en) 2016-12-09 2019-06-25 Fuji Electric Co., Ltd. Semiconductor device

Similar Documents

Publication Publication Date Title
US8575745B2 (en) Power semiconductor device, printed wiring board, and mechanism for connecting the power semiconductor device and the printed wiring board
JP2008171938A (en) Semiconductor device and its manufacturing method
JP4226200B2 (en) Semiconductor device and manufacturing method thereof
JP4468115B2 (en) Semiconductor device
JPH11289023A (en) Semiconductor device and manufacture thereof
GB2451077A (en) Semiconductor chip package
US9711484B2 (en) Semiconductor package with semiconductor die directly attached to lead frame and method
JP2015220341A (en) Metal base substrate, power module, and manufacturing method of metal base substrate
JP2009105305A (en) Thermoelectric module
JP4069070B2 (en) Power semiconductor module
JP6043049B2 (en) Semiconductor device mounting structure and semiconductor device mounting method
JP2007035913A (en) Semiconductor device
JPWO2021193823A5 (en)
JP2002009217A (en) Resin-sealed semiconductor device
JP2008294219A (en) Semiconductor device, and manufacturing method thereof
JP2005183568A (en) Power semiconductor device
JP6292066B2 (en) Power semiconductor device
US20180366631A1 (en) Thermoelectric conversion module and method for manufacturing thermoelectric conversion module
JP2009164511A (en) Semiconductor device and method of manufacturing the same
JP5124329B2 (en) Semiconductor device
JP2003124251A5 (en)
JP4329187B2 (en) Semiconductor element
JP7180735B2 (en) Lead frames and semiconductor equipment
JP4047572B2 (en) Power semiconductor device
US20030039102A1 (en) Semiconductor chip mounting substrate and semiconductor device using it

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20081007