JP2008171938A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2008171938A
JP2008171938A JP2007002429A JP2007002429A JP2008171938A JP 2008171938 A JP2008171938 A JP 2008171938A JP 2007002429 A JP2007002429 A JP 2007002429A JP 2007002429 A JP2007002429 A JP 2007002429A JP 2008171938 A JP2008171938 A JP 2008171938A
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electrode
circuit board
semiconductor element
protruding electrode
insulating layer
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JP5347222B2 (en
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Yoshikatsu Ishizuki
義克 石月
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To increase a packaging density in a laminated structure type semiconductor device. <P>SOLUTION: The semiconductor device has at least one semiconductor element 21 loaded on a circuit board 10, bump electrodes 12 formed on at least one electrode pad 11 disposed on the circuit board 10 and the bump electrodes 23 formed on at least one electrode pad 22 of the semiconductor element 21. The semiconductor device further has an insulating layer 30 coating the side faces of the bump electrodes 12 and the bump electrodes 23 and being formed on the circuit board 10 and the semiconductor element 21 and wiring layers 32 disposed on the insulating layer 30 and electrically connected to the wiring layers 31 electrically connected to the bump electrodes 12 and the bump electrodes 23. The heights of the bump electrodes 12 and the bump electrodes 23 formed in the insulating layer 30 are equalized. Accordingly, a metallic wire need not be drawn around in the insulating layer 30, thus increasing the packaging density of the semiconductor device 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置及び半導体装置の製造方法に関し、特に実装技術を用いた半導体装置及び半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device using mounting technology.

近年、半導体装置の高密度化、高機能化も進み、一つの半導体装置内に複数の半導体素子を搭載して一体化する実装技術が開発されている。例えば、複数の異なる種類や機能の半導体素子を同じ回路基板上に搭載し、それらを相互に半導体装置内で接続し、更に外部接続用端子が設けられた半導体装置が普及している。   2. Description of the Related Art In recent years, semiconductor devices have been increased in density and functionality, and a mounting technology for mounting and integrating a plurality of semiconductor elements in one semiconductor device has been developed. For example, a semiconductor device in which a plurality of different types and functions of semiconductor elements are mounted on the same circuit board, connected to each other within the semiconductor device, and further provided with an external connection terminal has become widespread.

そして、最近では、更なる微細構造に対応した実装技術として、複数の半導体素子や多層配線を有した回路基板を積層構造にしてパッケージする実装技術が注目されている。
このような実装技術では、層間に形成する電極として、例えば、半導体素子の電極上に、材質が銅（Ｃｕ）の銅ポストを形成する。そして、銅ポストを形成させた半導体素子を樹脂で封止し、封止した樹脂の表面を研磨して銅ポストを樹脂から露出させる。さらに、銅ポストが露出した樹脂面に引き回し用の再配線を配設し、再配線上に外部接続用端子を形成する（例えば、特許文献１）。
特開２０００−１２４３５４号公報 Recently, a mounting technique for packaging a circuit board having a plurality of semiconductor elements and multilayer wirings in a laminated structure has attracted attention as a mounting technique corresponding to a further fine structure.
In such a mounting technique, for example, a copper post made of copper (Cu) is formed on an electrode of a semiconductor element as an electrode formed between layers. Then, the semiconductor element on which the copper post is formed is sealed with resin, and the surface of the sealed resin is polished to expose the copper post from the resin. Further, a rewiring for routing is provided on the resin surface where the copper post is exposed, and an external connection terminal is formed on the rewiring (for example, Patent Document 1).
JP 2000-124354 A

しかしながら、特開２０００−１２４３５４号公報に開示される従来の金属ポストの形成方法では、例えば、半導体素子上の同じ高さに位置する電極部から、金属ポストを形成しているに過ぎない。従って、積層構造型の実装において、回路基板の電極部及び半導体素子の電極部の双方から金属ポストを形成させる必要がある場合、高さの異なる下地から同じ高さの金属ポストを形成することができないという問題があった。   However, in the conventional method for forming a metal post disclosed in Japanese Patent Laid-Open No. 2000-124354, for example, the metal post is merely formed from electrode portions located at the same height on the semiconductor element. Therefore, when it is necessary to form a metal post from both the electrode part of the circuit board and the electrode part of the semiconductor element in the stacked structure type mounting, it is possible to form the metal post having the same height from the bases having different heights. There was a problem that I could not.

その理由は、例えば、電解めっき法では、高さの異なる下地から、同じ高さの金属ポストを制御して形成することは不可能だからである。また、電解めっき法を用いて、金属ポストの高さを揃えようとすると、回路基板の電極部上に形成する金属ポストを、半導体素子の電極部上に形成する金属ポストの高さ以上にするための厚膜レジストを半導体素子を除いた回路基板領域に形成させる必要がある。しかし、このような厚膜レジストを半導体素子が搭載されている領域外の回路基板領域に部分的に形成することは難しい。また、研磨法を用いての金属ポストの高さを調整することもできるが、研磨法を導入すると、製造工程が多工程になり、製造コストの低減ができないという問題があった。   The reason is that, for example, in the electroplating method, it is impossible to control and form metal posts having the same height from bases having different heights. Moreover, when trying to make the metal post height uniform by using the electrolytic plating method, the metal post formed on the electrode part of the circuit board is set to be equal to or higher than the metal post formed on the electrode part of the semiconductor element. Therefore, it is necessary to form a thick film resist in the circuit board region excluding the semiconductor element. However, it is difficult to partially form such a thick film resist in the circuit board region outside the region where the semiconductor element is mounted. Moreover, although the height of the metal post using the polishing method can be adjusted, there is a problem that when the polishing method is introduced, the manufacturing process becomes multi-step and the manufacturing cost cannot be reduced.

このように、積層構造型の実装では、簡便且つ確実に、回路基板及び半導体素子の表面から、同じ高さの金属ポストを形成できないという問題があった。
本発明は、このような点に鑑みてなされたものであり、回路基板の電極部及び半導体装置の電極部に、スタッドバンプ法によって同じ高さの突起電極を形成させた半導体装置及びその製造方法を提供すると共に、半導体装置の実装密度をより向上させることを目的とする。 As described above, in the stacked structure type mounting, there has been a problem that metal posts having the same height cannot be formed easily and reliably from the surfaces of the circuit board and the semiconductor element.
The present invention has been made in view of the above points, and a semiconductor device in which protruding electrodes having the same height are formed by the stud bump method on an electrode portion of a circuit board and an electrode portion of the semiconductor device, and a manufacturing method thereof. And to improve the mounting density of the semiconductor device.

本発明では上記課題を解決するために、図１に示すような半導体装置１が提供される。図１に示す半導体装置１は、回路基板１０上に搭載された少なくとも一つの半導体素子２１と、回路基板１０上に配設された少なくとも一つの電極（電極パッド１１）上に形成された突起電極１２と、半導体素子２１の少なくとも一つの電極（電極パッド２２）上に形成された突起電極２３と、突起電極１２及び突起電極２３の側面を被覆し、回路基板１０及び半導体素子２１上に形成された絶縁層３０と、絶縁層３０上に配設され、突起電極１２と電気的に接続された配線層３１及び突起電極２３と電気的に接続された配線層３２と、を備える。そして、絶縁層３０の内部に形成されている突起電極１２と突起電極２３の高さが均一であることを特徴とする。   In order to solve the above problems, the present invention provides a semiconductor device 1 as shown in FIG. A semiconductor device 1 shown in FIG. 1 includes at least one semiconductor element 21 mounted on a circuit board 10 and a protruding electrode formed on at least one electrode (electrode pad 11) provided on the circuit board 10. 12, the protruding electrode 23 formed on at least one electrode (electrode pad 22) of the semiconductor element 21, and the side surfaces of the protruding electrode 12 and the protruding electrode 23, and formed on the circuit board 10 and the semiconductor element 21. And an insulating layer 30, a wiring layer 31 disposed on the insulating layer 30 and electrically connected to the protruding electrode 12, and a wiring layer 32 electrically connected to the protruding electrode 23. The protruding electrodes 12 and the protruding electrodes 23 formed inside the insulating layer 30 are uniform in height.

このような半導体装置１によれば、回路基板１０上に少なくとも一つの半導体素子２１が搭載され、回路基板１０上に配設された少なくとも一つの電極上に突起電極１２が形成され、半導体素子２１の少なくとも一つの電極上に突起電極２３が形成され、突起電極１２及び突起電極２３の側面を被覆するように、回路基板１０及び半導体素子２１上に絶縁層３０が形成され、絶縁層３０上に、突起電極１２と電気的に接続された配線層３１及び突起電極２３と電気的に接続された配線層３２が配設される。そして、絶縁層３０の内部に形成されている突起電極１２と突起電極２３の高さは、均一である。   According to such a semiconductor device 1, at least one semiconductor element 21 is mounted on the circuit board 10, and the protruding electrode 12 is formed on at least one electrode disposed on the circuit board 10. The projecting electrode 23 is formed on at least one of the electrodes, and the insulating layer 30 is formed on the circuit board 10 and the semiconductor element 21 so as to cover the projecting electrode 12 and the side surfaces of the projecting electrode 23. A wiring layer 31 electrically connected to the protruding electrode 12 and a wiring layer 32 electrically connected to the protruding electrode 23 are disposed. The heights of the protruding electrode 12 and the protruding electrode 23 formed inside the insulating layer 30 are uniform.

また、本発明では上記課題を解決するために、スタッドバンプ法によって、回路基板上に配設された電極上に第１の突起電極を形成し、半導体素子の電極上に、前記第１の突起電極と同じ高さの第２の突起電極を形成する工程と、前記回路基板及び前記半導体素子の上に、金属膜が被覆された絶縁層を前記絶縁層の側から熱圧着する工程と、前記金属膜をパターニングし、前記第１の突起電極に電気的に接続された第１の配線層と、前記第２の突起電極に電気的に接続された第２の配線層とを前記絶縁層上に形成する工程と、を有することを特徴とする半導体装置の製造方法が提供される。   In the present invention, in order to solve the above problem, a first bump electrode is formed on an electrode disposed on a circuit board by a stud bump method, and the first bump is formed on an electrode of a semiconductor element. A step of forming a second protruding electrode having the same height as the electrode, a step of thermocompression-bonding an insulating layer coated with a metal film on the circuit board and the semiconductor element from the side of the insulating layer, A metal film is patterned, and a first wiring layer electrically connected to the first protruding electrode and a second wiring layer electrically connected to the second protruding electrode are formed on the insulating layer. And a step of forming the semiconductor device. A method for manufacturing a semiconductor device is provided.

このような半導体装置の製造方法によれば、スタッドバンプ法によって、回路基板上に配設された電極上に第１の突起電極が形成され、半導体素子の電極上に、第１の突起電極と同じ高さの第２の突起電極が形成され、回路基板及び半導体素子の上に、金属膜が被覆された絶縁層が絶縁層の側から熱圧着され、金属膜がパターニングされ、第１の突起電極に電気的に接続された第１の配線層と、第２の突起電極に電気的に接続された第２の配線層が絶縁層上に形成される。   According to such a semiconductor device manufacturing method, the first bump electrode is formed on the electrode disposed on the circuit board by the stud bump method, and the first bump electrode and the first bump electrode are formed on the electrode of the semiconductor element. A second protruding electrode having the same height is formed. An insulating layer covered with a metal film is thermocompression-bonded from the insulating layer side on the circuit board and the semiconductor element, the metal film is patterned, and the first protrusion is formed. A first wiring layer electrically connected to the electrode and a second wiring layer electrically connected to the second protruding electrode are formed on the insulating layer.

本発明では、回路基板上に少なくとも一つの半導体素子を搭載し、回路基板上に配設された少なくとも一つの電極上に突起電極を形成し、半導体素子の少なくとも一つの電極上に突起電極を形成し、突起電極及び突起電極の側面を被覆するように、回路基板及び半導体素子上に絶縁層を形成し、絶縁層上に、突起電極と電気的に接続された配線層及び突起電極と電気的に接続された配線層を配設するようにした。そして、絶縁層の内部に形成されている突起電極と突起電極の高さを均一になるようにした。   In the present invention, at least one semiconductor element is mounted on a circuit board, a protruding electrode is formed on at least one electrode disposed on the circuit board, and a protruding electrode is formed on at least one electrode of the semiconductor element. Then, an insulating layer is formed on the circuit board and the semiconductor element so as to cover the protruding electrode and the side surface of the protruding electrode, and the wiring layer and the protruding electrode electrically connected to the protruding electrode are electrically connected to the insulating layer. A wiring layer connected to is arranged. And the height of the protruding electrode and the protruding electrode formed inside the insulating layer was made uniform.

また、本発明では、スタッドバンプ法によって、回路基板上に配設された電極上に第１の突起電極を形成し、半導体素子の電極上に、第１の突起電極と同じ高さの第２の突起電極を形成し、回路基板及び半導体素子の上に、金属膜が被覆された絶縁層を絶縁層の側から熱圧着し、金属膜をパターニングし、第１の突起電極に電気的に接続された第１の配線層と、第２の突起電極に電気的に接続された第２の配線層を絶縁層上に形成するようにした。   In the present invention, the first bump electrode is formed on the electrode disposed on the circuit board by the stud bump method, and the second bump having the same height as the first bump electrode is formed on the electrode of the semiconductor element. The insulating layer covered with the metal film is thermocompression-bonded from the insulating layer side on the circuit board and the semiconductor element, the metal film is patterned, and electrically connected to the first protruding electrode. The first wiring layer thus formed and the second wiring layer electrically connected to the second protruding electrode are formed on the insulating layer.

これにより、下地の高さが異なった場合においても、同じ高さの突起電極を備えた半導体装置が実現する。また、そのような突起電極を備えた簡便且つ確実な半導体装置の製造方法が実現する。その結果、半導体装置の実装密度をより向上させることができる。   As a result, a semiconductor device having protruding electrodes having the same height is realized even when the bases have different heights. In addition, a simple and reliable method for manufacturing a semiconductor device including such protruding electrodes is realized. As a result, the mounting density of the semiconductor device can be further improved.

以下、本発明の実施の形態を、図面を参照して詳細に説明する。
図１は半導体装置の要部断面模式図である。
この図に示す半導体装置１は、回路基板１０上に、接着層２０を介して半導体素子２１が搭載されている。回路基板１０上には、配線パターンが形成され、金属製の電極パッド１１が配設されている。また、半導体素子２１上には、金属製の電極パッド２２が形成されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic cross-sectional view of a main part of a semiconductor device.
In the semiconductor device 1 shown in this figure, a semiconductor element 21 is mounted on a circuit board 10 via an adhesive layer 20. A wiring pattern is formed on the circuit board 10 and a metal electrode pad 11 is provided. A metal electrode pad 22 is formed on the semiconductor element 21.

そして、回路基板１０には、少なくとも一つの電極パッド１１が形成され、電極パッド１１上には、金属ポストとして突起電極１２（スタッドバンプ）が形成されている。また、半導体素子２１には、少なくとも一つの電極パッド２２が形成され、電極パッド２２上には、金属ポストとして突起電極２３が形成されている。そして、これらの絶縁層３０の内部に形成された突起電極１２、突起電極２３は、同じ高さであり、均一の高さに形成されている。   At least one electrode pad 11 is formed on the circuit board 10, and a protruding electrode 12 (stud bump) is formed on the electrode pad 11 as a metal post. Further, at least one electrode pad 22 is formed on the semiconductor element 21, and a protruding electrode 23 is formed on the electrode pad 22 as a metal post. The protruding electrodes 12 and the protruding electrodes 23 formed inside these insulating layers 30 have the same height and are formed at a uniform height.

また、、回路基板１０及び半導体素子２１上には、突起電極１２及び突起電極２３の側面を被覆するように絶縁層３０が形成されている。
さらに、絶縁層３０上には、配線層３１、配線層３２がパターン形成され、突起電極１２と配線層３１、突起電極２３と配線層３２とがそれぞれ電気的に接続されている。 An insulating layer 30 is formed on the circuit board 10 and the semiconductor element 21 so as to cover the side surfaces of the protruding electrodes 12 and the protruding electrodes 23.
Further, a wiring layer 31 and a wiring layer 32 are patterned on the insulating layer 30, and the protruding electrode 12 and the wiring layer 31, and the protruding electrode 23 and the wiring layer 32 are electrically connected to each other.

尚、半導体素子２１の個数は、一つに限ることはなく、少なくとも一つの半導体素子２１が回路基板１０上に搭載されている。また、回路基板１０は、プリント基板またはフィルム基板であってもよい。また、回路基板１０の代わりに、半導体素子２１と同種または異種の半導体素子そのものを用い、半導体素子を積層させてもよい。   The number of semiconductor elements 21 is not limited to one, and at least one semiconductor element 21 is mounted on the circuit board 10. The circuit board 10 may be a printed board or a film board. Further, instead of the circuit board 10, a semiconductor element may be stacked using the same or different type of semiconductor element 21 as the semiconductor element 21.

また、絶縁層３０の材質は、加熱によって流動性を示す材料を用いる。具体的には、ポリイミド系樹脂、エポキシ系樹脂、アクリル系樹脂またはフェノール系樹脂の少なくとも一つを主成分とする樹脂である。   The insulating layer 30 is made of a material that exhibits fluidity when heated. Specifically, it is a resin whose main component is at least one of a polyimide resin, an epoxy resin, an acrylic resin, or a phenol resin.

また、突起電極１２及び突起電極２３の材質は、金（Ａｕ）、銅またはニッケル（Ｎｉ）の少なくとも一つを主成分とする金属である。
このような半導体装置１の実装構造によれば、回路基板１０の電極パッド１１、半導体素子２１の電極パッド２２から直接、突起電極１２、突起電極２３を引き出し、回路基板１０及び半導体素子２１の上層に形成した配線層３１、配線層３２に突起電極１２、突起電極２３をそれぞれ電気的に接続させているので、絶縁層３０内部に半導体素子２１と回路基板１０を接続する金属ワイヤを引き回す必要がなく、実装密度が向上する。 The material of the protruding electrode 12 and the protruding electrode 23 is a metal whose main component is at least one of gold (Au), copper, or nickel (Ni).
According to such a mounting structure of the semiconductor device 1, the protruding electrode 12 and the protruding electrode 23 are directly drawn out from the electrode pad 11 of the circuit board 10 and the electrode pad 22 of the semiconductor element 21, and the upper layer of the circuit board 10 and the semiconductor element 21. Since the protruding electrode 12 and the protruding electrode 23 are electrically connected to the wiring layer 31 and the wiring layer 32 formed in the above, it is necessary to route a metal wire for connecting the semiconductor element 21 and the circuit board 10 inside the insulating layer 30. In addition, the mounting density is improved.

次に、半導体装置１を製造する工程について説明する。最初に、半導体装置１を製造する基本的な原理を説明する。
図２は半導体装置の製造方法の基本原理を説明するフロー図である。先ず、図１に示した回路基板１０及び半導体素子２１に、スタッドバンプ法で用いるキャピラリを接近させる（ステップＳ１）。次に、スタッドバンプ法によって、回路基板１０上に配設された少なくとも一つの電極パッド１１上に、突起電極１２を形成し、半導体素子２１の少なくとも一つの電極パッド２２上に、突起電極１２と同じ高さの突起電極２３を形成する（ステップＳ２）。 Next, a process for manufacturing the semiconductor device 1 will be described. First, the basic principle for manufacturing the semiconductor device 1 will be described.
FIG. 2 is a flowchart for explaining the basic principle of the semiconductor device manufacturing method. First, a capillary used in the stud bump method is brought close to the circuit board 10 and the semiconductor element 21 shown in FIG. 1 (step S1). Next, a protruding electrode 12 is formed on at least one electrode pad 11 disposed on the circuit board 10 by a stud bump method, and the protruding electrode 12 is formed on at least one electrode pad 22 of the semiconductor element 21. The protruding electrode 23 having the same height is formed (step S2).

次に、回路基板１０及び半導体素子２１上に、金属膜が被覆された絶縁層３０を絶縁層３０の側から熱圧着する(ステップＳ３)。これにより、突起電極１２及び突起電極２３と金属膜とが電気的に接続する。   Next, the insulating layer 30 covered with the metal film is thermocompression bonded onto the circuit board 10 and the semiconductor element 21 from the insulating layer 30 side (step S3). Thereby, the protruding electrode 12 and the protruding electrode 23 are electrically connected to the metal film.

そして、金属膜をリソグラフィ法によってパターニングし、突起電極１２に電気的に接続された配線層３１と、突起電極２３に電気的に接続された配線層３２とを絶縁層３０上に形成する（ステップＳ４）。   Then, the metal film is patterned by a lithography method, and a wiring layer 31 electrically connected to the protruding electrode 12 and a wiring layer 32 electrically connected to the protruding electrode 23 are formed on the insulating layer 30 (step) S4).

このように、回路基板１０上に配設された電極パッド１１及び半導体素子２１の電極パッド２２に、スタッドバンプ法で同じ高さの突起電極１２、突起電極２３を形成する。
そして、回路基板１０及び半導体素子２１上に、絶縁層３０に金属膜が被膜された金属膜付絶縁層を加熱しながら熱圧着する。このとき、突起電極１２，２３は、金属膜付絶縁層の絶縁層３０を突き抜け、金属膜と接触する。そして、金属膜のパターニングを行い、絶縁層３０上に、突起電極１２と導通する配線層３１、突起電極２３と導通する配線層３２を形成させる。 As described above, the protruding electrodes 12 and the protruding electrodes 23 having the same height are formed on the electrode pads 11 disposed on the circuit board 10 and the electrode pads 22 of the semiconductor element 21 by the stud bump method.
Then, the insulating layer with metal film in which the insulating layer 30 is coated with the metal film is thermocompression-bonded on the circuit board 10 and the semiconductor element 21 while heating. At this time, the protruding electrodes 12 and 23 penetrate the insulating layer 30 of the insulating layer with a metal film and come into contact with the metal film. Then, the metal film is patterned to form on the insulating layer 30 a wiring layer 31 that is conductive with the protruding electrode 12 and a wiring layer 32 that is conductive with the protruding electrode 23.

続いて、上記の基本原理を基に、半導体装置１の具体的な製造方法について説明する。最初に、突起電極１２、突起電極２３の具体的な形成方法から説明する。
図３は突起電極形成工程の要部断面模式図である。 Next, a specific method for manufacturing the semiconductor device 1 will be described based on the above basic principle. First, a specific method for forming the protruding electrode 12 and the protruding electrode 23 will be described.
FIG. 3 is a schematic cross-sectional view of the relevant part in the bump electrode forming step.

先ず、図３（ａ）に示すように、回路基板１０上の電極パッド１１または半導体素子２１上の電極パッド２２に、キャピラリ４０を接近させる。ここで、キャピラリ４０の内部には、金属ワイヤ４１が備えられている。そして、予め、金属ワイヤ４１の一部を放電によって溶解し、キャピラリ４０の先端に、金属バンプ４２を形成させておく。   First, as shown in FIG. 3A, the capillary 40 is brought close to the electrode pad 11 on the circuit board 10 or the electrode pad 22 on the semiconductor element 21. Here, a metal wire 41 is provided inside the capillary 40. In advance, a part of the metal wire 41 is melted by discharge to form a metal bump 42 at the tip of the capillary 40.

尚、回路基板１０としては、半導体パッケージ用のプリント基板またはフレキシブル形状のフィルム基板等を用いる。また、回路基板１０に代えて、半導体素子を用いてもよい。回路基板１０に代えて用いる半導体素子は、半導体素子２１と同種のものでもよく、異種のものでもよい。また、回路基板１０に代えて用いる半導体素子は、半導体素子２１と形状が異なった半導体素子を用いてもよい。   As the circuit board 10, a printed circuit board for a semiconductor package or a flexible film board is used. Further, a semiconductor element may be used instead of the circuit board 10. The semiconductor element used in place of the circuit board 10 may be the same as or different from the semiconductor element 21. In addition, as a semiconductor element used instead of the circuit board 10, a semiconductor element having a shape different from that of the semiconductor element 21 may be used.

そして、図３（ｂ）に示すように、金属バンプ４２を回路基板１０の電極パッド１１上に押圧させ、超音波接合法によって、金属バンプ４２と電極パッド１１とを電気的に接続させる。   Then, as shown in FIG. 3B, the metal bumps 42 are pressed onto the electrode pads 11 of the circuit board 10, and the metal bumps 42 and the electrode pads 11 are electrically connected by an ultrasonic bonding method.

電極パッド１１上に金属バンプ４２を接合した後、図３（ｃ）に示すように、金属ワイヤ４１を上方に引張りながら、適度な位置で、金属ワイヤ４１を切断する。このような接合と切断を繰り返すことにより、図３（ｄ）に示すように、回路基板１０の電極パッド１１から複数の突起電極１２、半導体素子２１の電極パッド２２から複数の突起電極２３を形成させる。   After joining the metal bump 42 on the electrode pad 11, as shown in FIG. 3C, the metal wire 41 is cut at an appropriate position while pulling the metal wire 41 upward. By repeating such joining and cutting, a plurality of protruding electrodes 12 are formed from the electrode pads 11 of the circuit board 10 and a plurality of protruding electrodes 23 are formed from the electrode pads 22 of the semiconductor element 21 as shown in FIG. Let

このとき、突起電極１２及び突起電極２３の先端に生成する、それぞれの突起部１２ａ、突起部２３ａの長さを調整することによって、長さの異なる突起電極１２、突起電極２３をそれぞれ電極パッド１１、電極パッド２２上に形成する。   At this time, by adjusting the lengths of the projections 12a and 23a generated at the tips of the projection electrode 12 and the projection electrode 23, the projection electrodes 12 and 23 having different lengths are respectively connected to the electrode pads 11. And formed on the electrode pad 22.

そして、回路基板１０の電極パッド１１上に形成する突起電極１２は、半導体素子２１の電極パッド２２上に形成する突起電極２３より高くなるように形成し、突起電極１２と突起電極２３との高さが同じになるように形成する。   The protruding electrode 12 formed on the electrode pad 11 of the circuit board 10 is formed to be higher than the protruding electrode 23 formed on the electrode pad 22 of the semiconductor element 21, and the height between the protruding electrode 12 and the protruding electrode 23 is increased. Are formed to be the same.

或いは、キャピラリ４０の先端部に形成する金属バンプ４２の体積を調整することによって、突起電極１２と突起電極２３との高さを揃えてもよい。この場合、突起部１２ａ及び突起部２３ａの長さをより短くさせることができるので、後述する熱圧着の工程で、突起部１２ａ、突起部２３ａを樹脂に抗して押圧するときの突起部１２ａ及び突起部２３ａの歪曲を防止することが可能になる。   Alternatively, the height of the protruding electrode 12 and the protruding electrode 23 may be made uniform by adjusting the volume of the metal bump 42 formed at the tip of the capillary 40. In this case, since the length of the protrusion 12a and the protrusion 23a can be further shortened, the protrusion 12a when the protrusion 12a and the protrusion 23a are pressed against the resin in the thermocompression bonding process described later. And it becomes possible to prevent distortion of the projection part 23a.

このように、キャピラリ４０の内部から放出する金属ワイヤ４１の長さ、またはキャピラリ４０の先端に形成する金属バンプ４２の体積を調整することにより、突起電極１２、突起電極２３の長さを調節し、突起電極１２、突起電極２３の高さを均一にする。尚、突起電極１２及び突起電極２３の材質としては、金、銅またはニッケルの少なくとも一つを主成分とする金属を用いる。   As described above, the lengths of the protruding electrode 12 and the protruding electrode 23 are adjusted by adjusting the length of the metal wire 41 discharged from the inside of the capillary 40 or the volume of the metal bump 42 formed at the tip of the capillary 40. The heights of the protruding electrode 12 and the protruding electrode 23 are made uniform. In addition, as a material of the protruding electrode 12 and the protruding electrode 23, a metal having at least one of gold, copper, or nickel as a main component is used.

次に、絶縁層３０を回路基板１０、半導体素子２１に熱圧着させる工程について説明する。
図４は金属膜付絶縁層の熱圧着工程の要部断面模式図である。 Next, the process of thermocompression bonding the insulating layer 30 to the circuit board 10 and the semiconductor element 21 will be described.
FIG. 4 is a schematic cross-sectional view of the relevant part in the thermocompression bonding process of the insulating layer with metal film.

先ず、図４（ａ）に示すように、絶縁層３０の片面に、金属膜３３が被膜された板状の金属膜付絶縁層３４の絶縁層３０側を半導体素子２１及び回路基板１０に向けて対向させる。ここで絶縁層３０を構成する材料は、加熱によって流動性を示す樹脂であり、例えば、ポリイミド系樹脂、エポキシ系樹脂、アクリル系樹脂またはフェノール系樹脂の少なくとも一つを主成分とする樹脂である。金属膜３３の材質は、例えば、銅である。   First, as shown in FIG. 4A, the insulating layer 30 side of the plate-like insulating layer 34 with the metal film 33 coated with the metal film 33 on one side of the insulating layer 30 faces the semiconductor element 21 and the circuit board 10. To face each other. Here, the material constituting the insulating layer 30 is a resin that exhibits fluidity when heated, and is, for example, a resin whose main component is at least one of a polyimide resin, an epoxy resin, an acrylic resin, or a phenol resin. . The material of the metal film 33 is, for example, copper.

そして、図４（ｂ）に示すように、金属膜付絶縁層３４を加熱した後、回路基板１０と金属膜付絶縁層３４との平行状態を維持させたまま、金属膜付絶縁層３４を半導体素子２１及び回路基板１０に対して熱圧着させる。   Then, as shown in FIG. 4B, after heating the insulating layer 34 with the metal film, the insulating layer 34 with the metal film is maintained while maintaining the parallel state between the circuit board 10 and the insulating layer 34 with the metal film. The semiconductor element 21 and the circuit board 10 are thermocompression bonded.

上述したように、絶縁層３０は、樹脂によって構成され、加熱によって絶縁層３０が軟化し、流動性を示す。また、突起電極１２及び突起電極２３の先端には、鋭利な形状の突起部１２ａ、突起部２３ａがそれぞれ形成されている。従って、熱圧着によって、突起電極１２及び突起電極２３を樹脂に抗して押圧させたとしても、突起電極１２、突起電極２３が容易に絶縁層３０の間を突き抜け、突起電極１２及び突起電極２３の側面が樹脂によって被覆される。そして、熱圧着後、突起部１２ａ及び突起部２３ａが金属膜３３と接触し、突起部１２ａ及び突起部２３ａが熱圧着によって金属膜３３に押圧される。   As described above, the insulating layer 30 is made of resin, and the insulating layer 30 is softened by heating and exhibits fluidity. In addition, sharp projections 12a and 23a are formed at the tips of the projection electrode 12 and the projection electrode 23, respectively. Therefore, even if the protruding electrode 12 and the protruding electrode 23 are pressed against the resin by thermocompression bonding, the protruding electrode 12 and the protruding electrode 23 easily penetrate between the insulating layers 30, and the protruding electrode 12 and the protruding electrode 23. The side surface of is covered with resin. Then, after thermocompression bonding, the protrusion 12a and the protrusion 23a come into contact with the metal film 33, and the protrusion 12a and the protrusion 23a are pressed against the metal film 33 by thermocompression bonding.

そして、絶縁層３０の温度が常温に戻った後においても、突起部１２ａ及び突起部２３ａが金属膜３３に押圧された状態が保持され、突起電極１２及び突起電極２３と金属膜３３との電気的な導通が確保される。尚、スタッドバンプ法では、突起部１２ａ、突起部２３ａの先端形状に軽微な相違が生じることもあるが、突起部１２ａ、突起部２３ａを構成する金属の延性、可塑性によって、押圧したときに突起部１２ａ、突起部２３ａの先端が容易に変形するので、問題なく全ての突起電極１２及び突起電極２３と金属膜３３との導通を確保することができる。   Even after the temperature of the insulating layer 30 returns to room temperature, the state in which the protrusions 12 a and the protrusions 23 a are pressed by the metal film 33 is maintained, and the electric Continuity is ensured. In the stud bump method, a slight difference may occur in the tip shapes of the protrusion 12a and the protrusion 23a. However, the protrusions when pressed due to the ductility and plasticity of the metal constituting the protrusion 12a and the protrusion 23a. Since the tips of the portion 12a and the protruding portion 23a are easily deformed, conduction between all the protruding electrodes 12 and the protruding electrodes 23 and the metal film 33 can be ensured without any problem.

また、熱圧着では絶縁層３０を構成する樹脂が流動性を示し、半導体素子２１の側面、回路基板１０の表面に充分に回りこむので、絶縁層３０を半導体素子２１、回路基板１０に抗するように圧着させても、金属膜３３が特定の場所で凹凸を形成することなく、平坦形状を維持した金属膜３３が絶縁層３０上に形成される。   Further, in the thermocompression bonding, the resin constituting the insulating layer 30 exhibits fluidity and sufficiently wraps around the side surface of the semiconductor element 21 and the surface of the circuit board 10, so that the insulating layer 30 resists the semiconductor element 21 and the circuit board 10. Thus, even if it press-fits, the metal film 33 which maintained flat shape is formed on the insulating layer 30, without forming the unevenness | corrugation in the specific place.

次に、図４（ｃ）に示すように、金属膜付絶縁層３４の金属膜３３上にレジスト３５を塗布する。そして、リソグラフィ法によって金属膜３３のパターニングを行い、突起電極１２及び突起電極２３に、それぞれ電気的に接続される配線層を絶縁層３０上に形成する。以上のような工程で、図１に示す半導体装置１が製造される。   Next, as shown in FIG. 4C, a resist 35 is applied on the metal film 33 of the insulating layer with metal film 34. Then, the metal film 33 is patterned by a lithography method, and wiring layers that are electrically connected to the bump electrode 12 and the bump electrode 23 are formed on the insulating layer 30. The semiconductor device 1 shown in FIG. 1 is manufactured through the processes as described above.

（付記１） 回路基板上に搭載された、少なくとも一つの半導体素子と、
前記回路基板上に配設された少なくとも一つの電極上に形成された第１の突起電極と、
前記半導体素子の少なくとも一つの電極上に形成された第２の突起電極と、
前記第１の突起電極及び前記第２の突起電極の側面を被覆し、前記回路基板及び前記半導体素子上に形成された絶縁層と、
前記絶縁層上に配設され、前記第１の突起電極と電気的に接続された第１の配線層及び前記第２の突起電極と電気的に接続された第２の配線層と、
を備え、前記第１の突起電極と前記第２の突起電極の高さが均一であることを特徴とする半導体装置。 (Appendix 1) At least one semiconductor element mounted on a circuit board;
A first protruding electrode formed on at least one electrode disposed on the circuit board;
A second protruding electrode formed on at least one electrode of the semiconductor element;
Covering the side surfaces of the first protruding electrode and the second protruding electrode, and an insulating layer formed on the circuit board and the semiconductor element;
A first wiring layer disposed on the insulating layer and electrically connected to the first protruding electrode; and a second wiring layer electrically connected to the second protruding electrode;
The semiconductor device is characterized in that the first protruding electrode and the second protruding electrode have a uniform height.

（付記２） 前記回路基板に代えて、前記半導体素子と同種または異種の半導体素子を用いることを特徴とする付記１記載の半導体装置。
（付記３） 前記絶縁層の材質がポリイミド系樹脂、エポキシ系樹脂、アクリル系樹脂、フェノール系樹脂の少なくとも一つを主成分とする樹脂であることを特徴とする付記１記載の半導体装置。 (Additional remark 2) It replaces with the said circuit board, and uses the same kind or different kind of semiconductor element as the said semiconductor element, The semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The semiconductor device of Additional remark 1 characterized by the material of the said insulating layer being resin which has at least one of polyimide resin, epoxy resin, acrylic resin, and phenol resin as a main component.

（付記４） 前記第１の突起電極及び前記第２の突起電極の材質が金、銅、ニッケルの少なくとも一つを主成分とする金属であることを特徴とする付記１記載の半導体装置。
（付記５） スタッドバンプ法によって、回路基板上に配設された電極上に第１の突起電極を形成し、半導体素子の電極上に、前記第１の突起電極と同じ高さの第２の突起電極を形成する工程と、
前記回路基板及び前記半導体素子の上に、金属膜が被覆された絶縁層を前記絶縁層の側から熱圧着する工程と、
前記金属膜をパターニングし、前記第１の突起電極に電気的に接続された第１の配線層と、前記第２の突起電極に電気的に接続された第２の配線層とを前記絶縁層上に形成する工程と、
を有することを特徴とする半導体装置の製造方法。 (Additional remark 4) The semiconductor device of Additional remark 1 characterized by the material of said 1st protruding electrode and said 2nd protruding electrode being a metal which has at least one of gold, copper, and nickel as a main component.
(Supplementary Note 5) A first bump electrode is formed on an electrode disposed on a circuit board by a stud bump method, and a second bump having the same height as the first bump electrode is formed on an electrode of a semiconductor element. Forming a bump electrode;
A step of thermocompression bonding an insulating layer coated with a metal film on the circuit board and the semiconductor element from the side of the insulating layer;
The metal film is patterned to form a first wiring layer electrically connected to the first protruding electrode and a second wiring layer electrically connected to the second protruding electrode. Forming on top;
A method for manufacturing a semiconductor device, comprising:

（付記６） 前記スタッドバンプ法によって、前記回路基板上に配設された前記電極上に前記第１の突起電極を形成し、前記半導体素子の前記電極上に、前記第１の突起電極と同じ高さの前記第２の突起電極を形成する工程においては、前記スタッドバンプ法に用いるキャピラリ内部から放出する金属ワイヤの長さまたは前記キャピラリの先端に形成する金属バンプの体積を調整することにより、前記第１の突起電極及び前記第２の突起電極の高さを同じにすることを特徴とする付記５記載の半導体装置の製造方法。   (Appendix 6) The first bump electrode is formed on the electrode disposed on the circuit board by the stud bump method, and the same as the first bump electrode on the electrode of the semiconductor element. In the step of forming the second protruding electrode having a height, by adjusting the length of the metal wire discharged from the inside of the capillary used for the stud bump method or the volume of the metal bump formed on the tip of the capillary, 6. The method of manufacturing a semiconductor device according to appendix 5, wherein the first protruding electrode and the second protruding electrode have the same height.

（付記７） 前記回路基板に代えて、前記半導体素子と同種または異種の半導体素子を用いることを特徴とする付記５または６記載の半導体装置の製造方法。
（付記８） 前記絶縁層の材質がポリイミド系樹脂、エポキシ系樹脂、アクリル系樹脂、フェノール系樹脂の少なくとも一つを主成分とする樹脂であることを特徴とする付記５記載の半導体装置の製造方法。 (Additional remark 7) It replaces with the said circuit board and uses the same kind or different kind of semiconductor element as the said semiconductor element, The manufacturing method of the semiconductor device of Additional remark 5 or 6 characterized by the above-mentioned.
(Additional remark 8) The material of the said insulating layer is resin which has at least one of polyimide resin, epoxy resin, acrylic resin, and phenol resin as a main component, The manufacturing of the semiconductor device of Additional remark 5 characterized by the above-mentioned Method.

（付記９） 前記第１の突起電極及び前記第２の突起電極の材質が金、銅、ニッケルの少なくとも一つを主成分とする金属であることを特徴とする付記５または６記載の半導体装置の製造方法。   (Supplementary note 9) The semiconductor device according to supplementary note 5 or 6, wherein a material of the first protruding electrode and the second protruding electrode is a metal containing at least one of gold, copper, and nickel as a main component. Manufacturing method.

半導体装置の要部断面模式図である。It is a principal part cross-sectional schematic diagram of a semiconductor device. 半導体装置の製造方法の基本原理を説明するフロー図である。It is a flowchart explaining the basic principle of the manufacturing method of a semiconductor device. 突起電極形成工程の要部断面模式図である。It is a principal part cross-sectional schematic diagram of a protruding electrode formation process. 金属膜付絶縁層の熱圧着工程の要部断面模式図である。It is a principal part cross-sectional schematic diagram of the thermocompression-bonding process of an insulating layer with a metal film.

符号の説明Explanation of symbols

１ 半導体装置
１０ 回路基板
１１，２２ 電極パッド
１２，２３ 突起電極
１２ａ，２３ａ 突起部
２０ 接着層
２１ 半導体素子
３０ 絶縁層
３１，３２ 配線層
３３ 金属膜
３４ 金属膜付絶縁層
３５ レジスト
４０ キャピラリ
４１ 金属ワイヤ
４２ 金属バンプ DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Circuit board 11, 22 Electrode pad 12, 23 Protruding electrode 12a, 23a Protruding part 20 Adhesive layer 21 Semiconductor element 30 Insulating layer 31, 32 Wiring layer 33 Metal film 34 Insulating layer with metal film 35 Resist 40 Capillary 41 Metal Wire 42 Metal bump

Claims (6)

回路基板上に搭載された、少なくとも一つの半導体素子と、
前記回路基板上に配設された少なくとも一つの電極上に形成された第１の突起電極と、
前記半導体素子の少なくとも一つの電極上に形成された第２の突起電極と、
前記第１の突起電極及び前記第２の突起電極の側面を被覆し、前記回路基板及び前記半導体素子上に形成された絶縁層と、
前記絶縁層上に配設され、前記第１の突起電極と電気的に接続された第１の配線層及び前記第２の突起電極と電気的に接続された第２の配線層と、
を備え、前記第１の突起電極と前記第２の突起電極の高さが均一であることを特徴とする半導体装置。 At least one semiconductor element mounted on a circuit board;
A first protruding electrode formed on at least one electrode disposed on the circuit board;
A second protruding electrode formed on at least one electrode of the semiconductor element;
Covering the side surfaces of the first protruding electrode and the second protruding electrode, and an insulating layer formed on the circuit board and the semiconductor element;
A first wiring layer disposed on the insulating layer and electrically connected to the first protruding electrode; and a second wiring layer electrically connected to the second protruding electrode;
The semiconductor device is characterized in that the first protruding electrode and the second protruding electrode have a uniform height. 前記回路基板に代えて、前記半導体素子と同種または異種の半導体素子を用いることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a semiconductor element of the same kind or different kind from the semiconductor element is used in place of the circuit board. 前記絶縁層の材質がポリイミド系樹脂、エポキシ系樹脂、アクリル系樹脂、フェノール系樹脂の少なくとも一つを主成分とする樹脂であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the material of the insulating layer is a resin whose main component is at least one of a polyimide resin, an epoxy resin, an acrylic resin, and a phenol resin. 前記第１の突起電極及び前記第２の突起電極の材質が金、銅、ニッケルの少なくとも一つを主成分とする金属であることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a material of the first protruding electrode and the second protruding electrode is a metal having at least one of gold, copper, and nickel as a main component. スタッドバンプ法によって、回路基板上に配設された電極上に第１の突起電極を形成し、半導体素子の電極上に、前記第１の突起電極と同じ高さの第２の突起電極を形成する工程と、
前記回路基板及び前記半導体素子の上に、金属膜が被覆された絶縁層を前記絶縁層の側から熱圧着する工程と、
前記金属膜をパターニングし、前記第１の突起電極に電気的に接続された第１の配線層と、前記第２の突起電極に電気的に接続された第２の配線層とを前記絶縁層上に形成する工程と、
を有することを特徴とする半導体装置の製造方法。 A first bump electrode is formed on an electrode disposed on a circuit board by a stud bump method, and a second bump electrode having the same height as the first bump electrode is formed on an electrode of a semiconductor element. And a process of
A step of thermocompression bonding an insulating layer coated with a metal film on the circuit board and the semiconductor element from the side of the insulating layer;
The metal film is patterned to form a first wiring layer electrically connected to the first protruding electrode and a second wiring layer electrically connected to the second protruding electrode. Forming on top;
A method for manufacturing a semiconductor device, comprising: 前記スタッドバンプ法によって、前記回路基板上に配設された前記電極上に前記第１の突起電極を形成し、前記半導体素子の前記電極上に、前記第１の突起電極と同じ高さの前記第２の突起電極を形成する工程においては、前記スタッドバンプ法に用いるキャピラリ内部から放出する金属ワイヤの長さまたは前記キャピラリの先端に形成する金属バンプの体積を調整することにより、前記第１の突起電極及び前記第２の突起電極の高さを同じにすることを特徴とする請求項５記載の半導体装置の製造方法。   The first bump electrode is formed on the electrode disposed on the circuit board by the stud bump method, and the first bump electrode having the same height as the first bump electrode is formed on the electrode of the semiconductor element. In the step of forming the second protruding electrode, the length of the metal wire discharged from the inside of the capillary used for the stud bump method or the volume of the metal bump formed on the tip of the capillary is adjusted to adjust the first bump electrode. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the height of the protruding electrode and the second protruding electrode are the same.
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