JP2016009819A - Power semiconductor module and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor module that can be miniaturized, enhanced in productivity and reduced in cost.SOLUTION: A projecting portion 8e which is electrically connected to the back surface electrode of a semiconductor element 5 is formed in an area out of an area having the semiconductor element 5 disposed therein on the same plane as a surface of a first insulation substrate 8 on which the semiconductor element 5 is disposed, lands 1a, 1b are provided at the positions corresponding to the surface electrode of the semiconductor element 5 and the projection portion 8e on one surface of a confronting second insulation substrate 1, the surface electrode of the semiconductor element 5 and the land 1a are connected to each other by a first joint portion, and the projection portion 8e and the land 1b are connected to each other by a second joint portion.

Description

  The present invention relates to a power semiconductor module and a method for manufacturing the same, and particularly to a technique for reducing the size of the power semiconductor module.

  In a conventional power semiconductor module, a semiconductor chip on an insulating substrate constituting a power substrate, for example, a power chip such as an IGBT chip or a diode chip, and an external electrode are soldered or wire-bonded in a semiconductor package. Sealed with mold resin or the like.

  In a conventional semiconductor package, solder bumps are made on a glass epoxy substrate and the solder is remelted to connect with wiring on the semiconductor chip. However, the height of the semiconductor chip differs from that on the substrate. For this wiring, it was necessary to perform wire bonding separately.

  In such an insulating substrate on which a semiconductor chip is mounted, in order to reduce the size of the module, improve the productivity, and reduce the cost, a technique for collectively wiring the semiconductor chip having a step and the substrate is required. .

  On the other hand, in Patent Document 1 and Patent Document 2, for example, by arranging solder balls or solder bumps having different heights on the chip and the substrate, collective wiring between the chip having a step and the substrate is performed. Techniques that enable it are disclosed.

  In Patent Document 3, the front surface of a semiconductor chip is bump-bonded to a wiring pattern on a substrate connected to an external electrode, and the back surface is bonded to the semiconductor chip and the substrate using a lead frame having a shape corresponding to a step instead of wire bonding. A technique that enables collective wiring is disclosed.

JP 2008-104348 A (paragraph 0059, FIG. 7) JP2013-140870A (paragraph 0019, FIG. 2) JP 2001-057408 A (paragraph 0067, FIG. 2)

  However, in Patent Document 1, since it is difficult to produce solder bumps having different heights by printing / reflowing solder paste, it is necessary to prepare and arrange solder balls having different sizes. There was a problem that the process was complicated.

  In Patent Document 2, it is necessary to use a solder bump in which a copper core having a melting point higher than that of the solder is included in the solder, and there is a problem that stable supply is difficult.

  In Patent Document 3, the front surface of a semiconductor chip is bump-bonded to a pattern on a substrate connected to an external electrode, and the back surface uses a lead frame instead of wire bonding. However, tolerances for chip die bond and lead frame height tolerances are used. However, there was a problem that the production efficiency was lowered.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a power semiconductor module capable of improving productivity and reducing costs while reducing the size of the power semiconductor module. And

  In the power semiconductor module according to the present invention, a protrusion electrically connected to the back electrode of the semiconductor element is formed in a region other than the region where the semiconductor element is installed on the same surface as the surface where the semiconductor element is installed. On the surface of the first insulating substrate and the surface of the first insulating substrate facing the surface on which the semiconductor element is installed and the protrusion is formed, the inner side is located at a position corresponding to the surface electrode and the protrusion of the semiconductor element. A second insulating substrate having a terminal formed thereon and an external terminal formed on the other surface connected to the internal terminal via a through hole; a surface electrode of the semiconductor element on the first insulating substrate; and a surface A first joint connected to an internal terminal of the second insulating substrate at a position corresponding to the electrode, a protrusion of the first insulating substrate, and a second insulation at a position corresponding to the protrusion. The second terminal connected to the inner terminal of the substrate It is obtained by a coupling portion.

  In the method for manufacturing a power semiconductor module according to the present invention, the semiconductor element is disposed on one surface of the first insulating substrate, and is on the same surface as the surface on which the semiconductor element is installed, except for the region where the semiconductor element is installed. Forming a protrusion electrically connected to the back electrode of the semiconductor element in the region, and a second insulating substrate of the first insulating substrate facing the surface on which the semiconductor element is provided and the protrusion is formed A step of forming solder bumps on the inner side terminals respectively formed at positions corresponding to the surface electrodes and protrusions of the semiconductor element on one surface of the semiconductor element; and the surface electrode of the semiconductor element of the first insulating substrate; Overlay the solder bump on the inner terminal of the second insulating substrate provided at the position corresponding to the surface electrode, and provide at the end corresponding to the protruding portion of the first insulating substrate and the position corresponding to the protruding portion. Of the second insulating substrate formed Overlapping the solder bumps on the terminals, after heating and melting the solder bumps, it is intended to include a process of solder joining collectively by cooling.

  According to the present invention, the semiconductor element and the protrusion electrically connected to the back electrode of the semiconductor element are provided on one surface of the first insulating substrate, and the surface of the semiconductor element is provided on the one surface of the second insulating substrate facing each other. A configuration in which internal terminals are provided at positions corresponding to the electrodes and the protrusions, the surface electrodes of the semiconductor element are connected to the corresponding internal terminals, and the protrusions are connected to the corresponding internal terminals; Therefore, even if there is a step in the region other than the region where the semiconductor element is arranged and the region where the semiconductor element is arranged on the surface of the first insulating substrate, it is possible to perform collective wiring without using wire bonding. it can. Further, the package can be downsized in the height direction as compared with the case of using wire bonding.

It is sectional drawing which shows the structure of the power semiconductor module by Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing process of the power semiconductor module by Embodiment 1 of this invention. It is a front view which shows a part of example of the printing mask used for manufacture of the power semiconductor module by Embodiment 1 of this invention. It is sectional drawing explaining an example of the manufacturing method of the power semiconductor module by Embodiment 1 of this invention. It is sectional drawing which shows the structure of the power semiconductor module by Embodiment 2 of this invention. It is a perspective view which shows the example of the projection part which is a part of structure of the power semiconductor module by Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing process of the power semiconductor module by Embodiment 2 of this invention. It is sectional drawing which shows the structure of the power semiconductor module by Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing process of the power semiconductor module by Embodiment 3 of this invention.

Embodiment 1 FIG.
1 is a cross-sectional view of a power semiconductor module 100 according to Embodiment 1 of the present invention. As shown in FIG. 1, the power semiconductor module 100 includes a semiconductor chip 5 as a semiconductor element, a first insulating substrate 8 on which the semiconductor chip 5 is mounted, and the semiconductor chip 5 and the first through the solder joints 4a and 4b. A second insulating substrate 1 connected to one insulating substrate 8 and a sealing resin portion 6 that covers the semiconductor chip 5, the first insulating substrate 8, and the like on the second insulating substrate 1.

  As the semiconductor chip 5 (for example, an external dimension of 10 mm × 10 mm), a semiconductor such as an IC (Integrated Circuit) or a diode, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or the like. A power semiconductor may be used. Here, Si IGBT was used.

  As the first insulating substrate 8 (for example, an outer dimension of 18 mm × 18 mm), an aluminum nitride (AlN) substrate that is a ceramic substrate is used. On the first insulating substrate 8, the semiconductor chip 5 is die-bonded by sheet solder. In FIG. 1, only one semiconductor chip 5 is provided, but a plurality of chips are arranged in series or in parallel as required.

  As the second insulating substrate 1 (outer dimension 20 mm × 20 mm), a glass epoxy substrate in which a glass fiber cloth is impregnated with an epoxy resin is used. On the surface of the second insulating substrate 1, lands 1a as internal terminals that are electrically connected to the surface electrodes of the semiconductor chip 5 via solder joints 4a as first joints, and second A land 1b is provided as an internal terminal that is electrically connected to the first insulating substrate 8 via a solder joint 4b as a joint.

  The land 1a is connected to the front surface electrode of the semiconductor chip 5 via the solder joint 4a, and the land 1b is connected to the back surface electrode of the semiconductor chip 5 via the solder joint 4b. The land 1a and the land 1b of the second insulating substrate 1 are electrically connected to the external electrode 10 as an external terminal provided on the back surface of the second insulating substrate 1 through a through hole (not shown). It is connected.

  The first insulating substrate 8 and the second insulating substrate 1 are an AlN substrate and a glass epoxy substrate, respectively. However, if the insulating property is obtained and a land on which the solder gets wet like Cu can be formed, this is possible. It is not limited to this, and other insulating substrates may be used. As the ceramic substrate, for example, an insulating substrate base material such as alumina, silicon carbide (SiC), or silicon nitride (SiN) may be used.

  The lands 1a and 1b only have to be able to wet the solder, and the outermost surface is not limited to Cu, but may be any metal such as Sn, Au, or Ag. Moreover, the surface and the back surface of the semiconductor chip 5 may be any metal that can wet the solder, and the outermost surface may be Sn, Au, Ag, or the like.

  The sealing resin portion 6 is formed by potting resin so as to cover the solder joint portions 4a and 4b connected to the semiconductor chip 5, the first insulating substrate 8, and the lands 1a and 1b of the second insulating substrate 1, and is insulated. Seal. The sealing resin portion 6 is not limited to potting resin and may be liquid as long as insulation is ensured and the space between the second insulating substrate 1 and the first insulating substrate 8 can be filled with resin. A gel or the like may be used. Further, it may be sealed by transfer molding using a mold resin.

  Next, a method for manufacturing the power semiconductor module 100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing a manufacturing process of power semiconductor module 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 2A1, the second insulating substrate 1 is provided with lands 1a and 1b (Cu, φ1 mm) on the front surface and external electrodes 10 on the back surface. In order to form solder bumps on 1b, solder pastes 30a and 30b (for example, Sn—Ag—Cu solder) are printed using the mask 2a. The solder pastes 30a and 30b are not limited to Sn—Ag—Cu solder, but may also be one added with Sb or CuSn solder.

  Thus, the solder paste 30a for soldering to the front surface electrode of the semiconductor chip 5 and the solder paste for soldering to the wiring on the first insulating substrate 8 electrically connected to the back surface electrode of the semiconductor chip 5 30b can be formed simultaneously.

  Subsequently, as shown in FIG. 2 (b1), by heating the second insulating substrate 1, the printed solder pastes 30a and 30b are melted, and then cooled, thereby cooling the solder bumps 40a and 40b. Become.

  In parallel with the above steps, as shown in FIG. 2 (a2), the first insulating substrate 8 is provided on the same surface of the first insulating substrate 8 on the side where the semiconductor chip 5 is disposed. A solder paste 31b (Sn—Ag—Cu) is formed using a mask 2b on a land (not shown) electrically connected to the back surface electrode by a wiring pattern at a position corresponding to the land 1b of the second insulating substrate 1. Solder) is printed.

  Subsequently, as shown in FIG. 2 (b2), the semiconductor chip 5 is die-bonded to the first insulating substrate 8 by sheet solder. When die bonding is performed, the printed insulating paste 31b is melted by heating the first insulating substrate 8, and then the solder bumps 41b are formed by cooling.

  Here, it is preferable that the height of the solder bump 41 b is equal to or higher than the height of the semiconductor chip 5 and is equal to or lower than the value obtained by adding the height of the solder bump 40 a to the height of the semiconductor chip 5. When the height of the solder bump 41b is lower than the height of the semiconductor chip 5, the solder joint portion 4b (FIG. 2D) cannot be joined, or even if it can be joined, a sufficient current capacity cannot be obtained. If the height of the solder bump 41b is higher than the value obtained by adding the height of the solder bump 40a to the height of the semiconductor chip 5, the solder joint 4a cannot be joined or even if it can be joined, a sufficient current capacity can be obtained. I can't.

  FIG. 3 shows an example of a mask 2a used for printing the solder paste 30a, 30b on the second insulating substrate 1 or a mask 2b used for printing the solder paste 31b on the first insulating substrate 8. Indicates. In FIG. 3A and FIG. 3B, the diameter of the opening 2c is different.

  In order for the solder joints 4a and 4b of FIG. 1 to obtain a sufficient current capacity, the current capacity can be controlled by selecting the diameter of the opening 2c. Further, for example, even when the diameter of the opening 2c in FIG. 3A is required, as shown in FIG. 3B, the opening 2c having a smaller diameter than the opening 2c in FIG. A plurality of masks 2a can also be provided, and in this case, there is an effect that generation of voids in the solder joint portion can be reduced.

  The lands 1a and 1b formed on the second insulating substrate 1 have the same number of openings as the center of the mask 2a, and the diameter of the lands 1a and 1b is within ± 20% of the diameter of the opening of the mask 2a. It is desirable that

  Although the die bonding of the semiconductor chip 5 is performed by plate soldering, an opening for die bonding may be provided at the position of the mask 2b corresponding to the chip arrangement position, and die bonding may be performed using a solder paste.

  Further, the solder used for die bonding of the semiconductor chip 5 is a solder having a melting point higher than that of the solder bumps 40a, 40b, 41b, even when a plate solder is used or a solder paste is used. As a result, even if the solder bumps 40a, 40b, and 41b are heated to a temperature at which the solder bumps 40a, 40b, and 41b are melted in the subsequent process, the semiconductor chip 5 is prevented from being remelted and the semiconductor chip 5 is displaced or rotated Can be prevented.

  Next, as shown in FIG. 2 (c), the surface on which the solder bumps 40a and 40b of the second insulating substrate 1 shown in FIG. 2 (b1) are formed, and the first insulation shown in FIG. 2 (b2). The surface of the substrate 8 on which the solder bumps 41b are formed faces each other.

  The solder bumps 40b of the second insulating substrate 1 become the solder bumps 41b of the first insulating substrate 8 so that the solder bumps 40a of the second insulating substrate 1 overlap the surface of the semiconductor chip 5 of the first insulating substrate 8. After positioning so as to overlap, the first insulating substrate 8 and the second insulating substrate 1 are heated.

  By heating until the solder bumps 40a, 40b, and 41b are remelted, the solder bump 40a of the second insulating substrate 1 is joined to the surface electrode of the semiconductor chip 5 of the first insulating substrate 8, and the second The solder bumps 40 b of the insulating substrate 1 are joined to the solder bumps 41 b of the first insulating substrate 8.

  Thereafter, by cooling, as shown in FIG. 2D, the solder bump 40a becomes the solder joint portion 4a, and the land 1a of the second insulating substrate 1 passes through the solder joint portion 4a. Electrically connected to the surface electrode.

  The solder bumps 40b and the solder bumps 41b become solder joints 4b, and the lands 1b of the second insulating substrate 1 are electrically connected to the back electrodes of the semiconductor chip 5 on the first insulating substrate 8 ( (Not shown) and electrically connected.

  As shown in FIG. 4, when the solder bump 41b of the first insulating substrate is formed, a heat resistant resist 9 that does not melt even at the solder melting temperature is formed in advance around the position where the solder bump 41b is disposed. By doing so, the solder bump 41b melted by heating can be selectively wetted in the region 8a where the resist 9 is not formed, and the positional accuracy of the solder bump 41b can be improved (FIG. 4A).

  Further, by forming the protrusions 8b (FIG. 4B) or recesses in advance at the positions where the solder bumps 41b are arranged, the solder bumps 41b melted by heating are selectively applied to the protrusions 8b or recesses. The position accuracy of the solder bump 41b may be improved by getting wet.

  In addition, by previously forming a region 8c having a different surface roughness around the position where the solder bump 41b is arranged, the solder bump 41b melted by heating is selectively wetted in the region 8d having good wettability. Thus, the positional accuracy of the solder bump 41b may be improved.

  Furthermore, in each of the cases shown in FIGS. 4A to 4C, a pattern may be formed with a metal having excellent solder wettability such as Au, Ag, Cu only at the position where the solder bump 41b is arranged.

  Finally, as shown in FIG. 2E, the semiconductor chip 5, the first insulating substrate 8, and the lands 1a and 1b between the first insulating substrate 8 and the second insulating substrate 1 and the solder joints. A sealing resin portion 6 that covers 4a and 4b is formed of potting resin.

  Through the above process, wiring on a semiconductor chip and wiring on a substrate having different heights can be performed simultaneously without using wire bonding, which not only simplifies the manufacturing process but also enables vertical wiring for wire looping. A space in the direction is not necessary, and a miniaturized package can be provided.

  As described above, in the power semiconductor module 100 according to the first embodiment of the present invention, the first insulating substrate 8 and the second insulating substrate 1 are in the region where the semiconductor chip 5 of the first insulating substrate 8 is disposed. Is connected to the surface electrode of the semiconductor chip 5 of the first insulating substrate 8 and the land 1a of the second insulating substrate 1 by a solder joint portion 4a formed from a solder bump 40a provided on the land 1a. In a region other than the region where the semiconductor chip 5 of the insulating substrate 8 is disposed, the land of the first insulating substrate 8 connected to the back electrode of the semiconductor chip 5 by the wiring pattern, and the land 1b of the second insulating substrate 1. Are connected to the lands of the first insulating substrate 8 by the solder joints 4b formed from the solder bumps 41b and the solder bumps 40b on the lands 1b. Even if there is a step in the region other than the region to place the region and the semiconductor chip disposing a semiconductor chip on the surface of, without using the wire bonding can be collectively wiring. Further, the package can be downsized in the height direction as compared with the case of using wire bonding.

  In addition, by joining the solder bumps, the allowable range for the intersection of heights can be expanded, and the design margin can be ensured. Furthermore, the self-correction of the positional deviation is possible due to the tension between the solders.

  In addition, by performing batch wiring by printing / reflowing solder paste, productivity can be improved and costs can be reduced.

Embodiment 2. FIG.
In the first embodiment, in the region other than the region where the semiconductor chip 5 is disposed on the first insulating substrate 8, the second insulating substrate 1 and the first insulating substrate 8 are connected only by the solder joint 4b. In the second embodiment, the case where the first insulating substrate 8 is connected through a protruding portion will be described.

  FIG. 5 is a cross-sectional view of a power semiconductor module 200 according to Embodiment 2 of the present invention. As shown in FIG. 5, the first insulating substrate 8 is provided with a columnar protrusion 8e made of Cu. One end of the protruding portion 8 e is electrically connected to the land 1 b of the second insulating substrate 1 by the solder joint portion 4 c, and the other end is connected to the back electrode of the semiconductor chip 5 disposed on the first insulating substrate 8. Electrically connected.

  The protrusion 8e is not limited to the cylindrical protrusion 8e (FIGS. 5 and 6A) as long as the protrusion 8e can be bonded to the solder joint 4c of the second insulating substrate 1. It may be a polygonal columnar shape such as a square columnar shape (FIG. 6B), or a polygonal columnar projection 8e such as a conical shape (FIG. 6C) or a triangular pyramid shape (FIG. 6D).

  The protrusion 8e is not limited to Cu as long as it is a metal that gets wet with the solder, and may be made of metal such as Sn, Au, or Ag.

  Other configurations are the same as those of the power semiconductor module 100 of the first embodiment shown in FIG. 1, and the same portions are denoted by the same reference numerals and the description thereof is omitted.

  Next, a method for manufacturing the power semiconductor module 200 according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 7 is a sectional view showing a manufacturing process of the power semiconductor module 200 according to the second embodiment of the present invention.

  First, as in the first embodiment, as shown in FIG. 7 (a1), the second insulating substrate 1 is provided with lands 1a and 1b (Cu, φ1 mm) on the front surface and external electrodes 10 on the rear surface. In order to form solder bumps on the lands 1a and 1b on the surface, solder pastes 30a and 30b (for example, Sn—Ag—Cu solder) are printed using the mask 2a. The solder pastes 30a and 30b are not limited to Sn—Ag—Cu solder, but may also be one added with Sb or CuSn solder.

  Thus, the solder paste 30a for solder bonding to the front surface electrode of the semiconductor chip 5 and the protrusion 8e on the first insulating substrate 8 electrically connected to the back electrode of the semiconductor chip 5 are solder bonded. The solder paste 30b can be formed simultaneously.

  Subsequently, as in the first embodiment, as shown in FIG. 7B1, by heating the second insulating substrate 1, the printed solder pastes 30a and 30b are melted and then cooled. Thus, the solder bumps 40a and 40b are obtained.

  In parallel with the above steps, as shown in FIG. 7A2, a protrusion 8e is formed at a position corresponding to the land 1b of the second insulating substrate 1 of the first insulating substrate 8. As a method for forming the protrusion 8e, brazing or casting is selected depending on the type of the insulating substrate, but a wire bump is formed on a land (not shown) electrically connected to the back surface electrode of the semiconductor chip 5 by a wiring pattern. May be formed. The wire at that time may be Au, Cu, or the like as long as the metal wets the solder.

  Here, it is preferable that the height of the protruding portion 8 e is equal to or higher than the height of the semiconductor chip 5 and is equal to or lower than the value obtained by adding the height of the solder bump 40 a to the height of the semiconductor chip 5. When the height of the protrusion 8e is lower than the height of the semiconductor chip 5, the solder joint 4c (FIG. 7D) cannot be joined or even if it can be joined, a sufficient current capacity cannot be obtained. If the height of the protrusion 8e is higher than the value obtained by adding the height of the solder bump 40a to the height of the semiconductor chip 5, the solder joint 4a cannot be joined or even if it can be joined, a sufficient current capacity can be obtained. I can't.

  Subsequently, as shown in FIG. 7 (b2), the semiconductor chip 5 is die-bonded to the first insulating substrate 8 by sheet solder.

  In the second embodiment as well, the diameter of the opening 2c is selected as shown in FIG. 3 in order to obtain sufficient current capacity for the solder joints 4a and 4c in FIG. By doing so, the current capacity can be controlled. Further, for example, even when the diameter of the opening 2c in FIG. 3A is required, as shown in FIG. 3B, the opening 2c having a smaller diameter than the opening 2c in FIG. A plurality of masks 2a can also be provided, and in this case, there is an effect that generation of voids in the solder joint portion can be reduced.

  Also, the lands 1a and 1b formed on the second insulating substrate 1 have the same number of openings and the center position of the mask 2a, and the diameter of the lands 1a and 1b is ± 20 of the diameter of the opening of the mask 2a. % Is desirable.

  The die bonding of the semiconductor chip 5 is performed by sheet soldering. However, an opening for die bonding may be provided at the position of the mask 2b corresponding to the chip mounting position, and die bonding may be performed using a solder paste.

  In addition, the solder used for die bonding of the semiconductor chip 5 is a solder having a melting point higher than that of the solder bumps 40a and 40b, regardless of whether a plate solder is used or a solder paste is used. Therefore, even if the solder bumps 40a and 40b are heated to a temperature at which the solder bumps 40b are melted, it is possible to suppress remelting of the solder die bonded to the semiconductor chip 5 and prevent the semiconductor chip 5 from being displaced or rotated. Become.

  Next, as shown in FIG. 7C, the surface on which the solder bumps 40a and 40b of the second insulating substrate 1 shown in FIG. 7B1 are formed, and the first insulation shown in FIG. 7B2. The surface of the substrate 8 on which the semiconductor chip 5 and the protrusion 8e are formed is opposed to each other.

  The solder bumps 40b of the second insulating substrate 1 are formed on the protrusions 8e of the first insulating substrate 8 so that the solder bumps 40a of the second insulating substrate 1 overlap the surface of the semiconductor chip 5 of the first insulating substrate 8. After positioning so as to overlap, the first insulating substrate 8 and the second insulating substrate 1 are heated.

  By heating until the solder bumps 40a and 40b are remelted, the solder bumps 40a of the second insulating substrate 1 are bonded to the surface electrodes of the semiconductor chip 5 of the first insulating substrate 8, and the second insulating substrate 1 The solder bumps 40 b are joined to the protrusions 8 e of the first insulating substrate 8.

  Thereafter, by cooling, as shown in FIG. 7D, the solder bumps 40a become solder joints 4a, and the lands 1a of the second insulating substrate 1 pass through the solder joints 4a. Electrically connected to the surface electrode.

  Also, the solder bump 40b becomes a solder joint 4c, and the land 1b of the second insulating substrate 1 is electrically connected to the protrusion 8e that is electrically connected to the back electrode of the semiconductor chip 5 on the first insulating substrate 8. Connect to.

  Finally, as shown in FIG. 7E, the semiconductor chip 5, the first insulating substrate 8, and the lands 1a and 1b between the first insulating substrate 8 and the second insulating substrate 1, solder bonding The sealing resin portion 6 that covers the portions 4a and 4c and the protruding portion 8e is formed of potting resin.

  Also in the second embodiment, the first insulating substrate 8 and the second insulating substrate 1 are not limited to the AlN substrate and the glass epoxy substrate as long as insulation can be obtained, and may be other insulating substrates. . The second insulating substrate 1 only needs to be able to form a land on which the solder gets wet like Cu. As the ceramic substrate, for example, an insulating substrate base material such as alumina, SiC, or SiN may be used.

  The lands 1a and 1b only need to be able to wet the solder, and the outermost surface is not limited to Cu, but may be any metal such as Sn, Au, and Ag. Moreover, the front surface electrode and the back surface electrode of the semiconductor chip 5 may be any metal that can be wetted by solder, and the outermost surface may be Sn, Au, Ag, or the like.

  Moreover, the sealing resin part 6 should just be what can ensure insulation and can fill between the 2nd insulated substrate 1 and the 1st insulated substrate 8 with resin, and is not restricted to potting resin, but is liquid. Gel or heat-resistant rubber may be used. Further, it may be sealed by transfer molding using a mold resin.

  Through the above steps, as in the first embodiment, wiring on a semiconductor chip and wiring on a substrate having different heights can be performed simultaneously without using wire bonding, and the manufacturing process can be simplified. The vertical space for wire looping is not required, and a miniaturized package can be provided.

  Also, with this configuration, the protrusion 8e is disposed at the position of the first insulating substrate 8 corresponding to the solder bump 40b of the second insulating substrate 1, so that the solder joint 4c and the first insulating substrate 8 are arranged. The positioning accuracy of the position where and is connected is improved.

  As described above, in the power semiconductor module 200 according to the second embodiment of the present invention, the first insulating substrate 8 and the second insulating substrate 1 are in the region where the semiconductor chip 5 of the first insulating substrate 8 is disposed. Is connected to the surface electrode of the semiconductor chip 5 of the first insulating substrate 8 and the land 1a of the second insulating substrate 1 by a solder joint portion 4a formed from a solder bump 40a provided on the land 1a. In the region other than the region where the semiconductor chip 5 of the insulating substrate 8 is disposed, the end portion of the protruding portion 8e formed on the land of the first insulating substrate 8 connected to the back electrode of the semiconductor chip 5 by the wiring pattern. And the land 1b of the second insulating substrate 1 are connected by the solder joints 4b formed from the solder bumps 40b on the land 1b. Even if there is a step in the region other than the region to place the region and the semiconductor chip to place up, without using wire bonding can be collectively wiring. Further, the package can be downsized in the height direction as compared with the case of using wire bonding.

  Further, the height of the semiconductor chip 5 is equal to or higher than the height of the semiconductor chip 5 by adding the height of the solder bump 40a to the protrusion of the solder bump 40b. It is possible to widen the allowable range for the intersections, and to secure the design margin.

  Furthermore, by arranging the protrusion 8e at the position of the first insulating substrate 8 corresponding to the solder bump 40b of the second insulating substrate 1, the position where the solder joint and the second insulating substrate are connected to each other is set. Improve positioning accuracy

  In addition, by performing batch wiring by printing / reflowing solder paste, productivity can be improved and costs can be reduced.

Embodiment 3 FIG.
In the second embodiment, in the region other than the region where the semiconductor chip 5 is disposed on the first insulating substrate 8, the solder joint 4 c connected to the land 1 b of the second insulating substrate 1 is formed on the first insulating substrate 8. Although it was set as the structure connected to the edge part of the formed projection part 8e, Embodiment 3 demonstrates the case where a solder joint part covers a projection part and connects.

  FIG. 8 is a cross-sectional view of a power semiconductor module 300 according to Embodiment 3 of the present invention. As shown in FIG. 8, the first insulating substrate 8 is not only provided with a columnar protrusion 8e made of Cu, but also a solder joint 4d that joins the land 1b of the second insulating substrate 1. However, the projection 8e is covered and joined to be electrically connected. The solder joint 4d is electrically connected to the first insulating substrate 8 and a land (not shown) that is electrically connected to the protrusion 8e and the back electrode of the semiconductor chip 5 on the first insulating substrate 8. .

  As in the second embodiment, the protrusion 8e has a cylindrical protrusion 8e (FIGS. 8 and 6A) as long as the protrusion 8e has a shape that can be bonded to the solder joint 4d of the second insulating substrate 1. )), But is not limited to a polygonal columnar shape such as a quadrangular prism shape (FIG. 6B), or a polygonal columnar projection such as a conical shape (FIG. 6C) or a triangular pyramid shape (FIG. 6D). It may be 8e.

  The protrusion 8e is not limited to Cu as long as it is a metal that gets wet with the solder, and may be made of metal such as Sn, Au, or Ag.

  Other configurations are the same as those of the power semiconductor module 100 of the first embodiment shown in FIG. 1, and the same portions are denoted by the same reference numerals and the description thereof is omitted.

  Next, a method for manufacturing the power semiconductor module 300 according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 9 is a sectional view showing a manufacturing process of the power semiconductor module 300 according to the third embodiment of the present invention.

  First, as in the first embodiment, as shown in FIG. 9A1, the second insulating substrate 1 is provided with lands 1a and 1b (Cu, φ1 mm) on the front surface and external electrodes 10 on the rear surface. In order to form solder bumps on the lands 1a and 1b on the surface, solder pastes 30a and 30b (for example, Sn—Ag—Cu solder) are printed using the mask 2a. The solder pastes 30a and 30b are not limited to Sn—Ag—Cu solder, but may also be one added with Sb or CuSn solder.

  Thus, the solder paste 30a for soldering to the front surface electrode of the semiconductor chip 5 and the solder paste for soldering to the wiring on the first insulating substrate 8 electrically connected to the back surface electrode of the semiconductor chip 5 30b can be formed simultaneously.

  Subsequently, as in the first embodiment, as shown in FIG. 9B1, by heating the second insulating substrate 1, the printed solder pastes 30a and 30b are melted and then cooled. Thus, the solder bumps 40a and 40b are obtained.

  In parallel with the above steps, as shown in FIG. 9 (a2), the first insulating substrate 8 is formed with a protrusion 8e at a position corresponding to the land 1b of the second insulating substrate 1. . As in the second embodiment, the method of forming the protrusion 8e is selected from brazing or casting depending on the type of the insulating substrate. However, the protrusion 8e is electrically connected to the back electrode of the semiconductor chip 5 by the wiring pattern. Wire bumps may be formed on lands (not shown). The wire at that time may be Au, Cu, or the like as long as the metal wets the solder.

  Further, the solder paste 32b (Sn—Ag—Cu solder) is applied to the first insulating substrate 8 by using the mask 2b in order to form the solder bumps 42b around the protrusions 8e around the protrusions 8e. Printed.

  Here, it is preferable that the height of the protruding portion 8 e is equal to or higher than the height of the semiconductor chip 5 and is equal to or lower than the value obtained by adding the height of the solder bump 40 a to the height of the semiconductor chip 5. When the height of the protrusion 8e is lower than the height of the semiconductor chip 5, the solder joint 4d (FIG. 9D) cannot be joined, or even if it can be joined, a sufficient current capacity cannot be obtained. If the height of the protrusion 8e is higher than the value obtained by adding the height of the solder bump 40a to the height of the semiconductor chip 5, the solder joint 4a cannot be joined or even if it can be joined, a sufficient current capacity can be obtained. I can't.

  Subsequently, as shown in FIG. 9B2, the semiconductor chip 5 is die-bonded to the first insulating substrate 8 by sheet solder. When die bonding is performed, the printed solder paste 32b is also melted by heating the first insulating substrate 8, and then cooled, whereby solder bumps 42b are formed on the side surfaces of the protrusions 8e.

  In the third embodiment as well, the diameter of the opening 2c is selected as shown in FIG. 3 in order to obtain sufficient current capacity for the solder joints 4a and 4d in FIG. By doing so, the current capacity can be controlled. Further, for example, even when the diameter of the opening 2c in FIG. 3A is required, as shown in FIG. 3B, the opening 2c having a smaller diameter than the opening 2c in FIG. A plurality of masks 2a can also be provided, and in this case, there is an effect that generation of voids in the solder joint portion can be reduced.

  Also, the lands 1a and 1b formed on the second insulating substrate 1 have the same number of openings and the center position of the mask 2a, and the diameter of the lands 1a and 1b is ± 20 of the diameter of the opening of the mask 2a. % Is desirable.

  The die bonding of the semiconductor chip 5 is performed by sheet soldering. However, an opening for die bonding may be provided at the position of the mask 2b corresponding to the chip mounting position, and die bonding may be performed using a solder paste.

  In addition, the solder used for die bonding of the semiconductor chip 5 is a solder having a melting point higher than that of the solder bumps 40a and 40b, regardless of whether a plate solder is used or a solder paste is used. Therefore, even if the solder bumps 40a and 40b are heated to a temperature at which the solder bumps 40b are melted, it is possible to suppress remelting of the solder die bonded to the semiconductor chip 5 and prevent the semiconductor chip 5 from being displaced or rotated. Become.

  Next, as shown in FIG. 9C, the surface on which the solder bumps 40a and 40b of the second insulating substrate 1 shown in FIG. 9B1 are formed, and the first insulation shown in FIG. 9B2. The surface of the substrate 8 on which the semiconductor chip 5 and the protrusion 8e are formed is opposed to each other.

  The solder bumps 40b of the second insulating substrate 1 are overlapped with the surface bumps of the semiconductor chip 5 of the first insulating substrate 8 so that the solder bumps 40b of the second insulating substrate 1 overlap the surface electrodes of the semiconductor chip 5 of the first insulating substrate 8. After the positioning, the first insulating substrate 8 and the second insulating substrate 1 are heated.

  By heating until the solder bumps 40a and 40b and the solder bump 42b are remelted, the solder bump 40a of the second insulating substrate 1 is joined to the surface electrode of the semiconductor chip 5 of the first insulating substrate 8, The solder bumps 40 b of the second insulating substrate 1 are joined to the solder bumps 42 b that cover the protrusions 8 e of the first insulating substrate 8.

  Thereafter, by cooling, as shown in FIG. 9D, the solder bumps 40a become solder joints 4a, and the lands 1a of the second insulating substrate 1 pass through the solder joints 4a. Electrically connected to the surface electrode.

  Further, the solder bump 40b and the solder bump 42b become a solder joint portion 4d, and the land 1b of the second insulating substrate 1 is electrically connected to the back electrode of the semiconductor chip 5 on the first insulating substrate 8. The solder joint 4d and the protrusion 8e are electrically connected.

  Finally, as shown in FIG. 9E, the semiconductor chip 5, the first insulating substrate 8, and the lands 1a and 1b between the first insulating substrate 8 and the second insulating substrate 1, solder bonding The sealing resin portion 6 that covers the portions 4a and 4d is formed of potting resin.

  Also in the third embodiment, the first insulating substrate 8 and the second insulating substrate 1 are not limited to the AlN substrate and the glass epoxy substrate as long as insulating properties can be obtained, and may be other insulating substrates. . The second insulating substrate 1 only needs to be able to form a land on which the solder gets wet like Cu. As the ceramic substrate, for example, an insulating substrate base material such as alumina, SiC, or SiN may be used.

  The lands 1a and 1b only need to be able to wet the solder, and the outermost surface is not limited to Cu, but may be any metal such as Sn, Au, and Ag. Moreover, the front surface electrode and the back surface electrode of the semiconductor chip 5 may be any metal that can be wetted by solder, and the outermost surface may be Sn, Au, Ag, or the like.

  Moreover, the sealing resin part 6 should just be what can ensure insulation and can fill between the 2nd insulated substrate 1 and the 1st insulated substrate 8 with resin, and is not restricted to potting resin, but is liquid. Gel or heat-resistant rubber may be used. Further, it may be sealed by transfer molding using a mold resin.

  Through the above steps, as in the first embodiment, wiring on a semiconductor chip and wiring on a substrate having different heights can be performed simultaneously without using wire bonding, and the manufacturing process can be simplified. The vertical space for wire looping is not required, and a miniaturized package can be provided.

  Also, with this configuration, the protrusion 8e is disposed at the position of the first insulating substrate 8 corresponding to the solder bump 40b of the second insulating substrate 1, so that the solder bonding on the first insulating substrate 8 is performed. In addition to improving the positioning accuracy of the position of the portion 4d, the solder joint portion 4d covers the protruding portion 8e and is also joined to the first insulating substrate 8, so that the electrical connection is ensured and reliability is improved. Improvements can be made.

  As described above, in the power semiconductor module 300 according to the third embodiment of the present invention, the first insulating substrate 8 and the second insulating substrate 1 are in the region where the semiconductor chip 5 of the first insulating substrate 8 is disposed. Is connected to the surface electrode of the semiconductor chip 5 of the first insulating substrate 8 and the land 1a of the second insulating substrate 1 by a solder joint portion 4a formed from a solder bump 40a provided on the land 1a. In a region other than the region where the semiconductor chip 5 of the insulating substrate 8 is disposed, the protrusion 8e formed on the land of the first insulating substrate 8 connected to the back electrode of the semiconductor chip 5 by the wiring pattern, The land 1b of the second insulating substrate 1 is connected by the solder joint portion 4b formed from the solder bump 42b covering the protrusion 8e and the solder bump 40b on the land 1b. In, even if there is a step in the region other than the region to place the region and the semiconductor chip disposing a semiconductor chip on the surface of the insulating substrate, without using the wire bonding can be collectively wiring. Further, the package can be downsized in the height direction as compared with the case of using wire bonding.

  Further, the protrusions 8e and the solder bumps 42b, which are equal to or higher than the height of the semiconductor chip 5 and less than or equal to the height of the semiconductor chip 5 plus the height of the solder bump 40a, are joined to the solder bump 40b. By doing so, it is possible to widen the allowable range for the intersection of the heights, and it is possible to secure a design margin.

  Further, by positioning the protrusion 8e at the position of the first insulating substrate 8 corresponding to the solder bump 40a of the second insulating substrate 1, the position of the solder joint portion on the first insulating substrate is determined. In addition to improving the accuracy, the solder joint 4d covers the projection 8e and is also joined to the first insulating substrate 8, so that the electrical connection is ensured and reliability can be improved. .

  In addition, by joining the solder bumps, the allowable range for the intersection of heights can be expanded, and the design margin can be ensured. Furthermore, the self-correction of the positional deviation is possible due to the tension between the solders.

  In addition, by performing batch wiring by printing / reflowing solder paste, productivity can be improved and costs can be reduced.

  In addition, although Si IGBT was used as the semiconductor chip 5 which comprises the power semiconductor modules 100, 200, and 300 in the first to third embodiments described above, the present invention is not limited to this. You may form with a wide band gap semiconductor with a large band gap compared with Si. Examples of the wide band gap semiconductor include SiC, GaN, and diamond.

  A semiconductor chip formed of such a wide band gap semiconductor has high voltage resistance and high allowable current density. In addition, since the heat resistance is high, the cooling fins of the heat dissipating member can be downsized or air cooled, so that the power semiconductor module can be further downsized.

  As miniaturization of power semiconductor semiconductors progresses, the requirement for long-term reliability against thermal stress is further enhanced to ensure heat dissipation. The power semiconductor module of the present invention exhibits excellent effects even in response to such demands.

  It should be noted that within the scope of the invention, the embodiments can be freely combined, or the embodiments can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 1 2nd insulating substrate, 1a, 1b land, 4a, 4b, 4c, 4d Solder joint part, 5 Semiconductor chip, 8 1st insulating substrate, 8e Protrusion part, 10 External electrode, 40a, 40b, 41b, 42b Solder Bump, 100, 200, 300 Power semiconductor module

Claims (15)

A first insulating substrate formed with a protrusion electrically connected to a back electrode of the semiconductor element in a region other than the region where the semiconductor element is disposed, on the same surface as the surface where the semiconductor element is disposed; ,
On the surface of the first insulating substrate facing the surface on which the semiconductor element is installed and the protrusion is formed, the internal terminal is located at a position corresponding to the surface electrode of the semiconductor element and the protrusion, respectively. A second insulating substrate formed and connected to the internal terminal via a through hole and an external terminal formed on the other surface;
A first bonding portion connected to the surface electrode of the semiconductor element installed on the first insulating substrate and the internal terminal of the second insulating substrate at a position corresponding to the surface electrode;
And a second bonding portion connected to the protrusion of the first insulating substrate and the inner terminal of the second insulating substrate at a position corresponding to the protrusion. Power semiconductor module.   The power semiconductor module according to claim 1, wherein the first joint portion and the second joint portion are formed of solder.   The protrusion is not less than a height equal to or higher than the height of the semiconductor element, and not more than a value obtained by adding a height of the solder bump forming the second joint to the height of the semiconductor element. The power semiconductor module according to claim 2.   4. The power semiconductor module according to claim 1, wherein the second joint is connected to an end of the protrusion. 5.   4. The power semiconductor module according to claim 1, wherein the second joint portion is connected so as to cover the projecting portion. 5.   The power semiconductor module according to claim 2, wherein the protrusion is formed of solder.   The power semiconductor module according to any one of claims 1 to 6, wherein the semiconductor element is a wide band gap semiconductor.   The power semiconductor module according to claim 7, wherein the wide band gap semiconductor is a semiconductor using silicon carbide, a gallium nitride-based material, or diamond. A semiconductor element is disposed on one surface of the first insulating substrate, and the back surface electrode of the semiconductor element and the electrical surface are formed in a region other than the region where the semiconductor element is disposed on the same surface as the surface where the semiconductor element is disposed. Forming the connected projections, and
Corresponding to the surface electrode of the semiconductor element and the protrusion on one surface of the second insulating substrate facing the surface on which the semiconductor element is installed and the protrusion is formed, of the first insulating substrate. Forming solder bumps on the internal terminals respectively formed at the positions;
A surface electrode of the semiconductor element of the first insulating substrate and a solder bump on the inner terminal of the second insulating substrate provided at a position corresponding to the surface electrode are overlapped, and the first Overlap the end of the protrusion of the insulating substrate and the solder bump on the inner terminal of the second insulating substrate provided at a position corresponding to the protrusion, and heat-melt the solder bump. A method of manufacturing a power semiconductor module, comprising: a step of soldering together by cooling.   The protrusion is not less than a height equal to or higher than the height of the semiconductor element, and not more than a value obtained by adding the height of the solder bump formed at a position corresponding to the surface electrode of the semiconductor element to the height of the semiconductor element. The method for manufacturing a power semiconductor module according to claim 9, wherein the power semiconductor module is provided.   The method for manufacturing a power semiconductor module according to claim 9, wherein the protrusion is formed of solder.   12. The method of manufacturing a power semiconductor module according to claim 11, wherein the step of forming the protruding portion includes a step of performing a surface treatment to wet the solder in a position range where the protruding portion is formed.   11. The method for manufacturing a power semiconductor module according to claim 9, wherein the step of forming the protrusion includes a step of forming a solder bump on a side surface of the protrusion.   The method for manufacturing a power semiconductor module according to claim 9, wherein the semiconductor element is a wide band gap semiconductor.   The method of manufacturing a power semiconductor module according to claim 14, wherein the wide band gap semiconductor is a semiconductor using silicon carbide, a gallium nitride-based material, or diamond.

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