JP4038173B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device including an extraction electrode connected to a semiconductor element.

The lead electrode of the power semiconductor element constituting the power semiconductor device is indispensable for taking out an electrical signal from the semiconductor element to the outside. For example, a structure has been proposed in which a plate-like member is prepared as an extraction electrode, and the plate-like member is joined to an electrode on the surface of a semiconductor element to extract an electric signal to the outside.
In order to join the plate-like member to the electrode of the semiconductor element, the plate-like member and the electrode are joined with solder, and a metal having good wettability with respect to the solder is also provided on the portion covered with the insulating layer other than the electrode. Then, a plate-like member is joined with solder (for example, see Patent Document 1).
JP 2000-114445 A

  However, there has been a problem that thermal stress is generated in the joint due to a temperature cycle such as heat dissipation from the power semiconductor element, the insulating layer is broken, and an electrical short circuit occurs.

  Therefore, as a result of repeated research on such a short circuit, it was found that the problem is that the control wiring covered with the insulating layer and the plate-like member on the insulating layer are electrically short-circuited due to the breakdown of the insulating layer. Completed the invention.

  That is, an object of the present invention is to provide a highly reliable power semiconductor device that does not cause a short circuit even when used in an environment where thermal stress is applied.

The present invention relates to a semiconductor element in which a control wiring and an external electrode arranged opposite to each other with the control wiring interposed therebetween on the same surface, an insulating layer covering the control wiring, a connection material provided on the external electrode, and a connection A power semiconductor device comprising an extraction electrode connected to a material, and a gap provided between the connection material and the insulating layer. Further, a metal film that covers the insulating layer and the external electrode may be included.

  As described above, the power semiconductor device according to the present invention can prevent destruction due to thermal stress when a temperature cycle is loaded, and can provide a power semiconductor device with a high reliability line.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of the power semiconductor device according to the first embodiment of the present invention, the whole being represented by 100, and FIG. 2 is a perspective view of the vicinity of the IGBT 2 of the power semiconductor device 100.
The power semiconductor device 100 includes a block 1. The block 1 is made of, for example, copper having a thickness of 3 mm. On the block 1, the IGBT 2 and the diode 3 are fixed by solder 4A. The IGBT 2 is, for example, 0.4 mm thick and 15 mm in length and width, and the diode 3 is, for example, 0.3 mm thick, 11 mm long × 17 mm wide. For example, Sn-Ag-Cu solder having a thickness of 0.15 mm is used for the solder 4A.
The block 1 serves as both the heat radiation means from the IGBT 2 and the diode 3 and the backside wiring of both elements.

  For example, a lead made of copper having a thickness of 0.2 mm is connected to the IGBT 2 and the diode 3 with solder 4B as a connection material. Specifically, the lead 5 includes an extraction electrode portion 5A, and the extraction electrode portion 5A is electrically connected to the electrode of the IGBT 2 and the electrode of the diode 3 respectively. For example, Sn-Ag-Cu solder having a thickness of 0.2 mm is used for the solder 4B.

  The block 1 is fixed to the electrode terminal 6B and the lead 5 is fixed to the electrode terminal 6A, respectively, and inputs / outputs current to / from the outside of the apparatus. The gate electrode (not shown) of the IGBT 2 and the electrode terminal 6 </ b> C are connected using, for example, an aluminum bonding wire 7. Further, the IGBT 2 and the like are sealed in the resin casing 8 by transfer molding.

FIG. 3 shows the electrode shape on the surface of the IGBT 2. A gate electrode 9 as a control electrode and an emitter electrode 10 as an external electrode having a transistor structure inside are provided on the surface of the IGBT 2. The gate electrode 9 is connected to a gate wiring 9A which is a plurality of control wirings arranged so as to divide the emitter electrode 10.
In FIG. 3, the emitter electrodes 10 are disposed to face each other with the gate wiring 9 </ b> A interposed therebetween, but the two emitter electrodes 10 that are disposed to face each other may be connected. That is, the present invention is applied to a structure in which the gate wiring 9A is arranged so as to divide the two emitter electrodes 10 regardless of whether or not the two emitter electrodes 10 are connected to each other.

  4 is a partial cross-sectional view of the vicinity of the IGBT 2 of the power semiconductor device 100 of FIG. 2 when viewed in the II-II direction. On the semiconductor substrate 2A such as silicon, the emitter electrode 10 is disposed so as to face the gate wiring 9A. The gate wiring 9A has a thickness of 4 μm, is covered with a 1 μm thick insulating layer 9B made of a glass-based material, etc., and is insulated from the surrounding 4 μm thick emitter electrode 10 and the like. The distance between the gate wiring 9A and the emitter electrode 10 is about 5 μm.

On the surface of the emitter electrode 10, a metal layer 10A having a laminated structure of Al / Mo / Ni / Au is formed by vacuum deposition in order from the bottom so that the solder 4B gets wet. In the metal film 10A, Au on the outermost surface is dissolved in the solder during solder joining, and Ni and Sn of the solder are alloyed.
On the other hand, since the insulating layer 9B does not wet with the solder 4B, a gap 11 is formed on the insulating layer 9B.
Although not shown here, a metal layer is similarly formed on the surface of the diode 3 so that the solder 4B is wet.

Here, as for the solder 4B, it is desirable not to use flux for soldering. That is, when soldering is performed using a flux, the flux remains in a portion that should become the gap 11. Normally, these fluxes are removed by a cleaning process using a solvent or the like, but as in this embodiment, the solvent does not penetrate into the gap 11 having a thickness of 0.1 mm or less, and the flux remains. As a result, the insulating layer 9 </ b> B and the emitter electrode 10 are corroded by the flux, causing a device defect and the like.
When the thickness of the solder 4B is reduced, or when the portion corresponding to the gap of the extraction electrode 5A is coated with a material such as a polymer material that does not wet the solder, The solder 4B does not exist, and the gap 11 comes into direct contact with the extraction electrode portion 5A.

  Thus, in the power semiconductor device 100 according to the present embodiment, the air gap 11 is provided on the insulating layer 9B covering the gate wiring 9A. For this reason, the solder 4B joined to the emitter electrode 10 is not connected to the insulating layer 9B. Therefore, even when exposed to a temperature cycle due to heat dissipation from the IGBT 2, thermal stress resulting from a difference in thermal expansion coefficient between silicon, which is the main material of the IGBT 2, and copper, which is a component of the lead 5, is applied to the insulating layer 9B. And the damage to the insulating layer 9B can be prevented. This is especially true when copper or aluminum having a large difference in thermal expansion coefficient from silicon is used as the lead material. As a result, damage due to thermal stress, which has occurred in conventional power semiconductor devices, can be prevented, and a highly reliable power semiconductor device can be obtained.

FIG. 5 shows the number of cycles to break when a temperature cycle test (from −40 ° C. to 125 ° C.) is performed on a sample with and without voids.
The cross-sectional shape of the sample used for the test is almost the same as that in FIG. 4, and a semiconductor chip having a 0.2 mm-thick copper plate joined to the semiconductor chip by solder is used. A sample having a gap 11 (with a gap) is produced by forming an insulating layer 9B so as to cover the gate wiring 9A, similarly to the structure of FIG. On the other hand, a sample having no void is produced by forming a metal film on which solder is wetted also on the insulating layer 9B.

As shown in FIG. 5, when the solder material is in contact with the insulating layer 9B (no gap), destruction occurs in about 1000 cycles, whereas when the solder material is not in contact with the insulating layer 9B (with a gap), Testing up to 5000 cycles did not cause damage.
From the results of FIG. 5, it can be seen that the structure according to the present embodiment in which the air gap 11 is provided does not cause damage due to the temperature cycle and can provide a highly reliable power semiconductor device.
Further, since sufficient insulation can be obtained even if the rigidity of the insulating layer is lowered, the thickness of the insulating layer can be reduced to 1 μm or less, and the manufacturing cost of the power semiconductor device can be reduced.

FIG. 6 is a cross-sectional view of another power semiconductor device according to the present embodiment, indicated as a whole by 110. In FIG. 6, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. The power semiconductor device 110 is not a transfer mold type but a gel-sealed case type. That is, the insulating substrate 16 on which the IGBT 2 is mounted is surrounded by the resin case 14 and filled with the silicon gel 15 therein.
Also in the power semiconductor device 110, the gap 11 can be provided above the gate wiring 9A using the structure of FIG. Thereby, destruction due to thermal stress can be prevented, and a highly reliable power semiconductor device can be obtained.

  In addition, although the case where copper with high electric conductivity was used as the material of the lead 5 was described, a material obtained by subjecting an iron-based wiring material such as aluminum, Kovar, or 42 Alloy to a process in which solder is wetted may be used. .

  Further, an element such as a MOSFET may be used in place of the IGBT 2.

  Moreover, although the case where Sn-Ag solder is used as the solder material has been described, other solder materials such as Au-Si or Sn-Pb may be used.

  A multilayer structure of Al / Mo / Ni / Au was used as the metal film to which the solder gets wet. For the production of such a multilayer structure, vapor deposition using a mask pattern or electroless plating using a resist mask is used. Can be used. In addition, for the metal film, other laminated structures such as Al / Ti / Ni / Au and Al / Ni / Au, and other metals that cause solder to wet, such as Ni, Ag, Au, Pd, and Cu, are used. It doesn't matter.

  For the insulating layer 9B, in addition to a glass-based material, a polymer material such as polyimide, silicon oxide, silicon nitride, or the like can be used.

  These materials can also be applied to power semiconductor devices according to other embodiments described below.

Embodiment 2. FIG.
FIG. 7 is a partial cross-sectional view of the power semiconductor device according to the second embodiment, the whole being represented by 200. In FIG. 7, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
In the power semiconductor device 200, for example, a metal layer 12 made of aluminum having a thickness of 4 μm is formed so as to cover the insulating layer 9 </ b> B and the emitter electrode 10. The metal layer 12 is formed by, for example, a vapor deposition method and is electrically connected to the emitter electrode 10.
Further, on the surface of the metal layer 12 above the emitter electrode 10, a metal film 12 </ b> A that gets wet by solder is formed.

  On the metal film 12A, the lead electrode portion 5A is joined by, for example, Sn—Ag—Cu-based solder 4B by a method not using a flux. Thereby, the space | gap 11 is formed on the metal film 12 without the metal film 12A which the solder gets wet.

  In such a structure, by connecting the divided emitter electrodes 10 with the metal layer 12, even when the gap 11 is large, for example, a current path between the emitter electrodes 10 is secured by the metal layer 12. For this reason, the current drawing efficiency from the IGBT 2 can be improved.

  In the power semiconductor device 200, thermal stress caused by the difference in thermal expansion coefficient between the IGBT 2 and the extraction electrode 5A is applied to the metal layer 12 on the emitter electrode 10 and the solder 4B. Here, in the metal layer 12, since the stress is relieved by the step existing between the gate wiring 9A and the emitter electrode 10, the metal layer 12 on the gate wiring 9A is not subjected to shear deformation. Accordingly, the gate wiring 9A and the surrounding insulating layer 9 are not deformed and are not destroyed. As a result, it is possible to suppress the occurrence of defects due to a short circuit between the gate wiring 9A and the emitter electrode 10, and to provide a highly reliable power semiconductor device 200.

  In addition, even if cracks develop in the solder 4B due to thermal stress due to the temperature cycle and the bonding area with the metal film 12A decreases, the metal layer 12 continues, so that the metal is reduced against the decrease in the bonding area. The layer 12 serves as a current bypass, and an increase in electrical resistance can be prevented.

  Similarly, even if the region where the metal film 12A is formed is reduced, the effect on the increase in resistance is small. Therefore, even if the mounting position accuracy of the extraction electrode 5A and the deposition position accuracy of the metal film 12A are lowered, The characteristics of the semiconductor device do not deteriorate. For this reason, the manufacturing process of the power semiconductor device can be simplified, and the manufacturing cost can be reduced.

Embodiment 3 FIG.
FIG. 8 is a perspective view of the vicinity of the IGBT 2 of the power semiconductor device according to the third embodiment of the present invention, the whole being represented by 300. FIG. 9 is a cross-sectional view of the power semiconductor device 300 of FIG. 8 in the VIII-VIII direction. 8 and 9, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions.

As shown in FIG. 8, in the power semiconductor device 300, the lead electrode portion 5 </ b> A of the lead 5 has a shape divided into strips. The strip-shaped lead electrode portion 5A is produced, for example, by press punching the lead 5, etching, or the like. Further, a gap 13 is formed between the extraction electrodes 5A.
The width of the strips and the interval between the strips are not particularly limited, but are preferably about the same as the plate thickness of the leads 5 from the viewpoint of formability.
Further, the position where the strip-shaped lead electrode portion 5A is arranged is not particularly specified. However, when the lead electrode portion 5A is located above the gate wiring 9A and the emitter electrode 10 are located, the following implementation is performed. This will be described in Embodiments 4 and 5.

  In the power semiconductor device 300 according to the present embodiment, since the extraction electrode 5A is divided into strips, the thermal stress when the extraction electrode 5A expands can be made smaller than that of the integrated extraction electrode 5A. Further, not only the thermal stress on the gate wiring 9A and the insulating layer 9B but also the thermal stress on the emitter electrode 10 can be reduced. Moreover, since the thermal stress to the solder 4B is also reduced, cracks occurring in the solder 4B can be suppressed. As a result, a highly reliable power semiconductor device 300 can be obtained.

  The extraction electrode portion 5A connected to the diode 2 does not have the gate wiring 9A, and thus does not need to be divided into strips. However, in order to reduce thermal stress, It is preferable to do.

Embodiment 4 FIG.
FIG. 10 is a partial cross-sectional view of the power semiconductor device according to the fourth embodiment of the present invention, indicated as a whole by 400. 10, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

  In the power semiconductor device 400 according to the present embodiment, as in the third embodiment, the extraction electrode 5A is divided into strips, and the extraction electrode 5A is disposed above the gate wiring 9A. ing. A gap 11 is provided above the gate wiring 9A so that the metal layer 12 and the solder 4B do not contact each other.

  In such a power semiconductor device 400, by providing the gap 11 on the metal layer 12, it is possible to prevent the insulating layer 9B from being damaged by thermal stress without coating a polymer material such as polyimide as described later. The formation of the void 11 does not involve an increase in the manufacturing process, and a highly reliable power semiconductor device 400 can be obtained without increasing the manufacturing cost.

Embodiment 5. FIG.
FIG. 11 is a partial cross-sectional view of the power semiconductor device according to the fifth embodiment of the present invention, indicated as a whole by 500. 11, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
As shown in FIG. 11, in the power semiconductor device 500 according to the present embodiment, there is no solder 4B and no lead electrode 5A above the gate wiring 9A, and a gap 13 is formed.

  For example, in the case of a gel-sealed semiconductor device as shown in FIG. 6, the gap 13 is filled with silicon gel to form a relaxation layer (not shown). However, the silicon gel has a small elastic coefficient, and the adhesion with the metal layer 12 is also smaller than the adhesion when the solder 4B is wet. For this reason, the thermal stress which is so large that the insulating layer 9B is destroyed does not occur, and the insulating layer 9B does not break. The silicon gel is formed by gelling by pouring a liquid silicon material into the gap 13 and then heating at 150 ° C. for about 1 hour.

On the other hand, when the resin-encapsulated semiconductor device as shown in FIG. 1 is used, the gap 13 is filled with a resin such as an epoxy resin to form a relaxation layer (not shown). To fill the epoxy resin in the gap 13, for example, placed in a mold in a state that combines each member, the gel-like epoxy resin is injected at a pressure of 120 kg / cm ² in a mold, about 180 ° C. Heat-curing with

  By interposing a buffer layer (not shown) such as a polyimide film of about 4 to 10 μm, for example, between the insulating layer 9B and a resin such as silicon gel or epoxy resin, the elasticity of the resin or the like that fills the gap 13 You can raise the rate. The buffer layer is, for example, a polyimide film formed by spin-coating polyamic acid with the insulating layer 9B formed and heating. In such a structure, deformation due to thermal stress is relaxed by the polyimide layer, and damage to the insulating layer 9B can be prevented.

  As described above, in the power semiconductor device 500, similarly to the power semiconductor devices 300 and 400 described above, it is possible to prevent the insulating layer 9B from being broken due to thermal stress, and to obtain a highly reliable power semiconductor device.

  Further, as in the case where the extraction electrode 5A is arranged on one surface (FIG. 2), it is possible to draw an equal current from each emitter electrode 10 toward the width of the strip-shaped extraction electrode 5A. For this reason, it becomes possible to operate the power semiconductor device efficiently.

  Furthermore, in the structure in which the gap 13 is formed, the flux can be easily cleaned even if soldering using the flux is performed. For this reason, mass processing by soldering using a flux becomes possible.

Embodiment 6 FIG.
FIG. 12 is a perspective view of the vicinity of the IGBT 2 of the power semiconductor device according to the sixth embodiment of the present invention. As is apparent from FIG. 12, in the present embodiment, the extraction electrode portion 5A is divided into strips as described above, and the connecting portions 5B that connect the respective strip-like portions are formed at the tip portions thereof. Is provided.

Although current is drawn from the lead electrode 5A in one direction, the current flowing in each strip portion may vary. In such a case, current drawing from the IGBT 2 may not be uniform, and the temperature may rise locally. Although this is alleviated by the metal layer 12, the thickness of the metal layer 12 is small, so that the effect of equalization is reduced when the variation in current is large.
Therefore, as shown in FIG. 12, by connecting the tips of the strip-shaped lead electrode portions 5A with the connecting portions 5B, the current variation in the strip portions can be made uniform, and the local temperature rise of the IGBT 2 can be suppressed.

  Further, with this structure, the extraction electrode portion 5A is not easily deformed, the soldering accuracy of the extraction electrode portion 5A is improved, and a highly reliable power semiconductor device can be easily manufactured.

It is sectional drawing of the semiconductor device for electric power concerning Embodiment 1 of this invention. 1 is a perspective view of an IGBT according to a first embodiment of the present invention. 1 is a surface view of an IGBT according to a first embodiment of the present invention. 1 is a partial cross-sectional view of a power semiconductor device according to a first embodiment of the present invention. This is the number of cycles until the semiconductor chip is destroyed. It is sectional drawing of the other power semiconductor device concerning Embodiment 1 of this invention. It is a fragmentary sectional view of the power semiconductor device concerning Embodiment 2 of this invention. It is a perspective view of IGBT concerning Embodiment 3 of this invention. It is a fragmentary sectional view of the semiconductor device for electric power concerning Embodiment 3 of this invention. It is a fragmentary sectional view of the power semiconductor device concerning Embodiment 4 of this invention. It is a fragmentary sectional view of the power semiconductor device concerning Embodiment 5 of this invention. It is a perspective view of IGBT concerning Embodiment 6 of this invention.

Explanation of symbols

1 block, 2 IGBT, 2A semiconductor substrate, 3 diode, 4A, 4B solder, 5 lead, 5A lead electrode part, 5B connecting part, 6A, 6B, 6C electrode terminal, 7 bonding wire, 8 resin housing, 9 gate electrode , 9A gate wiring, 9B insulating layer, 10 emitter electrode, 11 void, 12 metal layer, 10A, 12A metal film, 13 void, 14 resin case, 15 silicon gel, 16 insulating substrate.

Claims (10)

A semiconductor element in which a control wiring and an external electrode arranged opposite to each other with the control wiring interposed therebetween are arranged on the same surface ;
An insulating layer covering the control wiring;
A connection material provided on the external electrode;
An extraction electrode connected to the connection material ,
A power semiconductor device, wherein a gap is provided between the connection material and the insulating layer . A semiconductor element in which a control wiring and an external electrode arranged opposite to each other with the control wiring interposed therebetween are arranged on the same surface ;
An insulating layer covering the control wiring;
A metal film covering the insulating layer and the external electrode;
A connection material provided on the metal film;
An extraction electrode connected to the connection material ,
A power semiconductor device, wherein a gap is provided between the connection material and the metal film . 3. The power semiconductor device according to claim 1, wherein the lead electrode is composed of comb-like electrodes divided into strips and arranged substantially in parallel. 4. A semiconductor element in which a control wiring and an external electrode arranged opposite to each other with the control wiring interposed therebetween are arranged on the same surface ;
An insulating layer covering the control wiring;
A connection material provided on the external electrode;
A comb-shaped lead electrode connected to the connecting material and divided into strips and arranged substantially in parallel ;
A power semiconductor device, wherein a gap is provided above the control wiring . A semiconductor element arranged to face the external electrodes sandwiching the control lines and control lines are juxtaposed on the same surface,
An insulating layer covering the control wiring;
A metal film covering the insulating layer and the external electrode;
A connection material provided on the metal film;
A comb-shaped lead electrode connected to the connecting material and divided into strips and arranged substantially in parallel ;
A power semiconductor device, wherein a gap is provided above the control wiring . A semiconductor element in which a control wiring and an external electrode arranged opposite to each other with the control wiring interposed therebetween are arranged on the same surface ;
An insulating layer covering the control wiring;
A connection material provided on the external electrode;
A comb-shaped lead electrode connected to the connecting material and divided into strips and arranged substantially in parallel ;
A power semiconductor device, wherein the lead electrode is provided above the external electrode, and a relaxation layer is filled above the control wiring. A semiconductor element in which a control wiring and an external electrode arranged opposite to each other with the control wiring interposed therebetween are arranged on the same surface ;
An insulating layer covering the control wiring;
A metal film covering the insulating layer and the external electrode;
A connection material provided on the metal film;
A comb-shaped lead electrode connected to the connecting material and divided into strips and arranged substantially in parallel ;
A power semiconductor device, wherein the lead electrode is provided above the external electrode, and a relaxation layer is filled above the control wiring. 8. The power semiconductor device according to claim 6, wherein the relaxation layer is made of a material selected from silicon gel and epoxy resin. 9. The power connection device according to claim 1, wherein the connection material is made of one solder selected from Sn—Ag solder, Au—Si solder, and Sn—Pb solder. Semiconductor device. 9. The power semiconductor device according to claim 3, further comprising a connecting portion for connecting the extraction electrode at an end of the comb-shaped extraction electrode.

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