JPH0348452A - Two-terminal surface mount semiconductor device - Google Patents
Two-terminal surface mount semiconductor deviceInfo
- Publication number
- JPH0348452A JPH0348452A JP1339506A JP33950689A JPH0348452A JP H0348452 A JPH0348452 A JP H0348452A JP 1339506 A JP1339506 A JP 1339506A JP 33950689 A JP33950689 A JP 33950689A JP H0348452 A JPH0348452 A JP H0348452A
- Authority
- JP
- Japan
- Prior art keywords
- package
- pins
- lead
- soldering
- lead pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000005476 soldering Methods 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000011247 coating layer Substances 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 238000003825 pressing Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 9
- 239000011347 resin Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 8
- 238000000465 moulding Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 238000005452 bending Methods 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- 206010011224 Cough Diseases 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229920000742 Cotton Polymers 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10909—Materials of terminal, e.g. of leads or electrodes of components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
〔産業上の利用分野〕
この発明は、半導体ダイオードなどの二端子面実装形半
導体装置、特にそのリード端子構造に関する.
〔従来の技術〕
頭記した二端子面実装形半導体装置として、第10図,
第11図に示すように半導体チップをリードフレームに
マウントして樹脂封止した構造のものが従来より知られ
ている.図において、1は半導体チフプ、2は半導体チ
ップlの周辺を封止した樹脂パフケージ、3はパンヶー
ジ2より引出したリード片、4は補助リード片である.
かかる構造の半導体装置の製造方法を第11図により説
明すると、まず第11図ta+のように金属平板から所
要の形状にブレス成形したリードフレーム5の所定位直
に半導体チンプ1をマウントし、さらに別な補助リード
片4を図示のように半導体チンプlとリ一ド5との間に
半田付けして接続する.次に同図(blのようにトラン
スファ成形により半導体チップ1の周辺を封止して樹脂
パッケージ2を成形した後、さらにリードフレーム5を
一点鎖線に沿いリードカントして同図(C)のものを得
る.次に同図(dlのようにバンケージ2の両端から引
出したリード片3にフォーミング加工を施し、その先端
部を同一面上に揃えるようにパッケージ2の下面側へ向
けてヘアピン状に成形する.
かかる半導体装置はプリント配線板への実装に際して、
リード片3の先端部を下に向けて基板上に搭載し、リフ
ロー半田付けなどの方法で面実装される.[Industrial Field of Application] The present invention relates to a two-terminal surface mount semiconductor device such as a semiconductor diode, and particularly to a lead terminal structure thereof. [Prior art] As the two-terminal surface mount type semiconductor device mentioned above, FIG.
As shown in Fig. 11, a structure in which a semiconductor chip is mounted on a lead frame and sealed with resin is conventionally known. In the figure, 1 is a semiconductor chip, 2 is a resin puff cage that seals the periphery of the semiconductor chip l, 3 is a lead piece pulled out from the pan cage 2, and 4 is an auxiliary lead piece. A method of manufacturing a semiconductor device having such a structure will be explained with reference to FIG. 11. First, as shown in FIG. 11, a semiconductor chimp 1 is mounted directly at a predetermined position on a lead frame 5 which is press-molded into a desired shape from a flat metal plate, and then Another auxiliary lead piece 4 is soldered and connected between the semiconductor chip l and the lead 5 as shown in the figure. Next, as shown in the same figure (bl), after sealing the periphery of the semiconductor chip 1 and molding the resin package 2 by transfer molding, the lead frame 5 is further canted along the dashed line to form the one shown in the same figure (C). Next, as shown in the same figure (dl), form the lead pieces 3 pulled out from both ends of the bankage 2, and form them into a hairpin shape toward the bottom of the package 2 so that the tips are aligned on the same plane. Molding. When mounting such a semiconductor device on a printed wiring board,
The lead piece 3 is mounted on the board with the tip facing downward, and surface-mounted using a method such as reflow soldering.
ところで、前記した従来構造の面実装型半導体装置では
、製作.および製品の取扱面で次記のような難点がある
.すなわち、
11)特注品として作られたリードフレーム5を使用し
てここに半導体チップlをマウントした構造であるので
、金型を含めたリードフレームの製作費が高く、コスト
高である,
(2)リードフレーム上で半導体チフブ1をリード片3
に接続するためには、リードフレーム5の他に補助リー
ド片4.およびその半田付け工程が必要である.
《3)製作過程で、個々の半導体装置はリードフレーム
上でサイドレール.タイバーにより一体に連結されてい
るので、リードフレームカット前の状態では個別に特性
試験が行えない.
本発明は上記の点にかんがみなされたものであり、前記
した従来構造の問題点を解決して安価に製作できる二端
子面実装形半導体装置を提供することを目的とする.
CRBを解決するための手段〕
上記1jlMを解決するために、本発明による二端子面
実装形半導体装置は、パッケージで封止された半導体チ
ップと、半導体チップを中央に挟んでパッケージの両端
から同紬上に引出したリードピンとの組立体からなり、
かつリードピンの先端部にプレス加工を施して偏平な半
田付け脚部を成形するとともに、核半田付け脚部の板面
を同一面上に揃えてパッケージの両端から引出した各リ
ードピンをヘアピン状に成形してI戒するものとする.
また、前記構威の半導体装置をプリント配線板へ面実装
するに際しての半田付け性を高めるために、リードピン
の先端部をプレス加工する以前に、リードピンの表面に
層厚さが1〜10μmである半田付着性のよい金属被覆
層を被着形成することができる.
また、同様な目的でリードピンの先端部に半田付け脚部
をプレス加工した後に、咳半田付け脚部の表面に半田付
着性のよい金属被覆層を被着形成することもできる.
〔作用〕
上記の構威により、リードフレームを用いることなく、
在来の同紬リード形半導体素子と同様に、リードに九線
のりードビンを使用して面実装の可能なリード端子構造
が得られる.特にリードピンの先端部にプレス加工を施
してここに偏平板状の半田付け脚部を形成したので、プ
リント配線根上に安定よく面実装できる.
また、前記構威でリードピンの先端部をプレス加工する
以前に、リードピンの表面に層厚さが1〜10μmであ
る十分な厚みを持った半田付着性のよい金属材.例えば
半田,銀などの金属被覆層を被着形戒したことにより、
その後にリードピンの先端にプレス加工を施しても、金
r!ANが剥がれてリードピンの下地金属が露出するよ
うなことがなく、プリント配線板に対して付着性よく半
田付けを行うことができる.なお、この金属被覆層はデ
ィンピング,ないしメッキ法などの表面処理で容易に被
着形成が可能である.
さらに、リードピンの先端部に半田付け脚部をプレス加
工した後に、咳半田付け脚部の表面に半田付着性のよい
金属被覆層を被着形成すれば、プレス加工の影響を受け
ることなく半田付け脚部に金属被覆層を安定よく被着形
戚することができ、プリント配線板との間で付着性のよ
い半田付が行える.
〔実施例〕
以下本発明の実施例を図面に基づいて説明する.まず、
第1図ないし第3図は本発明実施例の構造を示すもので
あり、図において、1は半導体チップ、2は半導体チン
ブ1の周辺を封止した樹脂パフケージ、6は半導体チッ
プ1を中央に挟んでパンケージ2の両端から同柚上に引
出した九線のりードピンである.また、咳リードピン6
に対して、半導体チップ1との接合端面にはプレス加工
により鍔円板状の電極ヘッダ6aが、さらにパッケージ
2より引出した先端部には偏平板状の半田付け脚部6b
が形成されており、かつ咳半田付け脚部6bの仮面をバ
フケージ2の下面側で同一面上に揃えるようにしてリー
ドピン6がフォーミング加工によりヘアピン状に屈曲成
形されている.かかる構造の面実装形半導体vt置は、
プリント配線板へ実装する際に前記した偏平板状の半田
付け脚部6bを下向きにして基板上に搭載し、半田リフ
ローなどにより半田付け接合される.次に前記構造の半
導体装置の製造方法を第4図により説明する.まず、九
線の線材から適当な長さに切断したリードピン6の一端
にはあらかじめ電極ヘソダ6aをプレス成形しておき、
同図1a)のように半導体チンプlを中央に挟んでその
両側に2本のリードピン6を同軸に並べ、半導体チップ
1と電極ヘッダ6aとの間を半田付けなどで接合する.
次に同図(blのように半導体チップ1とりードピン6
との組立体をモールド金型に挿入し、半導体チップの周
辺を封止するように樹脂パッケージ2を成形する.続い
てパンケージ2より引出したり一ドビン6の両端を所定
の長さ寸法に切断〈切断位置を一点鎖線で示す〉し、さ
らにリードピン6の先端部をプレス機7で上下からプレ
スし、この部分に同図(Clに示すような偏平板状の半
田付け脚部6bを成形する.そして、最後に同図(di
のように半田付け脚部6bをバンケージ2の下面側で同
一面上に揃えるようにしてパッケージから引出したりー
ドピン6を内方に向けてヘアピン状にフォーミングする
.
なお、半導体チソプ1とリードピン6の電極ヘッダ68
との間の接合は半田付け以外の方法、例えば圧接法も採
用できる.この場合は、パッケージ2としては、樹脂の
代わりに例えばガラスを用いて封止するのがよい.
次に、第4図と異なる製作方法を第5図に示す.第5図
では、まず同図IJ1),(b)のように半導体チンプ
1とリードピン6との間を接合し、さらにパッケージ2
で封止した後に、同図(elのようにバッケージ2の両
端より出たリードピン6を略直角方向に折り曲げ、続い
て同図1dlのようにリードピン6の先端部にプレス加
工を施して咳部に偏平板状の半田付け脚部6bを形成す
る.そして、最後に同図+a)のように半田付け脚部6
bの面を同一面上に揃えるようにバッケージ2の下面側
へ向けヘアピン状に折り曲げて所定形状にリード成形す
る.また、第6図,第7図は、半導体装置をプリント配
線板に面実装する際の半田付け性を高めるように、あら
かじめリードピンに対して表面処理を施した実施例を示
す.
すなわち、第6図ではパッケージ2より引出したリード
ピン6に対し、その先端部に半田付け脚部をプレス成形
する以前の段階でリードピン6の表面に表面処理を施し
、半田付着性のよい例えば半田ないし銀などの金属被覆
層7を被着したものである.なお、リードピン6の線材
が銅(Cu)を芯材にしてその周面にニッケル(Ni)
メッキしたものである場合には、金属被覆層7(半田)
を被着する際にあらかじめリードピン6の表面を活性の
高いフランクスで処理した後にディッピング.ないしメ
ッキ法により被覆するものとする.なお、前記金属被覆
層7の層屡さが薄いと、次の工程でリードピン6に半田
付け脚部をプレス加工した際の加圧力により金属被覆層
7が局部的に剥がれてリードピン6の下地金属であるニ
ッケル(半田に対して濡れ性が悪い)が露呈し、プリン
ト配線板へ半田付けする際に半田付け不良が生じるおそ
れがある.そこで、前記の金属被覆層7の層厚みを少な
くともlμm以上とすれば、その後にプレス加工を施し
ても金属被覆層7の[111が生じなくなり、プリント
配線板との間で良好な半田つけ性が得られる.すなわち
、第8図はり−ドピン6の表面に半田の金属被覆層7を
被着した後に半田付け脚部をプレス加工を施したものを
試料として、JIS規格C7021,A−2で規定され
ている半田付け性拭験法に基づいて前記試料を半田浴に
浸漬し、同規格3.4項により評価した半田付け性試験
の結果を示すものである.この試験結果から明らかなよ
うに、リードピン6の表面にあらかじめ被着した金属被
覆層(半田)の層厚dが1μm以上であれば「浸漬部分
の半田付着率が9594以上」となり、良好な半田付け
性の得られることが確認されている.なお、金属被覆層
7の層厚さは表面処理時間.コストなどの経済性を考え
ると10μm以下とするのが好ましい.一方、第7図は
リードピン6に対してその先端部に半田付け脚部6bを
プレス加工して成形した後(第4図の《C》,あるいは
第5図1dlの状態)に、その表面に金属被覆層7を被
着させた実施例を示す.このようにリードピン6に対し
て半田付け脚部6bをプレス加工した後に金属被覆層7
を被着させることにより、第6図で述べたようなプレス
加工に伴う金属被覆層7の剥がれの心配が全くなく、半
田付着性がより一層向上する.
次に第1図ないし第3図に示した実施例の応用実施例と
して、バンケージ2の形状を変えた幾つかの変形例を第
9図に示す.すなわち、同図(alは円柱状のパフケー
ジ2の上面一部を平坦面と威し、自動実装機などで半導
体装置を取り扱うに際してパンケージ2を安定よくテー
ピング,ピンクアップできるようにしたものである.ま
た、同rI!J(blは同様な主旨でパフケージ2の外
形を角柱状(四角柱.ないし多角柱)と威したものであ
る.さら“に、同部TC)はパッケージ2の下面両端部
に符号2aで示す凹所を切欠き形成し、この凹所2a内
へヘアピン状に屈曲したリードピン6の半田付け脚部6
bの先端部分をバフケージ2の下面と同一面上に揃えて
収めるようにしたものであり、この構造により半導体装
置をプリント配線板に実装する際の搭載姿勢の安定化が
図れる他、取扱い時に半田付け脚部6bが外力を受けて
不要に変形するのを保護できる.また、同図(dlは(
C)図で述べた凹所2aをパンケージ2(四角柱状)の
各辺に形成したものであり、例えば自動リード曲げ機で
リードピン6を屈曲成形する工程(第4図《d》)ある
いは第5図(C))で、パッケージ2の方向を自由に選
択できる利点が得られる.
〔発明の効果〕
本発明の二端子面実装形半導体装置は、以上説明したよ
うに構威されているので、次記の効果を奏する.
(1)リードピンの先端部にプレス加工を施して偏平な
半田付け脚部を成形するとともに、咳半田付け脚部の板
面を同一面上に揃えてパッケージの両端から引出した各
リードピンをヘアピン状に成形したことにより、特注晶
の高価な専用リードフレームを用いることなく、在来の
同紬リード形半導体素子と同様に安価な丸線材のリード
ピンを採用しつつ、当咳半導体装置をプリント配線板に
対し安定よく搭載して面実装を行うことができる.(2
)パッケージより引出したリードピンに対し、半田付け
脚部をプレス成形する以前.ないし以後の状態でその表
面に半田付着性のよい金属被覆層を被着しておくことに
より、プリント配線板へ半田付け接合する際に良好な半
田付け性が確保できる.また、特にリードピンに半田付
け脚部をプレス成形する以前に金属被覆層を被着する場
合には、咳金属被覆層の層厚を1〜10μmとして十分
な層厚を確保してお《ことにより、次のプレス工程で金
属被覆層が局部的に剥がれてリードピンの下地金属が露
出するなどのトラブルのおそれがなく、安定した半田付
け性が得られる.
{3》かくして、安価な製造コストでプリント配綿板へ
安定よく面実装し、かつ良好な半田付け性の得られる二
端子面実装形半導体装置を提供することができる.By the way, in the surface mount type semiconductor device of the conventional structure described above, the manufacturing process is difficult. There are also the following difficulties in handling the product. That is, 11) Since the structure uses a custom-made lead frame 5 and mounts the semiconductor chip l thereon, the manufacturing cost of the lead frame including the mold is high, and the cost is high. (2) ) Mount the semiconductor chip 1 on the lead frame with the lead piece 3
In order to connect to the lead frame 5, an auxiliary lead piece 4. A soldering process is also required. 《3) During the manufacturing process, individual semiconductor devices are mounted on side rails on a lead frame. Because they are connected together by tie bars, it is not possible to conduct individual characteristic tests on the lead frame before it is cut. The present invention has been made in consideration of the above points, and an object of the present invention is to provide a two-terminal surface-mounted semiconductor device that can be manufactured at low cost by solving the problems of the conventional structure described above. Means for Solving CRB] In order to solve the above 1jlM, a two-terminal surface mount type semiconductor device according to the present invention includes a semiconductor chip sealed in a package, and a semiconductor chip sealed in a package from both ends of the package with the semiconductor chip sandwiched in the center. It consists of an assembly with a lead pin pulled out on pongee.
In addition, the tips of the lead pins are pressed to form flat soldering legs, and the plate surfaces of the core soldering legs are aligned on the same plane, and each lead pin pulled out from both ends of the package is shaped into a hairpin shape. I will give you a precept.
In addition, in order to improve the solderability when surface-mounting the semiconductor device of the above structure onto a printed wiring board, a layer thickness of 1 to 10 μm is applied to the surface of the lead pin before pressing the tip of the lead pin. A metal coating layer with good solder adhesion can be formed. Further, for the same purpose, after pressing a soldering leg on the tip of a lead pin, a metal coating layer with good solder adhesion can be formed on the surface of the soldering leg. [Function] With the above structure, without using a lead frame,
Similar to the conventional pongee lead type semiconductor device, a lead terminal structure that allows surface mounting is obtained by using a nine-wire glued bin for the leads. In particular, the tip of the lead pin is pressed to form a flat plate-shaped soldering leg, allowing stable surface mounting on the printed wiring root. In addition, before pressing the tip of the lead pin in the above structure, a metal material with good solder adhesion and having a sufficient thickness of 1 to 10 μm is applied to the surface of the lead pin. For example, by applying a metal coating layer such as solder or silver,
Even if press processing is applied to the tip of the lead pin after that, the gold is still intact! The AN does not peel off and the underlying metal of the lead pin is exposed, and soldering can be performed with good adhesion to the printed wiring board. Note that this metal coating layer can be easily formed by surface treatment such as dipping or plating. Furthermore, if a metal coating layer with good solder adhesion is formed on the surface of the soldering leg after pressing the soldering leg at the tip of the lead pin, soldering can be performed without being affected by the pressing process. The metal coating layer can be stably adhered to the legs, and it can be soldered with good adhesion to the printed wiring board. [Examples] Examples of the present invention will be described below based on the drawings. first,
1 to 3 show the structure of an embodiment of the present invention. In the figures, 1 is a semiconductor chip, 2 is a resin puff cage that seals the periphery of the semiconductor chip 1, and 6 is a resin puff cage with the semiconductor chip 1 in the center. These are nine-line lead pins that are sandwiched and pulled out from both ends of the pan cage 2 on the same side. In addition, cough lead pin 6
On the other hand, a flange disk-shaped electrode header 6a is formed by press processing on the joint end surface with the semiconductor chip 1, and a flat plate-shaped soldering leg 6b is attached to the tip pulled out from the package 2.
is formed, and the lead pin 6 is bent into a hairpin shape by forming so that the masks of the soldering legs 6b are aligned on the same plane on the lower surface side of the buff cage 2. A surface mount type semiconductor VT device with such a structure is
When mounting on a printed wiring board, the soldering legs 6b in the shape of a flat plate are mounted on the board with the flat plate-shaped soldering legs 6b facing downward, and the soldering is performed by soldering reflow or the like. Next, a method for manufacturing a semiconductor device having the above structure will be explained with reference to FIG. First, an electrode pin 6a is press-molded in advance on one end of a lead pin 6 cut to an appropriate length from a nine-wire wire.
As shown in FIG. 1a), two lead pins 6 are arranged coaxially on both sides of the semiconductor chip 1 with the semiconductor chip 1 sandwiched in the center, and the semiconductor chip 1 and the electrode header 6a are joined by soldering or the like.
Next, in the same figure (as shown in BL, the semiconductor chip 1 and the lead pin 6
The assembly is inserted into a mold, and a resin package 2 is formed so as to seal the periphery of the semiconductor chip. Next, the lead pin 6 is pulled out from the pan cage 2, and both ends of the lead pin 6 are cut to a predetermined length (the cutting positions are indicated by the dashed line), and the tip of the lead pin 6 is pressed from above and below with the press 7, and this part is A flat plate-shaped soldering leg 6b as shown in the same figure (Cl) is formed.Finally, the same figure (di
Pull out the soldering legs 6b from the package so that they are flush with the lower surface of the bankage 2, or form them into a hairpin shape with the soldering pins 6 facing inward as shown in the figure. In addition, the electrode header 68 of the semiconductor chip 1 and the lead pin 6
Methods other than soldering, such as pressure welding, can also be used to connect the parts. In this case, it is preferable to seal the package 2 using, for example, glass instead of resin. Next, Fig. 5 shows a manufacturing method different from Fig. 4. In FIG. 5, first the semiconductor chip 1 and the lead pin 6 are bonded as shown in IJ1) and (b) of the same figure, and then the package 2
After sealing, the lead pins 6 protruding from both ends of the package 2 are bent approximately at right angles as shown in the figure (el), and then the tips of the lead pins 6 are pressed to form a cough part as shown in the figure 1dl. Form the soldering leg portion 6b in the shape of a flat plate.Finally, as shown in +a) of the same figure, the soldering leg portion 6b is formed.
Form the lead into a predetermined shape by bending it into a hairpin shape toward the bottom of the package 2 so that the sides b are on the same plane. Moreover, FIGS. 6 and 7 show an example in which lead pins are surface-treated in advance to improve solderability when surface-mounting a semiconductor device on a printed wiring board. That is, in FIG. 6, the surface of the lead pin 6 pulled out from the package 2 is subjected to a surface treatment before the soldering legs are press-molded on the tip of the lead pin 6. It is coated with a metal coating layer 7 made of silver or the like. Note that the wire of the lead pin 6 has copper (Cu) as its core material and nickel (Ni) on its surrounding surface.
If it is plated, metal coating layer 7 (solder)
When attaching the lead pin 6, the surface of the lead pin 6 is treated with a highly active Franks and then dipped. It shall be covered by a plating method. Note that if the thickness of the metal coating layer 7 is thin, the metal coating layer 7 may be locally peeled off due to the pressing force when the soldering legs are pressed onto the lead pin 6 in the next step, and the base metal of the lead pin 6 may be peeled off locally. Nickel (which has poor wettability with solder) is exposed, and there is a risk of soldering failure when soldering to a printed wiring board. Therefore, if the thickness of the metal coating layer 7 is at least 1 μm or more, [111] will not occur in the metal coating layer 7 even if press working is performed thereafter, and good solderability with the printed wiring board will be achieved. is obtained. In other words, a sample is prepared by applying a metal coating layer 7 of solder to the surface of the beam-doped pin 6 shown in FIG. This table shows the results of a solderability test in which the sample was immersed in a solder bath based on the solderability wiping test method and evaluated in accordance with Section 3.4 of the same standard. As is clear from this test result, if the layer thickness d of the metal coating layer (solder) previously deposited on the surface of the lead pin 6 is 1 μm or more, the solder adhesion rate of the immersed part is 9594 or more, which means that the solder is good. It has been confirmed that it provides good adhesion. Note that the layer thickness of the metal coating layer 7 depends on the surface treatment time. Considering economic efficiency such as cost, it is preferable to set the thickness to 10 μm or less. On the other hand, FIG. 7 shows the surface of the lead pin 6 after the soldering leg 6b is press-formed on the tip of the lead pin 6 (the state shown in ``C'' in FIG. 4 or 1dl in FIG. 5). An example in which a metal coating layer 7 is deposited is shown. After pressing the soldering legs 6b to the lead pins 6 in this way, the metal coating layer 7 is
By depositing the metal coating layer 7, there is no fear of the metal coating layer 7 peeling off during press working as described in FIG. 6, and the solder adhesion is further improved. Next, as applied examples of the embodiments shown in FIGS. 1 to 3, several modified examples in which the shape of the bunkage 2 is changed are shown in FIG. 9. In other words, in the figure (al), a part of the upper surface of the cylindrical puff cage 2 is made flat, so that the pan cage 2 can be stably taped and pinked up when handling semiconductor devices with an automatic mounting machine or the like. In addition, the same rI!J (bl means the same idea, with the outer shape of the puff cage 2 being prismatic (square prism. or polygonal prism). Furthermore, the same part TC) means both ends of the bottom surface of the package 2. A recess indicated by reference numeral 2a is cut out in the recess 2a, and the soldering leg 6 of the lead pin 6 is bent into the recess 2a in a hairpin shape.
The tip of b is placed flush with the bottom surface of buff cage 2, and this structure not only stabilizes the mounting posture when mounting semiconductor devices on a printed wiring board, but also prevents soldering during handling. It is possible to protect the attached leg portion 6b from being unnecessarily deformed due to external force. In addition, the same figure (dl is (
C) The recesses 2a described in the figure are formed on each side of the pan cage 2 (quadrangular prism shape). For example, the process of bending the lead pin 6 with an automatic lead bending machine (Fig. Figure (C)) provides the advantage of being able to freely select the direction of the package 2. [Effects of the Invention] Since the two-terminal surface mount semiconductor device of the present invention is constructed as described above, it achieves the following effects. (1) Press the tips of the lead pins to form flat soldering legs, align the plate surfaces of the soldering legs on the same plane, and pull out each lead pin from both ends of the package into a hairpin shape. By molding the semiconductor device into a printed wiring board, it is possible to use the same inexpensive round wire lead pins as conventional lead-type semiconductor devices without using an expensive dedicated lead frame made of custom-made crystals. It is possible to stably mount the device on the surface and perform surface mounting. (2
) Before pressing the soldering legs onto the lead pins pulled out from the package. By applying a metal coating layer with good solder adhesion to the surface in the subsequent state, good solderability can be ensured when soldering to a printed wiring board. In addition, especially when applying a metal coating layer to the lead pin before press-forming the soldering legs, the thickness of the metal coating layer should be set to 1 to 10 μm to ensure a sufficient layer thickness. , there is no risk of problems such as the metal coating layer peeling off locally during the next pressing process and the underlying metal of the lead pin being exposed, and stable solderability can be achieved. {3} In this way, it is possible to provide a two-terminal surface-mounted semiconductor device that can be stably surface-mounted on a printed cotton distribution board at a low manufacturing cost and has good solderability.
第1図は本発明一実施例の構造を示す一部切欠側面図、
第2図.第3図は第1図の端面図,底面図、第4図(a
l〜+dlは第1図の製造工程図、第5図ta+〜《e
)は第4図と異なる製造工程図、第6図,第7図はそれ
ぞれリードピンに半田付着性のよい金属層を被着した実
施例の斜視断面図、第8図は第6図に対応する半田付け
付性試験結果を表した特性図、第9図(a)〜(ロ)は
それぞれ本発明の異なる応用実施例を示す外形図、第1
0図は従来における二端子面実装形半導体装置の斜視構
造図、第11図(a)〜(d)は第10図に示した半導
体装置の製造工程図である.図において、
1:半導体チップ、2:パッケージ、6:りードビン、
6b:半田付け脚部、7:金属被覆層.第3図
I4rl1
0
15図
第8図
第10図FIG. 1 is a partially cutaway side view showing the structure of one embodiment of the present invention;
Figure 2. Figure 3 shows the end view and bottom view of Figure 1, and Figure 4 (a).
l~+dl are the manufacturing process diagrams in Figure 1, and ta+~《e in Figure 5.
) is a manufacturing process diagram different from Figure 4, Figures 6 and 7 are perspective cross-sectional views of an example in which a metal layer with good solder adhesion is applied to the lead pin, respectively, and Figure 8 corresponds to Figure 6. Characteristic diagrams showing the solderability test results, Figures 9(a) to 9(b) are external diagrams showing different application examples of the present invention, and Figure 1
0 is a perspective structural diagram of a conventional two-terminal surface mount type semiconductor device, and FIGS. 11(a) to 11(d) are manufacturing process diagrams of the semiconductor device shown in FIG. In the figure, 1: semiconductor chip, 2: package, 6: lead bin,
6b: soldering leg, 7: metal coating layer. Figure 3 I4rl1 0 15 Figure 8 Figure 10
Claims (1)
ップを中央に挟んでパッケージの両端から同軸上に引出
したリードピンとの組立体としてなり、かつリードピン
の先端部にプレス加工を施して偏平な半田付け脚部を成
形するとともに、該半田付け脚部の板面を同一面上に揃
えてパッケージの両端から引出した各リードピンをヘア
ピン状に成形してなることを特徴とする二端子面実装形
半導体装置。 2)請求項1に記載の半導体装置において、リードピン
の先端部をプレス加工する以前に、リードピンの表面に
層厚さが1〜10μmである半田付着性のよい金属被覆
層を被着形成したことを特徴とする二端子面実装形半導
体装置。 3)請求項1に記載の半導体装置において、リードピン
の先端部に半田付け脚部をプレス加工した後に、該半田
付け脚部の表面に半田付着性のよい金属被覆層を被着形
成したことを特徴とする二端子面実装形半導体装置。[Claims] 1) It is an assembly of a semiconductor chip sealed in a package and lead pins pulled out coaxially from both ends of the package with the semiconductor chip sandwiched in the center, and the tips of the lead pins are pressed. is applied to form a flat soldering leg, and each lead pin pulled out from both ends of the package is formed into a hairpin shape with the plate surfaces of the soldering leg aligned on the same plane. Two-terminal surface-mount semiconductor device. 2) In the semiconductor device according to claim 1, a metal coating layer having a thickness of 1 to 10 μm and having good solder adhesion is formed on the surface of the lead pin before pressing the tip of the lead pin. A two-terminal surface-mount semiconductor device characterized by: 3) In the semiconductor device according to claim 1, after the soldering leg is pressed onto the tip of the lead pin, a metal coating layer with good solder adhesion is formed on the surface of the soldering leg. A two-terminal surface-mount semiconductor device with special features.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/514,018 US5107324A (en) | 1989-04-27 | 1990-04-26 | Two-terminal semiconductor device of surface installation type |
KR1019900005938A KR930002809B1 (en) | 1989-04-27 | 1990-04-27 | Two-terminal semiconductor device of surface installation type |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1-108531 | 1989-04-27 | ||
JP01108531 | 1989-04-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0348452A true JPH0348452A (en) | 1991-03-01 |
JP2560869B2 JP2560869B2 (en) | 1996-12-04 |
Family
ID=14487166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1339506A Expired - Fee Related JP2560869B2 (en) | 1989-04-27 | 1989-12-27 | Two-terminal surface mount semiconductor device |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2560869B2 (en) |
KR (1) | KR930002809B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009049272A (en) * | 2007-08-22 | 2009-03-05 | Mitsubishi Electric Corp | Semiconductor device, and its manufacturing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58147233U (en) * | 1982-03-26 | 1983-10-03 | マルコン電子株式会社 | Chip type electronic components |
JPS63119231U (en) * | 1987-01-28 | 1988-08-02 |
-
1989
- 1989-12-27 JP JP1339506A patent/JP2560869B2/en not_active Expired - Fee Related
-
1990
- 1990-04-27 KR KR1019900005938A patent/KR930002809B1/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58147233U (en) * | 1982-03-26 | 1983-10-03 | マルコン電子株式会社 | Chip type electronic components |
JPS63119231U (en) * | 1987-01-28 | 1988-08-02 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009049272A (en) * | 2007-08-22 | 2009-03-05 | Mitsubishi Electric Corp | Semiconductor device, and its manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
KR900017161A (en) | 1990-11-15 |
JP2560869B2 (en) | 1996-12-04 |
KR930002809B1 (en) | 1993-04-10 |
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