JPH02184059A - Mini-mold type semiconductor device and lead frame and manufacture of mini-mold type semiconductor device - Google Patents
Mini-mold type semiconductor device and lead frame and manufacture of mini-mold type semiconductor deviceInfo
- Publication number
- JPH02184059A JPH02184059A JP408389A JP408389A JPH02184059A JP H02184059 A JPH02184059 A JP H02184059A JP 408389 A JP408389 A JP 408389A JP 408389 A JP408389 A JP 408389A JP H02184059 A JPH02184059 A JP H02184059A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lead
- mini
- groove
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 36
- 229920005989 resin Polymers 0.000 claims abstract description 7
- 239000011347 resin Substances 0.000 claims abstract description 7
- 238000000465 moulding Methods 0.000 claims abstract description 4
- 238000005520 cutting process Methods 0.000 claims abstract description 3
- 238000005452 bending Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 2
- 238000007598 dipping method Methods 0.000 abstract 2
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は信頼性の高い実装、特に表面実装が可能な半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device that can be mounted with high reliability, particularly surface-mounted.
（ロ）従来の技術
近年、電子機器の小型化・高機能化に伴って半導体装置
にも一層軽薄短小化が望まれている。前記軽薄短小化を
実現する１つの手段として、プリント基板の電極パター
ン上に外部接続リードを対向接着する表面実装型のパッ
ケージが開発されている。(b) Prior Art In recent years, as electronic devices have become smaller and more sophisticated, semiconductor devices have also been desired to be smaller and lighter. As one means for achieving the above-described reduction in weight, thickness, and size, a surface-mount package has been developed in which external connection leads are bonded facing each other on the electrode pattern of a printed circuit board.
表面実装用にリードフォーミングされた樹脂封止型半導
体装置の例としては、所謂ミニモールド型トランジスタ
が挙げられる。（例えば、特願昭６３−１７８８０８）
この様な半導体装置の製造は、一般に肉厚０．１〜０．
３１１１１１の銅系又は鉄系合金から成る板状材料を第
３図に示すような形状に抜き金型で打抜き加工（スタン
ピング）したリードフレーム（１）を使用し、このリー
ドフレーム（１）に半導体チップ（２）をダイボンド、
ワイヤボンドし、エポキシ樹脂（３）等により主要部を
樹脂モールドし、リード（４）を半田ディップした後側
々に分割していた。An example of a resin-sealed semiconductor device lead-formed for surface mounting is a so-called mini-mold transistor. (For example, patent application No. 63-178808)
The manufacturing of such semiconductor devices generally has a wall thickness of 0.1 to 0.
A lead frame (1) is used, which is stamped from a plate-shaped material made of copper-based or iron-based alloy No. 311111 using a die as shown in Figure 3. Die bond the chip (2),
Wire bonding was performed, the main part was resin molded with epoxy resin (3), etc., and the leads (4) were dipped with solder and then divided into sides.
（ハ）発明が解決しようとする課題
しかしながら、ミニモールド型トランジスタの接続リー
ド（４）はそれ自体が０，２〜ｏ、ｓｍｍと極めて小さ
いサイズである為、またリードフレーム（１）の抜きパ
リの影響等で半田層が厚く付着せず、膜厚が２〜３μｍ
と極めて薄くしかメツキできない、従ってプリント基板
への実装時に濡れ性が劣化し、接着強度の信頼性低下を
招く欠点があった。(c) Problems to be Solved by the Invention However, since the connecting lead (4) of the mini-mold transistor itself is extremely small in size, 0.2~0.smm, and the lead frame (1) is The solder layer does not adhere thickly due to the influence of
This has the disadvantage that it can only be plated extremely thinly, resulting in poor wettability when mounted on a printed circuit board, leading to a decrease in reliability of adhesive strength.
＜二）課題を解決するための手段
本発明は上記従来の欠点に鑑み成されたもので、接続リ
ード（１４）の先端部分に溝（１７）を設けると共に、
半田の表面張力により溝（１７）の凹んだ部分に半田（
２０）を厚く付着させることにより、従来の欠点を改善
したミニモールド型半導体装置とリードフレーム、およ
びミニモールド型半導体装置の製造方法を提供するもの
である。<2) Means for Solving the Problems The present invention has been made in view of the above conventional drawbacks, and includes providing a groove (17) at the tip of the connection lead (14),
Due to the surface tension of the solder, the solder (
The present invention provides a mini-mold type semiconductor device and a lead frame, and a method for manufacturing a mini-mold type semiconductor device, which improve the conventional drawbacks by thickly adhering 20).
（＊）作用
本発明によれば、接続リード（１４）の先端部分に階段
状の凹みを有するので、溶融半田の表面張力により、前
記凹み部分に半田層（２０）が厚く付着する。従って、
厚く付着した部分を接続リード（１４）の先端となるよ
うに接続リード（１４）を切断することにより、信頼性
の高い表面実装が可能になる。(*) Function According to the present invention, since the tip portion of the connection lead (14) has a stepped recess, the solder layer (20) thickly adheres to the recessed portion due to the surface tension of the molten solder. Therefore,
By cutting the connection lead (14) so that the thickly adhered portion becomes the tip of the connection lead (14), highly reliable surface mounting becomes possible.
（へ）実施例 以下に本発明を図面を参照しながら詳細に説明する。(f) Example The present invention will be explained in detail below with reference to the drawings.
第１図は本発明のリードフレームを示し、このリードフ
レーム〈１１）は肉厚０．１〜Ｑ、３ｍｍの銅系又は鉄
系合金から成る板状材料をスタンピングにより打ち抜き
加工して得られ、その表面にはＡｇ、Ｎｉ等の金属メツ
キ処理が成される。（１２）は素子形成が終了した半導
体チップ（１３）を載置するリードフレーム（１１）の
タブ部、（１４）はタブ部（１３）に先端を近接する外
部接続用のリード、（１５〉はタブ部（１２）と接続リ
ード（１４）とを連結保持する２本の連結細条、（１６
〉はタイバーである。FIG. 1 shows a lead frame of the present invention, and this lead frame (11) is obtained by stamping a plate-shaped material made of copper or iron alloy with a wall thickness of 0.1 to Q and 3 mm. The surface is plated with a metal such as Ag or Ni. (12) is a tab portion of a lead frame (11) on which a semiconductor chip (13) on which element formation has been completed is placed; (14) is a lead for external connection whose tip is close to the tab portion (13); (15) (16) are two connecting strips that connect and hold the tab portion (12) and the connecting lead (14).
〉 is a tie bar.
接続リード（１４）の根元付近には、左右対称となる位
置に溝（１７）が設けられ、この部分ではリード幅が他
よりも狭くなるように打ち抜かれる。溝（１４）の角は
、できる限り直角に近い鋭角で構成することが後で述べ
る溶融半田の表面張力による半田の付着を助長する。Grooves (17) are provided in symmetrical positions near the base of the connection lead (14), and the grooves (17) are punched out so that the width of the lead is narrower in this part than in other parts. The corners of the grooves (14) are configured to have acute angles as close to right angles as possible to promote adhesion of the solder due to the surface tension of the molten solder, which will be described later.
本願発明の製造方法は、まず上記構成のリードフレーム
（１１）のタブ部（１２）に対してＡｇペースト、Ａｕ
／Ｓｉ共晶等のロウ材を用いて半導体チップ（１３）を
グイボンドし、次いで半導体チップ（１３）表面の電極
と接続リード（１４）とを金属細線（１８）でワイヤボ
ンドし、半導体チップ（１３）を含む主要部を熱硬化性
樹脂（１９）で樹脂モールドする。そして、樹脂モール
ドが終了したリードフレーム（１１）ヲ２５０〜４００
°Ｃの温度で溶融した溶融半田槽へ浸し、接続リード（
１４）へ半田ディップ処理を行う。In the manufacturing method of the present invention, first, Ag paste is applied to the tab portion (12) of the lead frame (11) having the above structure.
The semiconductor chip (13) is bonded using a brazing material such as /Si eutectic, and then the electrodes on the surface of the semiconductor chip (13) and the connection leads (14) are wire-bonded with thin metal wires (18). The main parts including 13) are molded with thermosetting resin (19). Then, the lead frame (11) after resin molding is 250~400 yen.
Immerse the connecting lead (
14) Perform solder dip processing.
斯様に半田ディップ処理が成されたリードフレーム（１
１）は第２図に示す様に、連結細条（１５）、タイバー
（１６）、および接続リード（１４）の全ての表面に膜
厚２〜３μｍの半田層が付着されると同時に、接続リー
ド（１４）の溝（１７）へは溶融半田の表面張力により
、同図に示す様に半田（２０）が他よりも厚く付着する
。特に鋭角に切り取られた溝（１７）の角の凹んだ部分
には、大体５〜１０μｍの厚さに半田（２０）が付着す
る。溝（１７）の中央部分ではこれよりも薄くなる。そ
して、前記半田（２０）が厚く付着した部分が接続リー
ド（１４）の先端となるように図示切り取り線（２１）
で接続リード（１４）を切断し、半導体装置を個々に分
断すると共に接続リード（１４）のフォーミングを行っ
て接続リード（１４）を表面実装に適したＺ型形状に折
り曲げる。A lead frame (1
1) As shown in Fig. 2, a solder layer with a thickness of 2 to 3 μm is attached to all surfaces of the connecting strip (15), tie bar (16), and connection lead (14), and at the same time the connection is made. Due to the surface tension of the molten solder, the solder (20) adheres to the groove (17) of the lead (14) thicker than other parts, as shown in the figure. In particular, the solder (20) is adhered to a thickness of about 5 to 10 μm on the recessed corners of the groove (17) cut at an acute angle. The central portion of the groove (17) is thinner than this. Then, mark the cutout line (21) so that the part to which the solder (20) is thickly adhered becomes the tip of the connection lead (14).
The connection leads (14) are cut, the semiconductor device is individually divided, and the connection leads (14) are formed and bent into a Z-shape suitable for surface mounting.
上記本願の製造方法によって得られた半導体装置は第３
図に示すように、装置本体（２２）の側面から導出され
た接続リード（１４）が２型に折り曲げられ、接続リー
ド（１４）の先端は溝（１７）の途中で切り取られるの
でリード幅が根元部分よりも細い形状を成す。そして、
階段状に細くなった接続リード（１４）先端の側面には
、上記半田ディップ処理により付着された厚い半田（２
０）が残る。The semiconductor device obtained by the manufacturing method of the present application is the third
As shown in the figure, the connection lead (14) led out from the side of the device body (22) is bent into a 2-shape shape, and the tip of the connection lead (14) is cut off in the middle of the groove (17), so the lead width is reduced. It has a thinner shape than the base. and,
The side surface of the tip of the connection lead (14), which is tapered in a stepped manner, is coated with thick solder (2
0) remains.
従って本願発明によれば、接続リード（１４）の先端付
近に半田（２０）が厚く付着しているので、プリント基
板に対して表面実装を行う際に接続用半田の濡れ性が高
く、その為接着強度及び信頼性の高い半田付表面実装が
行える。Therefore, according to the present invention, since the solder (20) is thickly adhered near the tip of the connection lead (14), the wettability of the connection solder is high when performing surface mounting on a printed circuit board. Can perform surface mounting by soldering with high adhesive strength and reliability.
（ト）発明の効果
以上に説明した通り、本発明によれば溶融半田の表面張
力により溝（１７）を埋めるようにして半田（２０）が
付着するので、接続リード（１４）の先端付近に半田（
２０）を厚く付着することが可能な、ミニモールド型半
導体装置とリードフレーム、およびミニモールド型半導
体装置の製造方法を提供でき、従って信頼性の高い表面
実装ができる半導体装置を提供できる利点を有する。ま
た、溝（１７）の形成はスタンピングと同時的に行える
ので、何ら製造工程を追加せずに済む利点をも有する。(G) Effects of the Invention As explained above, according to the present invention, the solder (20) adheres to fill the groove (17) due to the surface tension of the molten solder, so that the solder (20) is attached near the tip of the connection lead (14). solder(
20) It is possible to provide a mini-mold type semiconductor device, a lead frame, and a method for manufacturing a mini-mold type semiconductor device that can be thickly attached, and therefore, it has the advantage of being able to provide a semiconductor device that can be surface-mounted with high reliability. . Furthermore, since the grooves (17) can be formed simultaneously with the stamping, there is an advantage that no additional manufacturing process is required.
第１図乃至第３図は夫々本発明を説明する為の平面図、
要部拡大平面図、および斜視図、第４図は従来例を説明
する為の平面図である。1 to 3 are plan views for explaining the present invention, respectively;
An enlarged plan view and a perspective view of essential parts, and FIG. 4 are plan views for explaining a conventional example.
Claims (3)
外部接続リードを導出し、該接続リードが半田ディップ
処理されると共にＺ形に折り曲げられた表面実装用のミ
ニモールド型半導体装置において、 前記接続リードの先端付近が段階状にリード幅が狭めら
れ、その凹んだ部分に半田が他よりも厚く付着して成る
ことを特徴とするミニモールド型半導体装置。(1) A mini-mold type semiconductor device for surface mounting in which a plurality of external connection leads are led out from the side of a main body in which a semiconductor chip is sealed, and the connection leads are solder-dipped and bent into a Z shape. A mini-mold type semiconductor device characterized in that the lead width is narrowed stepwise near the tip of the connection lead, and the solder adheres thicker to the recessed portion than to other parts.
に先端を近接する複数本の外部接続リードと、前記タブ
部と接続リードとを保持する２本の連結細条とを備え、 前記連結細条から切離される前記接続リードの予定位置
に、リード幅が他よりも狭くなるような溝部を設けたこ
とを特徴とするミニモールド型半導体装置用のリードフ
レーム。(2) comprising a tab portion to which a semiconductor chip is fixed; a plurality of external connection leads having tips close to the tab portion; and two connecting strips holding the tab portion and the connection leads; A lead frame for a mini-mold type semiconductor device, characterized in that a groove portion is provided at a predetermined position of the connection lead to be separated from the connecting strip so that the width of the lead is narrower than that of other portions.
ド幅が他よりも狭くなるような溝部を設けたリードフレ
ームに対して半導体チップの固着と主要部の樹脂モール
ドを行い、 前記リードフレームの露出した部分に半田 ディップ処理を行うと共に、溶融半田の表面張力により
前記接続リードの溝部に溝を埋めるようにして半田を付
着させ、 前記半田の付着膜厚が薄くなる前記溝部の略中央で前記
接続リードを切断し、且つ前記接続リードの折り曲げを
行うことを特徴とするミニモールド型半導体装置の製造
方法。(3) Fixing the semiconductor chip and resin molding of the main parts to the lead frame, which has a groove in which the lead width is narrower than other parts in the area that is to become the tip of the external connection lead, and molding the main part with resin. A solder dip treatment is performed on the exposed portion, and the surface tension of the molten solder causes the solder to adhere to the groove of the connection lead so as to fill the groove, and the solder is applied approximately at the center of the groove where the solder adhesion film thickness becomes thinner. A method of manufacturing a mini-mold type semiconductor device, comprising cutting a connection lead and bending the connection lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP408389A JPH02184059A (en) | 1989-01-11 | 1989-01-11 | Mini-mold type semiconductor device and lead frame and manufacture of mini-mold type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP408389A JPH02184059A (en) | 1989-01-11 | 1989-01-11 | Mini-mold type semiconductor device and lead frame and manufacture of mini-mold type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02184059A true JPH02184059A (en) | 1990-07-18 |
Family
ID=11574889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP408389A Pending JPH02184059A (en) | 1989-01-11 | 1989-01-11 | Mini-mold type semiconductor device and lead frame and manufacture of mini-mold type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02184059A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760467A (en) * | 1991-09-19 | 1998-06-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device lead frame having sunk die pad portions |
| WO2002101813A1 (en) * | 2001-06-08 | 2002-12-19 | Infineon Technologies Ag | A substrate for mounting a semiconductor device thereon |
| JP2011023736A (en) * | 2010-09-13 | 2011-02-03 | Renesas Electronics Corp | Semiconductor device |
-
1989
- 1989-01-11 JP JP408389A patent/JPH02184059A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760467A (en) * | 1991-09-19 | 1998-06-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device lead frame having sunk die pad portions |
| WO2002101813A1 (en) * | 2001-06-08 | 2002-12-19 | Infineon Technologies Ag | A substrate for mounting a semiconductor device thereon |
| JP2011023736A (en) * | 2010-09-13 | 2011-02-03 | Renesas Electronics Corp | Semiconductor device |
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