JP2002043471A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive thinning by improving mounting and reliability. SOLUTION: A semiconductor device comprises a sealing part 3, a chip support part 1h comprising a tab 1b supporting a semiconductor chip and an insulation tape 1f exposed on the rear face 3a of the sealing part 3 arranged on the rear face, a hanging lead 1e supporting the chip support part 1h and extending straightly, a plurality of leads 1a exposing a face to be connected 1g on the peripheral edge part of the rear face 3a of the sealing part 3, and a bonding wire connecting the pad of the semiconductor chip and the lead 1a. When QFN 5 is mounted on a mounting board, the occurrence of an electric short circuit of the wiring pattern of the mounting board and tab 1b can be prevented because the insulation tape 1f is arranged between the tab 1b and the mounting board, thereby the wiring pattern can be formed on an area corresponding to downward of the tab 1b of QFN 5 in the mounting board, and its mounting can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and more particularly, to a technology effective when applied to improving the mountability and reliability and reducing the size of a small semiconductor device.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

As a miniaturized resin-encapsulated semiconductor device, a CSP (Chip Size Package or Chip Scale Pa) is used.
ckage) or QFN (Quad Flat Non-leaded Packag)
A small semiconductor package called e) having a chip size or slightly larger than a semiconductor chip has been developed.

In the QFN, a plurality of leads are arranged on a peripheral portion of a back surface (a surface on a semiconductor device mounting side) of a sealing portion so as to expose a connection surface thereof. Called shape.

The QFN has a structure in which a tab for supporting the semiconductor chip is exposed on the back surface of the sealing portion, and a structure in which the tab is embedded in the sealing portion and is not exposed.

First, in the QFN having the tab exposed structure, the exposed surface of the tab is plated with metal, and is used for ground connection (power supply connection may be used) or for improving heat dissipation. .

On the other hand, in the QFN having the tab-embedded structure, since the back surface of the sealing portion is reliably insulated, the wiring pattern of the mounting substrate can be formed below the sealing portion of the QFN at the time of mounting on the mounting substrate.

[0008] The structure of QFN assembled using a lead frame is described in, for example, Press Journal Co., Ltd., July 27, 1998, "Monthly Semico".
nector World Special Issue '99 Semiconductor Assembly and Inspection Technology ", pp. 53-57. Further, JP-A-8-83870 discloses a semiconductor device having a tab exposed structure, and JP-A-10-189830. In the official gazette,
A semiconductor device having a buried tab structure is described.

[0009]

However, in the semiconductor device (QFN) having the tab-exposed structure according to the above-described technique, since the metal plating portion of the tab is exposed, the QFN is mounted below the QFN when the QFN is mounted on the mounting board. Causes a problem that a wiring pattern cannot be formed on a mounting board.

Further, a semiconductor device (Q
In FN), since the tab is raised, it is necessary to set the package height high, or reduce the thickness of the semiconductor chip or reduce the wire loop height of the bonding wire. The problem of having to deal with it arises.

Further, in the QFN, since the resin thickness on the back surface of the tab is thin, there is a concern that a package crack on the back surface of the tab due to reflow or temperature cycle.

In addition, there is a problem that the tab location is difficult to stabilize due to the tab raising process.

In the tab embedding structure, the back surface of the tab in the lead frame is half-etched,
Thus, a method of thinning the back surface of the tab and embedding it in the sealing portion can be considered, but there is a problem that the cost of the lead frame is increased by the half etching process.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which improve the mountability and reliability.

Still another object of the present invention is to provide a semiconductor device which is reduced in thickness and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor device of the present invention, a sealing portion formed by sealing a semiconductor chip with a resin, and an insulating portion that supports the semiconductor chip and is exposed on the semiconductor device mounting side surface of the sealing portion. A chip supporting portion having a layer, a plurality of leads arranged such that a surface to be connected is exposed on a surface of the sealing portion on the semiconductor device mounting side, a surface electrode of the semiconductor chip, and the lead corresponding thereto And a conductive member for connecting

According to the present invention, when a semiconductor device is mounted on a mounting board, it is possible to form a wiring pattern on a portion of the mounting board corresponding to the chip supporting portion of the semiconductor device. Can be suppressed, and as a result, the mountability of the semiconductor device can be improved.

Further, a method of manufacturing a semiconductor device according to the present invention
A chip support having an insulating layer and capable of supporting a semiconductor chip, and a step of preparing a lead frame having a plurality of leads arranged around the chip support,
Joining the chip support portion of the lead frame and the semiconductor chip, connecting a surface electrode of the semiconductor chip and the corresponding lead of the lead frame by a conductive member, Exposing the connected surface of the insulating layer and the lead to the surface of the sealing portion on the semiconductor device mounting side to form the sealing portion and resin-seal the semiconductor chip; Cutting and separating from the frame.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is an external perspective view showing an example of the structure of a semiconductor device (QFN) according to a first embodiment of the present invention, and FIG. 2 is a view showing the structure of the QFN shown in FIG. ,
FIG. 3A is a plan view showing the inside, FIG. 3B is a cross-sectional view taken along the line AA of FIG. 3A, FIG. 3 is a bottom view showing the structure of the QFN shown in FIG. FIG. 4 shows the QFN shown in FIG.
FIG. 5 is a partial plan view showing an example of the structure of a lead frame used for assembling the semiconductor device, FIG. 5 is a manufacturing process flow chart showing an example of an assembling procedure in the method for manufacturing the QFN shown in FIG. 2, and FIG. 6 is a modification of the QFN shown in FIG. FIG. 7 is a bottom view showing the structure of the example through the inside, FIG. 7 is a diagram showing the structure of a modification of the QFN of the first embodiment, (a) is a plan view showing the inside through, and (b) is FIG. 8A is a sectional view taken along the line BB of FIG.
9 is a bottom view showing the structure of the QFN of the modification shown in FIG. 7 through the inside, FIG. 9 is a diagram showing the structure of the modification of the QFN of the first embodiment, and FIG. Plan view,
FIG. 10B is a cross-sectional view taken along line CC of FIG.
11 is a bottom view showing the structure of the QFN of the modified example shown in FIG. 11 through the inside, FIG. 11 is a diagram showing the structure of the modified example of the QFN of the first embodiment, and FIG. ,
FIG. 12B is a sectional view taken along the line DD of FIG.
FIG. 13 is a bottom view showing the structure of the QFN of the modification shown in FIG. 1 through the inside, and FIG. 13 is a diagram showing the structure of the modification of the QFN of the first embodiment. FIG. Figure,
FIG. 14B is a sectional view taken along the line EE of FIG.
3 is a bottom view showing the structure of the QFN of the modified example shown in FIG. 3 through the inside, and FIG. 15 is a diagram showing the structure of the modified example of the QFN of the first embodiment. FIG. Figure,
FIG. 16B is a cross-sectional view taken along line FF of FIG.
5 is a bottom view showing the structure of the QFN of the modification shown in FIG. 5 through the inside, and FIG. 17 is a diagram showing the structure of the modification of the QFN of the first embodiment. FIG. Figure,
FIG. 18B is a cross-sectional view, FIG. 18 is a diagram showing a structure of a modification of the semiconductor device of the first embodiment, FIG. 19A is a bottom view showing the inside of the semiconductor device, FIG. 20A and 20B are diagrams showing a structure of a modification of the QFN of the first embodiment, wherein FIG. 20A is a plan view showing the inside thereof, FIG. 20B is a sectional view taken along line GG of FIG. FIG. 21 is a bottom view showing the structure of the QFN of the modification shown in FIG.
It is a figure which shows the structure of the modification of FN, (a) is a bottom view which shows the inside transparently, (b) is sectional drawing, FIG. 22 is a figure which shows the structure of the modification of QFN of Embodiment 1. FIG. 5A is a bottom view showing the inside of the device, and FIG.

The semiconductor device shown in FIG.
The semiconductor device according to the first embodiment is mainly a QFN5 as an example of the semiconductor device.
Is explained.

As shown in the bottom view of FIG. 3, the connection surface 1g of the plurality of leads 1a is formed on the semiconductor device mounting side of the sealing portion 3 formed by resin molding (hereinafter referred to as the back surface). 3a), and is of a peripheral type arranged and exposed along the periphery of each lead 1a.
Are the inner leads embedded in the sealing portion 3 and the sealing portion 3
Has both functions with the outer leads exposed on the back surface 3a.

The structure of the QFN 5 will be described in detail with reference to FIGS. 1 to 4. The sealing portion 3 formed by sealing the semiconductor chip 2 with a resin, the tab 1b for supporting the semiconductor chip 2, and the chip A chip support portion 1h comprising an insulating tape 1f which is disposed on the back surface 1d opposite to the support surface 1c and constitutes an insulating layer exposed on the back surface 3a of the sealing portion 3;
And a suspension lead 1e that supports the chip supporting portion 1h and extends straight, and a plurality of leads as external terminals arranged so that the connected surface 1g is exposed at a peripheral portion of the back surface 3a of the sealing portion 3. 1a and a bonding wire 4 which is a conductive member for connecting a pad 2a which is a surface electrode of the semiconductor chip 2 and a corresponding lead 1a.

That is, as shown in FIGS. 2 and 3, the insulating tape 1f is attached to the back surface 1d of the tab 1b so that the insulating tape 1f is attached to the back surface 3d of the sealing portion 3. Can be configured to be exposed to
Therefore, when QFN5 is mounted on a mounting board,
Since the mounting state is such that the insulating tape 1f is arranged between the tab 1b and the mounting board, it is possible to prevent an electrical short circuit between the wiring pattern of the mounting board and the tab 1b.

Thus, the QFN on the mounting board is
The wiring pattern can also be formed in a region corresponding to the area below the fifth tab 1b. As a result, the mountability of the QFN 5 can be improved.

The chip supporting portion 1h of the QFN 5 according to the first embodiment is composed of a tab 1b and an insulating tape 1f attached to the back surface 1d of the tab 1b.
The semiconductor chip 2 is fixed to the chip supporting surface 1c of the tab 1b with a die bond material such as a silver paste.

The insulating tape 1f is, for example, a polyimide tape or the like, and its thickness (L shown in FIG. 2) is
Although it is about 80 μm, the material, size and thickness of the insulating tape 1f are not particularly limited.

The thickness of the insulating tape 1f is as follows.
After the completion of the wire bonding, the semiconductor chip 2 descends by the thickness of the tape together with the tab 1b, and the stress at that time is applied to the wire bonding portion of the semiconductor chip 2 or the ultrasonic wave or heat generated during the wire bonding. In consideration of conduction, it is preferable that the thickness is as thin as possible.

The QFN 5 is assembled using the lead frame 1 shown in FIG. 4, and the lead frame 1 has an insulating tape 1 on the back surface 1d of the tab 1b.
f is pasted.

Further, in the QFN 5, the suspension leads 1e and the leads 1a extend straight, and are not bent.

Therefore, the lead frame 1 is a flat thin plate and can be manufactured only by pressing, and requires other processing such as etching and bending in addition to the pressing. It can be manufactured at a lower cost than the ones. In addition to the press working, it is possible to manufacture by etching only. However, in view of cost, it is preferable that the manufacturing is performed only by press working.

The lead frame 1 shown in FIG. 4 shows only a package area corresponding to one QFN 5 in a multi-cavity frame in which a plurality of QFNs 5 can be assembled together. The frame 1 may be, for example, one in which a plurality of the package regions are arranged in one column, or one in which a plurality of the package regions are arranged in a matrix in a plurality of columns × a plurality of rows.

The lead frame 1 is made of, for example, copper and has a thickness of about 0.125 to 0.2 mm.

Therefore, the thickness (T shown in FIG. 2) of the tab 1b, the suspension lead 1e, and the lead 1a is, for example, 0.1 mm.
It is about 125 to 0.2 mm.

The bonding wire 4 (conductive member) for connecting the pad 2a of the semiconductor chip 2 and the corresponding lead 1a is, for example, a gold wire.

Further, the sealing portion 3 is formed by resin sealing by a molding method, and a sealing resin (mold resin) used at this time is, for example, a thermosetting epoxy resin.

In the QFN5, for signals except for the suspension leads 1e (here, also for power and ground electrodes)
As shown in FIG. 2A, the width of the lead 1a is different between the tip side and the inside.

That is, in each of the leads 1a, the inner width is wider than the tip side, so that the lead 1a falls out of the sealing portion 3 (drops).
Can be prevented.

The tab 1b in the QFN 5 is shown in FIG.
As shown in FIG. 2B, it is smaller than the semiconductor chip 2 and has a cross shape as shown in FIG. That is, the QFN 5 has a small tab structure.

As a result, the semiconductor chip 2 larger than the tab 1b can be mounted as the semiconductor chip 2 to be mounted, or the semiconductor chip 2 smaller than the tab 1b can be mounted. The degree of freedom can be given to the size of the chip 2.

Further, since the area of the tab 1b having poor adhesion with the mold resin can be reduced as compared with the adhesion between the semiconductor chip 2 and the mold resin, moisture remaining on the mounting surface can be suppressed. And the occurrence of reflow cracks can be prevented.

As shown in FIG. 2 (b), a connection surface 1g of each lead 1a exposed on the peripheral portion of the back surface 3a of the sealing portion 3 is provided for solder connection at the time of mounting on a mounting board. Solder plating 6 is formed.

In place of the solder plating 6, Sn
Plating using a metal other than Sn-Pb eutectic solder such as Ag-based alloy, Sn-Bi-based alloy or palladium (P
d) Plating may be performed, and in that case, lead-free can be realized.

Next, a method of manufacturing the QFN 5 according to the first embodiment will be described with reference to a manufacturing process flow chart shown in FIG.

First, an insulating tape 1f (insulating layer) is attached to the back surface 1d, and a chip supporting portion 1h having a tab 1b capable of supporting the semiconductor chip 2 on a chip supporting surface 1c, and a suspension lead 1e for supporting the same. A lead frame 1 shown in FIG. 4 having a plurality of leads 1a arranged around the chip support 1h is prepared (Step S).
1).

That is, the lead frame 1 shown in FIG. 4 is prepared in which the insulating tape 1f has been previously attached to the back surface 1d of the tab 1b.

On the other hand, after preparing the semiconductor chip 2 having the semiconductor integrated circuit formed on the main surface 2b, the semiconductor chip 2 is supplied. Then, as shown in step S2, the tab of the chip supporting portion 1h of the lead frame 1 is provided. 1b chip support surface 1
die bonding for bonding the semiconductor chip 2 to the back surface 2c of the semiconductor chip 2 is performed.

That is, the semiconductor chip 2 with the main surface 2b facing upward on the tab 1b of the chip supporting portion 1h of the lead frame 1 via a die bond material (for example, silver paste).
Is performed by die bonding (also referred to as pellet bonding or chip mounting).

Thereafter, the pads 2a of the semiconductor chip 2 and the corresponding leads 1a are connected by wire bonding with the bonding wires 4 which are conductive members (step S3).

Thus, the pad 2a of the semiconductor chip 2
And a lead 1a corresponding to the bonding wire 4
Connected by

Thereafter, as shown in step S4, the semiconductor chip 2 is sealed with a resin (here, transfer molding).

At this time, the insulating tape 1f (insulating layer) attached to the back surface 1d of the tab 1b of the chip supporting portion 1h and the connection surface 1g of each lead 1a are sealed as shown in FIGS. The sealing portion 3 is exposed on the back surface 3a of the portion 3.
To form

The insulating tape 1f is exposed substantially at the center of the back surface 3a of the sealing portion 3, and each lead 1a is located outside the periphery of the insulating tape 1f and at the periphery of the back surface 3a of the sealing portion 3. It is exposed to the part.

Thereafter, as shown in step S5, each of the leads 1a and the suspension leads 1e is cut and separated from the lead frame 1 (individualization), whereby the QFN 5 shown in FIGS. 1 to 3 is completed. (Step S6).

QFN 5 (semiconductor device) of the first embodiment
According to the method and the method for manufacturing the same, the following effects can be obtained.

That is, since the chip supporting portion 1h supporting the semiconductor chip 2 has the insulating tape 1f (insulating layer) exposed on the back surface 3a of the sealing portion 3, the wiring pattern of the mounting board on which the QFN 5 is mounted is provided. And the tab 1b and the suspension lead 1e of the QFN5 are separated from each other by a gap corresponding to the thickness of the insulating tape 1f. Therefore, an electric short circuit occurs between the wiring pattern of the mounting board and the tab 1b and the suspension lead 1e of the QFN5. Can be prevented.

As a result, in the mounting board on which the QFN 5 is mounted, the chip supporting portion 1h of the QFN 5 of the mounting board is mounted.
It is also possible to form a wiring pattern at a location corresponding to the above, and it is possible to suppress the occurrence of restrictions in forming a wiring pattern on the mounting board.

Thus, the mountability of the QFN 5 can be improved.

Further, the thickness of the back side of the chip supporting portion 1h can be made smaller than that of a conventional semiconductor device having a buried tab structure, so that the QFN 5 can be made thinner.

Since the suspension lead 1e supporting the chip supporting portion 1h does not bend in the height direction of the semiconductor device as compared with the conventional semiconductor device having the tab-embedded structure, the thickness of the QFN 5 can be reduced. Can be planned.

Since the thickness of the QFN 5 can be made smaller than that of the conventional semiconductor device having the embedded tab structure, the thickness of the QFN 5 can be made the same as that of the conventional semiconductor device having the embedded tab structure. The thickness can be increased.

Furthermore, since the QFN 5 can be made thinner than a conventional semiconductor device having a buried tab structure,
When the thickness of the QFN 5 is the same as that of the conventional tab embedded structure, the margin of the height of the wire loop of the bonding wire 4 can be increased.

When the chip supporting portion 1h has the tab 1b as its configuration, the sealing resin is not disposed on the back surface side of the chip supporting portion 1h, which is caused in a conventional semiconductor device having a tab embedded structure. It is possible to eliminate the occurrence of troubles (resin cracks on the back surface of the tab that occur during reflow or a temperature cycle test) due to the difference in resin balance between the front and back surfaces of the tab.

Thus, the reliability of the QFN 5 can be improved.

Further, compared with a semiconductor device in which the back surface of the tab is half-etched to make the back surface of the tab thinner, the lead frame 1 having a smaller thickness can be used. (Resin) The thickness is also reduced, so that the potential for generation of lead chips due to chipping of the package and scattering of mold resin dust generated at the time of cutting the leads can be reduced.

As a result, the quality and reliability of the QFN 5 can be improved.

Further, the lead frame 1 for assembling the QFN 5 according to the first embodiment can be manufactured by an existing manufacturing technique without introducing new equipment.

The QFN 5 according to the first embodiment can be assembled by an existing manufacturing technique.

Further, in the manufacture of the lead frame 1 for assembling the QFN 5 according to the first embodiment, no other processing is required, and the manufacturing can be performed only by pressing, so that it is inexpensive and has stable quality. The lead frame 1 can be prepared.

Further, since the suspension lead 1e can use the flat lead frame 1 in which no bend is formed, an unstable element of the tab location in assembling the QFN 5 can be removed. Supply becomes possible.

Since the insulating tape 1f can be easily peeled off by using the insulating tape 1f as the insulating layer, the insulating tape 1f can be easily removed at the shipping destination of the QFN5.
Can be peeled off, and as a result, it is easy to peel off the insulating tape 1f at the shipping destination and change to the tab exposed structure.

Next, the structure of a semiconductor device according to a modification of the first embodiment will be described.

First, the QFN 5 of the modified example shown in FIG. 6 is obtained by matching the shape of the insulating tape 1f to the shape of the cross-shaped tab 1b (see FIG. 2).

The modified QFN 5 shown in FIGS. 7A, 7B and 8 is an example in which the size of the insulating tape 1f is larger than that of the tab 1b. The positioning accuracy of the tab 1b and the insulating tape 1f when attaching the insulating tape 1f can be relaxed.

The QFN 5 of the modified example shown in FIGS. 9A, 9B and 10 is an example in which the size of the insulating tape 1f is smaller than that of the tab 1b. Therefore, the cost of the lead frame 1 can be reduced.

In the modified QFN 5 shown in FIGS. 9A and 9B and FIG. 10, since the insulating tape 1f is smaller than the tab 1b, as shown in FIG. Wraps around the back surface of the tab 1b. At this time, there may be a portion around the insulating tape 1f where the back surface 1d of the tab 1b is exposed.

That is, when the QFN 5 is mounted on the mounting substrate, a gap can be formed between the tab 1b and the mounting substrate by the thickness (L) of the insulating tape 1f, so that the back surface 1d of the tab 1b is slightly exposed. May be.

The modified QFN 5 shown in FIGS. 11A, 11B and 12 is an example in which the tab 1b is larger than the semiconductor chip 2 instead of the small tab. This is an example in which an insulating tape 1f having the same size as the tab 1b is attached.

The modified QFN 5 shown in FIGS. 13A, 13B and 14 is an example in which a tab 1b larger than the semiconductor chip 2 is used. In this case, an insulating tape 1f larger than the tab 1b is used. This is an example of pasting.

Further, FIGS. 15A and 15B and FIG.
Is an example in which a tab 1b larger than the semiconductor chip 2 is used, and an insulating tape 1f smaller than the tab 1b is attached at that time.

The QFN 5 of the modified example shown in FIGS. 17A and 17B has a coating layer 1 such as an oxide film, an insulating film or paint as an insulating layer disposed on the back surface 1d of the tub 1b.
i.

The coating layer 1i is, for example, a layer having a thickness of 1 μm or less. Before assembling the QFN 5, the coating layer 1i is formed on the back surface 1d of the tab 1b of the lead frame 1 in advance. 1 to assemble QFN5.

Thus, the height of the QFN 5 can be further reduced by using the coating layer 1i which is much thinner than the insulating tape 1f without using the insulating tape 1f as shown in FIG.

The semiconductor device of the modified example shown in FIGS. 18A and 18B is an example of a ball terminal package 7 in which solder balls 7a are provided as external terminals on a connection surface 1g of a lead 1a.

The modified QFN 5 shown in FIGS. 19 (a), (b) and 20 is an example in which the chip supporting portion 1h is constituted only by the insulating tape 1f which is an insulating layer.
The insulating tape 1f, which is the chip supporting portion 1h, is supported by the suspension leads 1e, and the semiconductor chip 2 is directly fixed to the insulating tape 1f.

As a result, the tab 1b as shown in FIG. 2 can be eliminated, so that the QFN5 shown in FIG. 19 has a thickness QFN5 shown in FIG.
The thickness of N5 can be reduced.

The QFN 5 of the modification shown in FIGS. 21A and 21B is an example in which the chip supporting portion 1h is constituted only by the insulating tape 1f which is an insulating layer.
The insulating tape 1f as the chip supporting portion 1h is supported by e and each lead 1a, and the semiconductor chip 2 is directly fixed to the insulating tape 1f.

Each lead 1a has a notch 1j
By attaching the insulating tape 1f to the notch 1j, the connected surface 1g of each lead 1a can be reliably exposed to the back surface 3a of the sealing portion 3 after molding.

The QFN5 of the modification shown in FIG.
This is an example in which the chip supporting portion 1h is constituted only by the insulating tape 1f which is an insulating layer. Each of the leads 1a supports the insulating tape 1f which is the chip supporting portion 1h, and the semiconductor chip 2 is directly fixed to the insulating tape 1f. Is what it is.

As a result, since there is no suspension lead 1e as shown in FIG. 21, there is a problem that occurs when the suspension lead is cut when cutting the lead. (Because the mold resin is not cut but broken, resin dust is generated. In addition, the vicinity of the suspension lead of the sealing portion 3 may be damaged).

(Embodiment 2) FIGS. 23A and 23B show an example of the structure of a QFN according to Embodiment 2 of the present invention. FIG. 23A is a bottom view showing the inside of the QFN, and FIG. 24 is a manufacturing process flow chart showing an example of an assembling procedure in the method for manufacturing the QFN shown in FIG. 23, and FIG. 25 is a view showing a structure of a modification of the semiconductor device of the second embodiment.
FIG. 2 is a bottom view showing the inside through the inside, and FIG.

As in the semiconductor device of the first embodiment, the semiconductor device of the second embodiment has a QFN having a structure in which the insulating layer of the chip supporting portion 1h is exposed on the back surface 3a of the sealing portion 3.
5, the back surface 3a of the sealing portion 3 as in the first embodiment.
Is a peripheral type in which connected surfaces 1g of a plurality of leads 1a are exposed side by side at the peripheral edge of the lead.

The difference between the QFN 5 of the second embodiment and the QFN 5 of the first embodiment is a procedure for forming an insulating layer on the tab 1b.

That is, in QFN5 of the first embodiment,
When assembling, the tab 1
b, an insulating layer such as an insulating tape 1f or a coating layer 1i is attached or formed (applied). In the QFN 5 of the second embodiment, the back surface 3 of the sealing portion 3 is formed after molding.
The insulating layer is formed on the tub 1b exposed at a.

Therefore, the structure of the QFN 5 of the second embodiment is almost the same as the structure of the QFN 5 of the first embodiment. For example, if the insulating layer is the coating layer 1i,
As shown in FIG. 23B, the structure is such that the thickness of the coating layer 1 i slightly protrudes from the back surface 3 a of the sealing portion 3.

This means that the insulating tape 1f is used as an insulating layer.
Is used, a structure in which the thickness of the insulating tape 1f protrudes from the back surface 3a of the sealing portion 3 is obtained. However, in consideration of the standoff (Z) at the time of mounting the QFN on the mounting board, the second embodiment is used.
In the QFN 5, it is preferable to form the coating layer 1i as an insulating layer.
In (a), when the coating layer 1i is formed (coated) on the exposed portion of the tab 1b, the coating layer 1i is formed as thin as possible so that the standoff (Z)> the thickness (L) of the coating layer 1i is satisfied. Is preferably formed (coated).

However, when soldering the QFN5 to the mounting board, cream solder (for example, about 100 μm thick)
Therefore, the relationship of stand-off (Z)> thickness (L) of the coating layer 1i does not always have to be satisfied.

In the method of manufacturing the QFN 5 according to the present embodiment, as shown in the manufacturing process flow chart of FIG. 24, the lead frame 1 having no insulating layer formed in the preparation of the lead frame 1 in step S11 is prepared. Then, die bonding in step S12 and step S1
The steps up to the wire bonding of step 3 and the molding of step S14 are performed in the same manner as in the first embodiment to expose the tab 1b on the back surface 3a of the sealing portion 3.

After molding (resin sealing), the second embodiment
In QFN5, in forming the insulating layer shown in step S15, the insulating layer is formed by forming the coating layer 1i on the exposed portion of the tab 1b (or by applying a brush or the like) or pasting the insulating tape 1f.

Thereafter, as in the manufacturing method of the first embodiment, the lead is cut (individualized) in step S16 to complete the QFN 5 in step S17.

The other structure and manufacturing method of the QFN 5 according to the second embodiment will be described with reference to the QFN 5 according to the first embodiment.
5, the description thereof is omitted.

Further, the functions and effects obtained by the QFN 5 according to the second embodiment and the method of manufacturing the same are the same as those described in the first embodiment, and a duplicate description thereof will be omitted.

The semiconductor device of the modified example shown in FIGS. 25A and 25B is an example of a ball terminal package 7 in which solder balls 7a are provided as external terminals on a connection surface 1g of a lead 1a. Also in such a semiconductor device, if an insulating layer such as an insulating tape 1f is formed on the exposed portion of the tab 1b after molding, the same operation and effect as those of the ball terminal package 7 shown in FIG. be able to.

Although the invention made by the inventor has been specifically described based on the first and second embodiments of the present invention, the present invention is not limited to the first and second embodiments of the invention. It goes without saying that various changes can be made without departing from the gist of the invention.

For example, in the first and second embodiments, the case where the lead 1a is not bent is described.
The leads 1a other than the suspension leads 1e may be bent in the package height direction.

Further, in the first and second embodiments, the case where the semiconductor device is the peripheral type QFN 5 and the case where the external terminal is the ball terminal package 7 of the solder ball 7a has been described. The semiconductor package may be any other than the QFN5 as long as the package is a resin-sealed type assembled using the semiconductor device 1 and has a structure in which external terminals are arranged on the back surface 3a of the sealing portion 3.

[0109]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). Since the chip supporting portion for supporting the semiconductor chip has an insulating layer exposed on the back surface of the sealing portion, when the semiconductor device is mounted on the mounting substrate, a portion corresponding to the chip supporting portion of the semiconductor device on the mounting substrate It is also possible to form a wiring pattern on the mounting board, and it is possible to suppress the occurrence of restrictions in forming the wiring pattern on the mounting board,
Thereby, the mountability of the semiconductor device can be improved.

(2). Since the thickness of the back surface side of the chip supporting portion can be reduced as compared with the conventional tab embedded structure, the semiconductor device can be made thin. Since the suspension lead does not bend in the height direction of the semiconductor device as compared with the conventional tab embedded structure, the semiconductor device can be made thinner.

(3). Since the thickness can be reduced as compared with the conventional tab embedded structure, when the thickness of the semiconductor device is the same as that of the conventional tab embedded structure, the thickness of the semiconductor chip to be mounted can be increased. At the same time, the height margin of the wire loop can be increased.

(4). When the chip supporting portion has a tab, the sealing resin is not disposed on the back surface side of the chip supporting portion, so that a defect due to a difference in resin balance between the front and back surfaces of the tab occurs in a semiconductor device having a conventional tab embedded structure. Can be eliminated. Thereby, the reliability of the semiconductor device can be improved.

(5). Compared to a semiconductor device in which the back side of the tab is half-etched and the back side of the tab is made thinner, a thinner lead frame can be used, so the resin thickness inside the dam bar after molding also becomes thinner, which occurs when cutting leads. And the potential for generation of lead dents due to scattering of mold chips and scattering of mold resin waste can be reduced. Therefore, the quality and reliability of the semiconductor device can be improved.

(6). The manufacture of the lead frame for a semiconductor device of the present invention can be performed by an existing manufacturing technique without introducing new equipment, and the semiconductor device of the present invention can be assembled by the existing manufacturing technique. It is possible.

(7). In the manufacture of the lead frame for a semiconductor device of the present invention, no other processing is required, and the manufacturing can be performed only by press working. Therefore, an inexpensive and stable lead frame can be prepared. Further, since a flat lead frame in which no bend is formed in the suspension lead can be used, an unstable element of the tab location can be removed, and the lead frame can be stably supplied.

(8). By using the insulating tape as the insulating layer, it is easy to peel off the insulating tape, so it is possible to peel off the insulating tape at the shipping destination. As a result, the insulating tape can be peeled off at the shipping destination to change to a tab exposed structure. Can be easily performed.

[Brief description of the drawings]

FIG. 1 is a semiconductor device (QFN) according to a first embodiment of the present invention.
1 is an external perspective view showing an example of the structure of FIG.

FIGS. 2A and 2B are diagrams showing the structure of the QFN shown in FIG. 1, FIG. 2A is a plan view showing the inside of the QFN, and FIG.
FIG. 2 is a cross-sectional view taken along line AA of FIG.

FIG. 3 is a bottom view showing the structure of the QFN shown in FIG.

FIG. 4 is a partial plan view showing one example of a structure of a lead frame used for assembling the QFN shown in FIG. 2;

5 is a manufacturing process flow chart showing an example of an assembling procedure in the method for manufacturing a QFN shown in FIG. 2;

FIG. 6 is a bottom view showing the structure of a modification of the QFN shown in FIG.

FIGS. 7A and 7B are diagrams showing a structure of a modification of the QFN according to the first embodiment, where FIG. 7A is a plan view showing the inside thereof, and FIG. It is sectional drawing which follows the BB line.

FIG. 8 is a bottom view showing the structure of the QFN of the modification shown in FIG.

FIGS. 9A and 9B are diagrams showing a structure of a modified example of the QFN of the first embodiment, where FIG. 9A is a plan view showing the inside thereof, and FIG. It is sectional drawing which follows CC line.

10 is a bottom view showing the structure of the QFN of the modification shown in FIG.

FIGS. 11A and 11B are diagrams showing a structure of a modification of the QFN of the first embodiment, where FIG. 11A is a plan view showing the inside thereof, and FIG. It is sectional drawing which follows the DD line.

12 is a bottom view showing the structure of the QFN of the modification shown in FIG.

13A and 13B are diagrams showing a structure of a modification of the QFN of the first embodiment, wherein FIG. 13A is a plan view showing the inside of the modification, and FIG. It is sectional drawing which follows the EE line.

14 is a bottom view showing the structure of the QFN of the modification shown in FIG.

FIGS. 15A and 15B are diagrams showing a structure of a modification of the QFN according to the first embodiment, where FIG. 15A is a plan view showing the inside thereof, and FIG. It is sectional drawing which follows the FF line.

16 is a bottom view showing the structure of the QFN of the modification shown in FIG.

17A and 17B are diagrams showing a structure of a modification of the QFN according to the first embodiment, FIG. 17A is a bottom view showing the inside of the QFN, and FIG. .

FIGS. 18A and 18B are diagrams showing a structure of a modification of the semiconductor device of the first embodiment, wherein FIG. 18A is a bottom view showing the inside of the semiconductor device, and FIG. is there.

19A and 19B are diagrams showing a structure of a modification of the QFN according to the first embodiment, wherein FIG. 19A is a plan view showing the inside of the modification, and FIG. It is sectional drawing which follows the GG line.

FIG. 20 is a bottom view showing the structure of the QFN of the modification shown in FIG. 19 through the inside;

FIGS. 21A and 21B are diagrams showing a structure of a modification of the QFN of the first embodiment, wherein FIG. 21A is a bottom view showing the inside thereof, and FIG. .

22 (a) and (b) are diagrams showing a structure of a modification of the QFN of the first embodiment, (a) is a bottom view showing the inside of the QFN, and (b) is a sectional view. .

FIGS. 23 (a) and (b) are QFs according to the second embodiment of the present invention.
It is a figure which shows an example of the structure of N, (a) is a bottom view which shows the inside transparently, (b) is sectional drawing.

24 is a manufacturing process flow chart showing an example of an assembling procedure in the method for manufacturing the QFN shown in FIG. 23.

25A and 25B are diagrams showing a structure of a modification of the semiconductor device of the second embodiment, wherein FIG. 25A is a bottom view showing the inside of the semiconductor device, and FIG. is there.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Lead (external terminal) 1b Tab 1c Chip supporting surface 1d Back surface (opposite surface) 1e Suspended lead 1f Insulating tape (insulating layer) 1g Connected surface 1h Chip supporting portion 1i Coating layer (insulating layer) 1j Cutting Notch 2 Semiconductor chip 2a Pad (surface electrode) 2b Main surface 2c Back surface 3 Sealing portion 3a Back surface (surface on semiconductor device mounting side) 4 Bonding wire (conductive member) 5 QFN (semiconductor device) 6 Solder plating 7 Ball terminal package (Semiconductor device) 7a Solder ball (external terminal)

Claims (5)

[Claims] 1. A resin-sealed semiconductor device, comprising: a sealing portion formed by resin-sealing a semiconductor chip; and a surface of the sealing portion supporting the semiconductor chip on a semiconductor device mounting side. A chip supporting portion having an insulating layer exposed to the semiconductor device; a plurality of leads arranged so that a surface to be connected is exposed on a surface of the sealing portion on the semiconductor device mounting side; a surface electrode of the semiconductor chip; A conductive member for connecting to the corresponding lead. 2. A resin-sealed semiconductor device, comprising: a sealing portion formed by resin-sealing a semiconductor chip; a tab for supporting the semiconductor chip; and a tab opposite to the chip supporting surface. A chip support portion comprising an insulating tape disposed on a surface and forming an insulating layer exposed on the semiconductor device mounting side surface of the sealing portion; and a suspension lead that supports the chip support portion and extends straight. A plurality of external terminals having exposed surfaces disposed at a peripheral portion of the surface of the sealing portion on the semiconductor device mounting side, and a plurality of external terminals; and a surface electrode of the semiconductor chip and the corresponding lead. And a conductive member for connecting the semiconductor device. 3. A resin-sealed semiconductor device, comprising: a sealing portion formed by resin-sealing a semiconductor chip; a tab for supporting the semiconductor chip; and a tab opposite to the chip supporting surface. A chip supporting portion formed on a surface and a coating layer that is an insulating layer exposed on a surface of the sealing portion on the semiconductor device mounting side; and a suspension lead that supports the chip supporting portion and extends straight, A plurality of external terminal leads arranged so as to be exposed at a peripheral portion of the semiconductor device mounting side surface of the sealing portion; and a surface electrode of the semiconductor chip and the corresponding lead. A semiconductor device having a conductive member to be connected. 4. A step of preparing a lead frame having an insulating layer and a chip supporting portion capable of supporting a semiconductor chip, and a plurality of leads arranged around the chip supporting portion; A step of joining a chip supporting portion and the semiconductor chip, a step of connecting a surface electrode of the semiconductor chip and the corresponding lead of the lead frame by a conductive member, and the insulating layer of the chip supporting portion and Exposing the connected surface of the lead to the surface of the sealing portion on the semiconductor device mounting side to form the sealing portion and resin-seal the semiconductor chip; and cutting and separating the lead from the lead frame And a method of manufacturing a semiconductor device. 5. A step of preparing a lead frame having a tab forming a chip supporting portion capable of supporting a semiconductor chip, and a plurality of leads arranged around the tab, wherein the tab of the lead frame and the tab are provided. A step of joining a semiconductor chip, a step of connecting a surface electrode of the semiconductor chip and the corresponding lead of the lead frame by a conductive member, and a surface of the tab opposite to a chip supporting surface and the lead. Exposing the connected surface of the sealing portion to the surface of the sealing portion on the semiconductor device mounting side to form the sealing portion and resin-seal the semiconductor chip; and after the resin sealing, the chip of the tab A method of manufacturing a semiconductor device, comprising: forming an insulating layer on a surface opposite to a support surface; and cutting and separating the lead from the lead frame.