JP2596542B2 - Lead frame and semiconductor device using the same - Google Patents
Lead frame and semiconductor device using the sameInfo
- Publication number
- JP2596542B2 JP2596542B2 JP61106643A JP10664386A JP2596542B2 JP 2596542 B2 JP2596542 B2 JP 2596542B2 JP 61106643 A JP61106643 A JP 61106643A JP 10664386 A JP10664386 A JP 10664386A JP 2596542 B2 JP2596542 B2 JP 2596542B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- lead
- tin
- package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85439—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、いわゆる樹脂封止型半導体装置に適用して
有効な技術に関するものである。Description: TECHNICAL FIELD The present invention relates to a technology effective when applied to a so-called resin-sealed semiconductor device.
いわゆる樹脂封止型半導体装置については、1980年１
月15日、株式会社工業調査会発行、日本マイクロエレク
トロニクス協会編「IC化実装技術」P149〜P150に説明さ
れている。その概要は、そのパッケージがエポキシ樹脂
等の樹脂でモールド形成され、該パッケージ内に半導体
ペレット（以下、単にペレットともいう）および外部端
子等が封止されてなるものである。For the so-called resin-encapsulated semiconductor device,
Published by the Industrial Research Council on March 15, edited by the Japan Microelectronics Association, "IC Packaging Technology" P149-P150. The outline is that the package is molded with a resin such as an epoxy resin, and a semiconductor pellet (hereinafter, also simply referred to as a pellet), external terminals, and the like are sealed in the package.
樹脂封止型半導体装置は、一般にその基材が銅、コバ
ールまたは42アロイ等の金属からなるリードフレームを
用いて製造される。すなわち、このリードフレームのペ
レット取付部であるタブに半導体ペレットを取付け、該
ペレットの電極とタブの外周囲に配設されているリード
内端部とを金等のワイヤで接続する等の組立を行う。組
立が完了した後、モールド金型に上記組立完了後のリー
ドフレームをセットし、樹脂の注入を行ってパッケージ
形成を行い、その後フレーム部等の切り離し、外部リー
ド部の折曲成形等を行って前記半導体装置が完成される
ものである。The resin-encapsulated semiconductor device is generally manufactured using a lead frame whose base material is made of a metal such as copper, kovar, or 42 alloy. That is, assembling such that a semiconductor pellet is attached to a tab which is a pellet attaching portion of the lead frame, and an electrode of the pellet is connected to a lead inner end disposed around the outer periphery of the tab with a wire such as gold. Do. After the assembly is completed, the lead frame after the above-mentioned assembly is set in the mold, and the package is formed by injecting the resin. Thereafter, the frame portion and the like are separated, and the external lead portion is bent and formed. The semiconductor device is completed.
前記半導体装置においては、リード内端部にワイヤボ
ンディング性を、外部リード部には実装のための半田付
性を確保する必要があり、さらにパッケージを構成する
樹脂に埋設されたリード部には耐湿性向上等のために該
樹脂との接着性を確保する必要がある。In the semiconductor device, it is necessary to ensure wire bonding properties at the inner ends of the leads and solderability for mounting at the outer leads, and furthermore, to provide the leads embedded in the resin constituting the package with moisture resistance. It is necessary to ensure adhesiveness with the resin in order to improve the properties.
ところが、一般に前記金属材料からなるリードフレー
ムを用いる場合には、パッケージの樹脂との接着性が必
ずしも充分でない。読に、リードフレームが銅またはそ
れを主成分とする銅系材料からなる場合には上記接着性
に問題がある。また、外部リード部の半田付性向上のた
めに、パッケージ形成後、外部リード部に半田付性良好
な金属を被着することが考えられる。具体的にはめっき
法や半田ディップ法がある。However, in general, when a lead frame made of the metal material is used, the adhesiveness to the resin of the package is not always sufficient. For reading, when the lead frame is made of copper or a copper-based material containing copper as a main component, there is a problem in the adhesiveness. Further, in order to improve the solderability of the external leads, it is conceivable to attach a metal having good solderability to the external leads after the package is formed. Specifically, there are a plating method and a solder dipping method.
めっき法は、半導体装置が化学的汚染を受けることが
あり、また一般に外部製作によっているため搬送に時間
がかかり製品完成までに長時間要するという問題があ
る。また、半田ディップでは高温の溶融半田にパッケー
ジ部まで浸漬するため、熱衝撃によるリードとパッケー
ジの剥がれが生じる等の問題もある。The plating method has a problem that the semiconductor device may be chemically contaminated, and generally requires a long time for transportation and a long time to complete the product because the device is manufactured externally. Further, in the solder dip, since the package is immersed in the high-temperature molten solder, there is a problem that the lead and the package are peeled off due to thermal shock.
本発明の目的は、樹脂封止型半導体装置の信頼性向上
と、その製造に適用して有効な技術を提供することにあ
る。An object of the present invention is to improve the reliability of a resin-encapsulated semiconductor device and to provide an effective technique applicable to the manufacture thereof.
本発明の前記ならびにその他の目的と新規な特徴は、
本明細書の記述および添付図面から明らかになるであろ
う。The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概
要を簡単に説明すれば、次の通りである。The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
すなわち、リードフレームを、ニッケル層が被着され
た基材の全体に錫−ニッケル合金層が被着され、リード
内端部には前記錫−ニッケル合金層の上に銀層または金
層が被着され、外部リード部には前記錫−ニッケル合金
層の上に銀層、半田層または錫層が被着されて、その表
面層が、リード内端部では銀層または金層、該内端部を
除く内部リードでは錫−ニッケル合金層、外部リード部
では銀層、半田層または錫層となる構成とする、或は、
半導体ペレット及びリードの一部が樹脂モールドされる
パッケージを有する半導体装置を、リード全体に被着さ
れたニッケル層上に、錫−ニッケル合金層が被着され、
該リードの前記パッケージ内に位置する内端部には前記
錫−ニッケル合金層の上に銀層または金層が被着され、
前記リードの前記パッケージ外に位置する外部リード部
には前記パッケージ端から離れた位置の前記錫−ニッケ
ル合金層の上に銀層、半田層または錫層が被着されて、
その表面層が、リード内端部では銀層または金層、該内
端部を除く内部リードでは錫−ニッケル合金層、外部リ
ード部では銀層、半田層または錫層となる構成とする。That is, a tin-nickel alloy layer is applied to the entire surface of the lead frame on which the nickel layer is applied, and a silver layer or a gold layer is applied to the inner ends of the leads on the tin-nickel alloy layer. A silver layer, a solder layer or a tin layer is applied to the outer lead portion on the tin-nickel alloy layer, and a surface layer thereof has a silver layer or a gold layer at an inner end portion of the lead. The internal lead excluding the part is a tin-nickel alloy layer, the external lead part is a silver layer, a solder layer or a tin layer, or
A semiconductor device having a package in which a part of a semiconductor pellet and a lead is resin-molded, a tin-nickel alloy layer is deposited on a nickel layer deposited on the entire lead,
A silver layer or a gold layer is deposited on the tin-nickel alloy layer at an inner end of the lead located in the package,
An external lead portion located outside the package of the lead has a silver layer, a solder layer or a tin layer applied on the tin-nickel alloy layer at a position away from the package end,
The surface layer is configured to be a silver layer or a gold layer at the inner end of the lead, a tin-nickel alloy layer for the inner lead except the inner end, and a silver layer, a solder layer or a tin layer for the outer lead.
半導体装置を上記構造にすることにより、銀および金
はワイヤボンディング性、銀、半田および錫は半田付性
に優れ、錫−ニッケル合金は樹脂との接着性に優れニッ
ケル層は基材と錫−ニッケル合金との接着性に優れてい
るため、上記性能を有する半導体装置を提供できる。With the above structure of the semiconductor device, silver and gold are excellent in wire bonding properties, silver, solder and tin are excellent in solderability, tin-nickel alloy is excellent in adhesiveness to resin, and the nickel layer is a base material and tin-tin alloy. Since it has excellent adhesion to a nickel alloy, a semiconductor device having the above performance can be provided.
また、前記構造のリードフレームを用いることによ
り、パッケージ形成後に外部リード部の表面処理を行う
ことなく前記半導体装置を製造することができるもので
あり、前記目的が達成されるものである。Further, by using the lead frame having the above structure, the semiconductor device can be manufactured without performing a surface treatment of the external lead portion after the package is formed, and the object is achieved.
第１図は本発明による一実施例である樹脂封止型半導
体装置を示す概略断面図であり、第２図は上記半導体装
置の製造に用いるリードフレームの一単位を示す概略平
面図である。FIG. 1 is a schematic sectional view showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic plan view showing one unit of a lead frame used for manufacturing the semiconductor device.
本実施例の半導体装置は、いわゆるフラットパッケー
ジ型であり、エポキシ樹脂等の樹脂をモールドして形成
したパッケージ１を有している。そのパッケージ１のほ
ぼ中央にはペレット取付部であるタブ２に半導体ペレッ
ト３が金−シリコン共晶層（図示せず）を介して取付け
られている。また、パッケージ１には、リード４の一部
が埋設されており、上記タブ２の外周囲に配設された上
記リード４の内端部と前記ペレット３の電極（図示せ
ず）とが、金からなるワイヤ５を介して電気的に接続さ
れている。そして、パッケージ１の外側に位置する外部
リード部は、第１図のように折り曲げられており、該外
部リード部の下端部である実装部4aで半田付けされ、プ
リント基板等に実装されるものである。The semiconductor device of this embodiment is a so-called flat package type, and has a package 1 formed by molding a resin such as an epoxy resin. At the substantially center of the package 1, a semiconductor pellet 3 is mounted on a tab 2 serving as a pellet mounting portion via a gold-silicon eutectic layer (not shown). A part of the lead 4 is buried in the package 1, and the inner end of the lead 4 disposed around the outer periphery of the tub 2 and an electrode (not shown) of the pellet 3 are provided. They are electrically connected via wires 5 made of gold. An external lead portion located outside the package 1 is bent as shown in FIG. 1, and is soldered at a mounting portion 4a, which is a lower end portion of the external lead portion, and is mounted on a printed circuit board or the like. It is.
本実施例においては、前記リード４がその表面全体に
錫−ニッケル合金層（図示せず）が被着されており、リ
ード内端部には銀層６が上記合金層に重ねて被着され、
また外部リード部にはパッケージ端から離れた位置に同
じく銀層７が重ねて被着されている。リード内端部の銀
層６はワイヤ５のボンディング性向上を目的として、外
部リード部の銀層７は半田付性向上を目的として、それ
ぞれ被着されている。In this embodiment, the lead 4 has a tin-nickel alloy layer (not shown) applied over the entire surface thereof, and a silver layer 6 is applied to the inner end of the lead so as to overlap the alloy layer. ,
A silver layer 7 is also applied to the external lead portion at a position distant from the package end. The silver layer 6 at the inner end of the lead is applied for improving the bonding property of the wire 5, and the silver layer 7 for the external lead is applied for improving the soldering property.
本実施例の半導体装置は、前記第２図に示すリードフ
レームを用いることにより、常法により容易に製造する
ことができる。The semiconductor device of this embodiment can be easily manufactured by a conventional method by using the lead frame shown in FIG.
上記リードフレームは、その一単位が外枠８および仕
切枠９とからその周囲が形成された四角形状からなる。
上記単位の中央にはタブ２が、そのコーナ部が周囲コー
ナから延在されたタブ吊りリード10により支持固定され
ている。また、外枠８および仕切枠９からは、リード４
が延在され、その内端部が上記タブ２の外周囲に配設さ
れている。そして、上記タブ吊りリード10およびリード
４の途中がタイバー11によって支持されている。The lead frame has a rectangular shape in which one unit is formed by an outer frame 8 and a partition frame 9 as one unit.
A tab 2 is supported and fixed at the center of the unit by a tab suspension lead 10 having a corner portion extending from a peripheral corner. From the outer frame 8 and the partition frame 9, the lead 4
Are extended, and the inner end thereof is disposed around the outer periphery of the tab 2. The middle of the tab suspension lead 10 and the lead 4 is supported by a tie bar 11.
本実施例においては、上記リードフレームの基材が銅
からなり、その表面全体に錫−ニッケル合金層が被着さ
れている。上記合金としては、たとえば錫30％、ニッケ
ル70％のものが使用できる。In this embodiment, the base material of the lead frame is made of copper, and a tin-nickel alloy layer is applied to the entire surface. As the above alloy, for example, an alloy having 30% tin and 70% nickel can be used.
上記リードフレームのリード４の内端部には銀層６
が、また外部リード部にも銀層７がそれぞれ上記合金層
に重ねて被着されている。A silver layer 6 is provided on the inner end of the lead 4 of the lead frame.
However, a silver layer 7 is also applied to the external lead portion so as to overlap the alloy layer.
なお、上記リードフレームは、プレス等の常法によ
り、銅板を所定形状にした後、その基材である銅の表面
全体にニッケル層を被着しその上に錫−ニッケル合金を
めっきし、次いでリード４の内端部と外部リード部に銀
を部分めっきすることにより製造できる。In addition, the above-mentioned lead frame, by a conventional method such as pressing, after forming a copper plate into a predetermined shape, a nickel layer is applied over the entire surface of copper as a base material, and a tin-nickel alloy is plated thereon, and then It can be manufactured by partially plating silver on the inner end of the lead 4 and the outer lead.
このように、本実施例によれば以下の効果を得ること
ができる。As described above, according to the present embodiment, the following effects can be obtained.
（１）．樹脂封止型半導体装置のリードを、その基材が
銅からなり、表面全体に錫−ニッケル合金層が被着さ
れ、その内端部および外部リード部のパッケージ端から
離れた位置に、上記合金に重ねて銀層6,7を被着するこ
とにより、銀がワイヤボンディング性および半田付性に
優れ、また錫−ニッケル合金がパッケージ樹脂との接着
性に優れているので、信頼性の高い半導体装置を提供で
きる。(1). The lead of the resin-encapsulated semiconductor device is made of copper, and a tin-nickel alloy layer is coated on the entire surface thereof. By applying silver layers 6 and 7 on top of silver, silver is excellent in wire bonding and soldering properties, and tin-nickel alloy is excellent in adhesion to package resin, so highly reliable semiconductor Equipment can be provided.
（２）．リードフレームをその銅からなる所定形状の基
材全体にニッケル層を被着しその上に、錫−ニッケル合
金層を被着し、リード内端部および外部リード部に銀層
を被着して形成することにより、該リードフレームを用
いて常法に基づいて、上記半導体装置を容易に製造する
ことができ、しかもパッケージ形成後に行う半田付性向
上のための外部リード部の処理が不要となる。(2). The lead frame is coated with a nickel layer over the entire base material of a predetermined shape made of copper, a tin-nickel alloy layer is deposited thereon, and a silver layer is deposited on the inner and outer leads of the lead. By forming the semiconductor device, the semiconductor device can be easily manufactured based on an ordinary method using the lead frame, and further, the processing of the external lead portion for improving the solderability after forming the package becomes unnecessary. .
（３）．前記（２）により、外部リード部をめっきする
場合のような化学的汚染や、半田ディップを行う場合の
ような熱衝撃によるリードとパッケージ樹脂との剥がれ
等の発生を回避できるので、これらに起因する内部腐食
等の発生を防止できる。(3). According to the above (2), it is possible to avoid chemical contamination such as when plating the external lead portion and peeling of the lead and the package resin due to thermal shock such as when performing solder dip. The occurrence of internal corrosion or the like can be prevented.
（４）．前記（２）により、製品完成までの工程を短縮
できる。(4). According to the above (2), the process up to product completion can be shortened.
（５）．前記（１）および（３）により、さらに半導体
装置の信頼性を向上することができる。(5). According to (1) and (3), the reliability of the semiconductor device can be further improved.
以上本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.
たとえば、実施例ではワイヤボンディング性向上のた
めに、リード内端部に銀層が被着されたもののみを示し
たが、金層であってもよく、また外部リード部へも銀層
以外の半田付性向上が可能な材料である半田または錫を
被着してもよい。For example, in the embodiment, only a silver layer is applied to the inner end of the lead in order to improve the wire bonding property. However, a gold layer may be used. Solder or tin, which is a material capable of improving solderability, may be applied.
また、リードの基材は銅に限るものでないことはいう
までもない。Needless to say, the base material of the lead is not limited to copper.
また、リードフレームとしては、半田付性向上のため
の銀層７が外部リード部のみに被着されたものを示した
が、これに限るものでなくパッケージ形成後にリードの
切断・成形を行った段階で外部リード部に銀層７が存在
すればよい。したがって、リードフレームの状態では、
後に切断除去されるフレーム部等にも被着されているこ
とはかまわない。そして、銀層７は半田付性向上を目的
としているため、外部リード部のうち実装部4aのみに被
着されているものであってもよい。Further, as the lead frame, the one in which the silver layer 7 for improving the solderability was applied only to the external lead portion was shown, but the present invention is not limited to this, and the lead was cut and formed after the package was formed. It is sufficient that the silver layer 7 exists in the external lead portion at the stage. Therefore, in the state of the lead frame,
It may be attached to a frame portion or the like that is cut and removed later. Since the silver layer 7 is intended to improve solderability, the silver layer 7 may be applied only to the mounting portion 4a of the external lead portion.
なお、銀層6,7の被着はめっき法に限るものでないこ
とはいうまでもない。It goes without saying that the deposition of the silver layers 6 and 7 is not limited to the plating method.
以上の説明では主として本発明者によってなされた発
明をその利用分野であるフラットパッケージ型に適用し
た場合について説明したが、それに限定されるものでは
なく、たとえば、樹脂封止型半導体装置であればいわゆ
るDIP等の種々のパッケージ型式のものに適用して有効
である。In the above description, the case where the invention made by the present inventor is mainly applied to a flat package type as a field of use has been described. However, the present invention is not limited thereto. It is effective when applied to various package types such as DIP.
本願において開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.
樹脂封止型半導体装置におけるリードの表面をニッケ
ル層の上に形成された錫−ニッケル合金層とし、リード
内端部には銀層または金層を被着し、外部リード部には
パッケージ端から離れた位置に銀層、半田層または錫層
を被着することにより、リードの内端部ではワイヤボン
ディング性を、外部リード部では半田付性を、パッケー
ジ樹脂の埋設部では該樹脂との接着性を向上させ、錫−
ニッケル合金層と基材との接着性を向上させることがで
きるので、信頼性の高い半導体装置を提供できる。The surface of the lead in the resin-encapsulated semiconductor device is a tin-nickel alloy layer formed on a nickel layer, a silver layer or a gold layer is applied to the inner end of the lead, and the outer lead is formed from the package end. By attaching a silver layer, a solder layer or a tin layer at a distant position, wire bonding property at the inner end of the lead, solderability at the external lead, and bonding with the resin at the embedded part of the package resin Improve tin-
Since the adhesiveness between the nickel alloy layer and the substrate can be improved, a highly reliable semiconductor device can be provided.
また、表面全体が錫−ニッケル合金層からなり、リー
ド内端部には銀層または金層が被着され、外部リード部
には銀層、半田層または錫層を被着させてなるリードフ
レームを用いることにより、常法に基づいて前記半導体
装置を容易に製造することができる。また、上記リード
フレームを用いることにより、既に外部リード部の処理
が完了しているので、製品完成までの工程を短縮するこ
とができ、さらに外部リード処理工程におけるめっきに
起因する半導体装置の化学的汚染または半田ディップ時
の熱衝撃に起因するリードとパッケージ樹脂との剥がれ
等の発生を回避することができる。A lead frame in which the entire surface is made of a tin-nickel alloy layer, a silver layer or a gold layer is applied to the inner end of the lead, and a silver layer, a solder layer or a tin layer is applied to the outer lead. By using the semiconductor device, the semiconductor device can be easily manufactured based on an ordinary method. Further, by using the lead frame, since the processing of the external lead portion has already been completed, the process up to product completion can be shortened, and further, the chemical treatment of the semiconductor device caused by plating in the external lead processing step can be shortened. It is possible to prevent the lead and the package resin from peeling off due to contamination or thermal shock at the time of solder dipping.
【図面の簡単な説明】 第１図は本発明による一実施例である樹脂封止型半導体
装置を示す概略断面図、 第２図は上記半導体装置の製造に用いるリードフレーム
の一単位を示す概略平面図である。 １……パッケージ、２……タブ、３……半導体ペレッ
ト、４……リード、4a……実装部、５……ワイヤ、6,7
……銀層、８……外枠、９……仕切枠、10……タブ吊り
リード、11……タイバー。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic sectional view showing a resin-encapsulated semiconductor device according to one embodiment of the present invention, and FIG. 2 is a schematic diagram showing one unit of a lead frame used for manufacturing the semiconductor device. It is a top view. 1 ... package, 2 ... tab, 3 ... semiconductor pellet, 4 ... lead, 4a ... mounting part, 5 ... wire, 6, 7
... silver layer, 8 ... outer frame, 9 ... partition frame, 10 ... tab hanging lead, 11 ... tie bar.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴村 隆志 土浦市木田余町3550番地 日立電線株式 会社金属研究所内 (72)発明者 吉岡 修 土浦市木田余町3550番地 日立電線株式 会社金属研究所内 (56)参考文献 特開 昭60−257160（ＪＰ，Ａ) 特開 昭60−149155（ＪＰ，Ａ) 特開 昭59−161850（ＪＰ，Ａ) 特開 昭53−102672（ＪＰ，Ａ) 特公 昭59−36426（ＪＰ，Ｂ２) 特公 昭60−30105（ＪＰ，Ｂ２) ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Takashi Suzumura 3550 Kida Yomachi, Tsuchiura City Inside Hitachi Metals Co., Ltd. 56) References JP-A-60-257160 (JP, A) JP-A-60-149155 (JP, A) JP-A-59-161850 (JP, A) JP-A-53-102672 (JP, A) Showa 59-36426 (JP, B2) Japanese Patent Publication Sho 60-30105 (JP, B2)
Claims (2)
ニッケル合金層が被着され、リード内端部には前記錫−
ニッケル合金層の上に銀層または金層が被着され、外部
リード部には前記錫−ニッケル合金層の上に銀層、半田
層または錫層が被着されて、その表面層が、リード内端
部では銀層または金層、該内端部を除く内部リードでは
錫−ニッケル合金層、外部リード部では銀層、半田層ま
たは錫層となるリードフレーム。1. The method according to claim 1, wherein the base material on which the nickel layer is applied has tin-
A nickel alloy layer is applied, and the tin-
A silver layer or a gold layer is deposited on the nickel alloy layer, and a silver layer, a solder layer or a tin layer is deposited on the tin-nickel alloy layer on the external lead portion, and the surface layer is formed of a lead. A lead frame having a silver layer or a gold layer at an inner end, a tin-nickel alloy layer at an inner lead excluding the inner end, and a silver layer, a solder layer or a tin layer at an outer lead.
ールドされるパッケージを有する半導体装置であって、
リード全体に被着されたニッケル層上に、錫−ニッケル
合金層が被着され、該リードの前記パッケージ内に位置
する内端部には前記錫−ニッケル合金層の上に銀層また
は金層が被着され、前記リードの前記パッケージ外に位
置する外部リード部には前記パッケージ端から離れた位
置の前記錫−ニッケル合金層の上に銀層、半田層または
錫層が被着されて、その表面層が、リード内端部では銀
層または金層、該内端部を除く内部リードでは錫−ニッ
ケル合金層、外部リード部では銀層、半田層または錫層
となる半導体装置。2. A semiconductor device having a package in which a part of a semiconductor pellet and a lead is resin-molded,
A tin-nickel alloy layer is deposited on the nickel layer deposited on the entire lead, and a silver layer or a gold layer is formed on the tin-nickel alloy layer at an inner end of the lead located in the package. A silver layer, a solder layer or a tin layer is deposited on the tin-nickel alloy layer at a position away from the package end on an external lead portion of the lead located outside the package, A semiconductor device in which the surface layer is a silver layer or a gold layer at the inner end of the lead, a tin-nickel alloy layer for the inner lead except the inner end, and a silver layer, a solder layer or a tin layer for the outer lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61106643A JP2596542B2 (en) | 1986-05-12 | 1986-05-12 | Lead frame and semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61106643A JP2596542B2 (en) | 1986-05-12 | 1986-05-12 | Lead frame and semiconductor device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62263665A JPS62263665A (en) | 1987-11-16 |
| JP2596542B2 true JP2596542B2 (en) | 1997-04-02 |
Family
ID=14438801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61106643A Expired - Lifetime JP2596542B2 (en) | 1986-05-12 | 1986-05-12 | Lead frame and semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2596542B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994895A (en) * | 1988-07-11 | 1991-02-19 | Fujitsu Limited | Hybrid integrated circuit package structure |
| US5264730A (en) * | 1990-01-06 | 1993-11-23 | Fujitsu Limited | Resin mold package structure of integrated circuit |
| CN100499099C (en) * | 2003-01-16 | 2009-06-10 | 松下电器产业株式会社 | Lead frame for a semiconductor device |
| JP4490861B2 (en) * | 2005-04-25 | 2010-06-30 | 日立協和エンジニアリング株式会社 | substrate |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53102672A (en) * | 1977-02-21 | 1978-09-07 | Hitachi Ltd | Manufacture for lead frame |
| JPS5936426A (en) * | 1982-08-23 | 1984-02-28 | Mitsubishi Electric Corp | Tristate output circuit |
| JPS59161850A (en) * | 1983-03-07 | 1984-09-12 | Hitachi Ltd | Resin sealed type semiconductor device and lead frame used therefor |
| JPS6030105A (en) * | 1983-07-29 | 1985-02-15 | Hitachi Ltd | Superconductive apparatus |
| JPS60149155A (en) * | 1984-01-17 | 1985-08-06 | Hitachi Cable Ltd | Manufacture of semiconductor device and lead frame used therefor |
| JPH0612796B2 (en) * | 1984-06-04 | 1994-02-16 | 株式会社日立製作所 | Semiconductor device |
-
1986
- 1986-05-12 JP JP61106643A patent/JP2596542B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62263665A (en) | 1987-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7368328B2 (en) | Semiconductor device having post-mold nickel/palladium/gold plated leads | |
| JP5893826B2 (en) | Lead frame and manufacturing method thereof | |
| KR20080034081A (en) | Semiconductor device and manufacturing method of the same | |
| JPH0612796B2 (en) | Semiconductor device | |
| JP2003297995A (en) | Preplated stamped small outline no-lead leadframes having etched profiles | |
| JP2000031365A (en) | Lead frame with selective palladium plating | |
| US20090065915A1 (en) | Singulated semiconductor package | |
| JP2009517869A (en) | Lead frame with improved solderability and improved moisture resistance reliability of semiconductor devices | |
| JPH05299530A (en) | Resin sealed semiconductor device and manufacturing mehtod thereof | |
| JPS6050343B2 (en) | Lead frame for semiconductor device manufacturing | |
| JP2596542B2 (en) | Lead frame and semiconductor device using the same | |
| JPS59161850A (en) | Resin sealed type semiconductor device and lead frame used therefor | |
| JP2002064173A (en) | Preplating of small-sized no-lead frame for semiconductors | |
| JPS60241241A (en) | Semiconductor device | |
| CN220358084U (en) | Electronic device and lead frame | |
| JPS6050342B2 (en) | Lead frame for semiconductor device manufacturing | |
| JPH05211261A (en) | Semiconductor device | |
| JPH0228356A (en) | Surface mounting type semiconductor device and its manufacture | |
| JPH0689478B2 (en) | Method for manufacturing resin-sealed semiconductor device | |
| JPS63104457A (en) | Lead frame | |
| JP2743567B2 (en) | Resin-sealed integrated circuit | |
| JP2004335947A (en) | Semiconductor device and formation method thereof | |
| JPH0553310B2 (en) | ||
| JPH09326461A (en) | Semiconductor device | |
| JPS61128551A (en) | Lead frame for semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| EXPY | Cancellation because of completion of term |