JP2008527692A5 - - Google Patents

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Publication number
JP2008527692A5
JP2008527692A5 JP2007549384A JP2007549384A JP2008527692A5 JP 2008527692 A5 JP2008527692 A5 JP 2008527692A5 JP 2007549384 A JP2007549384 A JP 2007549384A JP 2007549384 A JP2007549384 A JP 2007549384A JP 2008527692 A5 JP2008527692 A5 JP 2008527692A5
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JP
Japan
Prior art keywords
forming
layer
box
gate
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007549384A
Other languages
English (en)
Japanese (ja)
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JP2008527692A (ja
JP4982382B2 (ja
Filing date
Publication date
Priority claimed from US11/028,811 external-priority patent/US7091071B2/en
Application filed filed Critical
Publication of JP2008527692A publication Critical patent/JP2008527692A/ja
Publication of JP2008527692A5 publication Critical patent/JP2008527692A5/ja
Application granted granted Critical
Publication of JP4982382B2 publication Critical patent/JP4982382B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007549384A 2005-01-03 2005-11-30 リセス型ソース／ドレイン領域をｓｏｉウェハに含む半導体形成プロセス Expired - Fee Related JP4982382B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/028,811 US7091071B2 (en) 2005-01-03 2005-01-03 Semiconductor fabrication process including recessed source/drain regions in an SOI wafer
US11/028,811 2005-01-03
PCT/US2005/043208 WO2006073624A1 (en) 2005-01-03 2005-11-30 Semiconductor fabrication process including recessed source/drain regions in an soi wafer

Publications (3)

Publication Number Publication Date
JP2008527692A JP2008527692A (ja) 2008-07-24
JP2008527692A5 true JP2008527692A5 (enExample) 2008-10-23
JP4982382B2 JP4982382B2 (ja) 2012-07-25

Family

ID=36641070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007549384A Expired - Fee Related JP4982382B2 (ja) 2005-01-03 2005-11-30 リセス型ソース／ドレイン領域をｓｏｉウェハに含む半導体形成プロセス

Country Status (6)

Country Link
US (1) US7091071B2 (enExample)
JP (1) JP4982382B2 (enExample)
KR (1) KR101169920B1 (enExample)
CN (1) CN101076924B (enExample)
TW (1) TWI380374B (enExample)
WO (1) WO2006073624A1 (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7358571B2 (en) * 2004-10-20 2008-04-15 Taiwan Semiconductor Manufacturing Company Isolation spacer for thin SOI devices
US7659172B2 (en) * 2005-11-18 2010-02-09 International Business Machines Corporation Structure and method for reducing miller capacitance in field effect transistors
US7422950B2 (en) * 2005-12-14 2008-09-09 Intel Corporation Strained silicon MOS device with box layer between the source and drain regions
JP2008027942A (ja) * 2006-07-18 2008-02-07 Oki Electric Ind Co Ltd 半導体デバイス及びその製造方法
US8114128B2 (en) 2006-11-01 2012-02-14 Depuy Mitek, Inc. Cannulated suture anchor
US7393751B1 (en) 2007-03-13 2008-07-01 International Business Machines Corporation Semiconductor structure including laminated isolation region
US20080272432A1 (en) * 2007-03-19 2008-11-06 Advanced Micro Devices, Inc. Accumulation mode mos devices and methods for fabricating the same
KR101194843B1 (ko) 2007-12-07 2012-10-25 삼성전자주식회사 Ｇｅ 실리사이드층의 형성방법, Ｇｅ 실리사이드층을포함하는 반도체 소자 및 그의 제조방법
US20100038715A1 (en) * 2008-08-18 2010-02-18 International Business Machines Corporation Thin body silicon-on-insulator transistor with borderless self-aligned contacts
US8106456B2 (en) * 2009-07-29 2012-01-31 International Business Machines Corporation SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics
CN102237396B (zh) * 2010-04-27 2014-04-09 中国科学院微电子研究所 半导体器件及其制造方法
US9698054B2 (en) 2010-10-19 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of a p-type field effect transistor
CN102856207B (zh) * 2011-06-30 2015-02-18 中国科学院微电子研究所 一种半导体结构及其制造方法
US8476131B2 (en) 2011-08-24 2013-07-02 Globalfoundries Inc. Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same
US9059212B2 (en) 2012-10-31 2015-06-16 International Business Machines Corporation Back-end transistors with highly doped low-temperature contacts
US9006071B2 (en) 2013-03-27 2015-04-14 International Business Machines Corporation Thin channel MOSFET with silicide local interconnect
FR3025941A1 (fr) * 2014-09-17 2016-03-18 Commissariat Energie Atomique Transistor mos a resistance et capacites parasites reduites
US9768254B2 (en) * 2015-07-30 2017-09-19 International Business Machines Corporation Leakage-free implantation-free ETSOI transistors

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121659A (en) * 1998-03-27 2000-09-19 International Business Machines Corporation Buried patterned conductor planes for semiconductor-on-insulator integrated circuit
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6396121B1 (en) * 2000-05-31 2002-05-28 International Business Machines Corporation Structures and methods of anti-fuse formation in SOI
US6930357B2 (en) * 2003-06-16 2005-08-16 Infineon Technologies Ag Active SOI structure with a body contact through an insulator
JP4446690B2 (ja) * 2003-06-27 2010-04-07 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US7271453B2 (en) * 2004-09-20 2007-09-18 International Business Machines Corporation Buried biasing wells in FETS
US7306997B2 (en) * 2004-11-10 2007-12-11 Advanced Micro Devices, Inc. Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor

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