JP2008227020A - 電子部品の実装構造 - Google Patents
電子部品の実装構造 Download PDFInfo
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- JP2008227020A JP2008227020A JP2007061018A JP2007061018A JP2008227020A JP 2008227020 A JP2008227020 A JP 2008227020A JP 2007061018 A JP2007061018 A JP 2007061018A JP 2007061018 A JP2007061018 A JP 2007061018A JP 2008227020 A JP2008227020 A JP 2008227020A
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- 229910000679 solder Inorganic materials 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims description 60
- 238000009826 distribution Methods 0.000 claims description 18
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 230000007423 decrease Effects 0.000 claims description 5
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 230000035882 stress Effects 0.000 description 24
- 230000008646 thermal stress Effects 0.000 description 18
- 238000004088 simulation Methods 0.000 description 10
- 238000004364 calculation method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Abstract
【解決手段】集積回路の実装構造10は、はんだバンプ1(1A〜1D)が実装面の中心部から外側に向かって、隣接するもの同士の間隔が小さくなるように配置され、例えば、中心部のはんだバンプ1Aとこの外側のはんだバンプ1BとはピッチP1の間隔で、はんだバンプ1Bとこの外側のはんだバンプ1CとはピッチP2の間隔で、はんだバンプ1Cとこの外側のはんだバンプ1DとはピッチP3(ここで、P1>P2>P3)の間隔でそれぞれ配置される。
【選択図】図1
Description
特許文献3に示されている集積回路の実装構造では、半導体チップの実装面に配置した突起状電極群の密度を、半導体チップの中央部に近い列が最も高く、それよりも外側の列ほど低くなるように設定されているが、このような突起状電極の配置は、半導体チップの実装面の中心部から外側に向かって分布密度が高くなるように突起状電極が配置される本願発明とは逆の関係になっている。
特許文献4に示されている集積回路の実装構造では、信頼性を向上するために突起状電極間の電位差を考慮して突起状電極が配置されているが、電子部品の温度上昇時に突起状電極に発生する応力を均一化するという本願発明の目的については考慮されていない。
特許文献5に示されている集積回路の実装構造では、突起状電極間のショートの発生を少なくするために突起状電極密度を規定値以上の所定の値に設定されているが、上述のように本願発明とは目的、手段を異にしている。
特許文献1では前述したように実装面の外周部のみに突起状電極であるはんだバンプ201を配置した半導体チップ202を対象にして、そのような配置のはんだバンプ201に発生する応力を緩和することを目的としてなされている。このようにはんだバンプを実装面の外周部のみに配置した半導体チップと、突起状電極を実装面全体に分布させるように配置した半導体チップとでは、集積回路動作中の温度上昇時に突起状電極に発生する応力の状況は異なってくる。したがって、特許文献1における問題解決手段をそのまま実装面全体にはんだバンプを分布させるように配置した本願発明に対して適用することはできない。
このような構成により、複数のはんだバンプ1に発生する応力の分布を全体のはんだバンプ1にわたって均一化させることができるので、電子部品動作中の温度上昇によりはんだバンプ1に発生する応力を緩和することにより、電子部品の信頼性を向上させることができる。
この例の電子部品の実装構造10は、同図に示すように、複数のはんだバンプ1(1A〜1D)が実装面全体に分布するようにX、Yの二次元方向に配置された半導体チップ2が、はんだバンプ1を介して基板3に実装される構成において、半導体チップ2の実装面の中心部から外側に向かって、はんだバンプ1が隣接するもの同士の間隔が小さくなるように配置されている。
したがって、複数のはんだバンプに発生する応力の分布を全体のはんだバンプにわたって均一化させることができるので、電子部品動作中の温度上昇によりはんだバンプに発生する応力を緩和させることにより、電子部品の信頼性を向上させることができる。
この例の電子部品の実装構造20は、同図に示すように、複数のはんだバンプ11が実装面全体に分布するようにX、Yの二次元方向に配置された半導体チップ12が、はんだバンプ11を介して基板に実装される構成において、実装面の中心部のはんだバンプ11Aとこの外側のはんだバンプ11BとはピッチP5の間隔で配置される一方、実装面の外周部のコーナ領域13A、13B、13Cには、ピッチP6(ここで、ピッチP5>P6)の間隔ではんだバンプ11Cが配置されている。
2,12 半導体チップ(電子部品チップ)
3 基板(配線基板)
10、20 電子部品の実装構造
13A〜13C 半導体チップの実装面のコーナ領域
Claims (5)
- 複数の突起状電極が実装面全体に分布するように配置された電子部品チップが、前記突起状電極を介して基板に実装される電子部品の実装構造であって、
前記電子部品チップの前記実装面の中心部から外側に向かって、分布密度が高くなるように前記突起状電極が配置されていることを特徴とする電子部品の実装構造。 - 前記電子部品チップの前記実装面の中心部から外側に向かって、隣接するもの同士の間隔が小さくなるように前記突起状電極が配置されていることを特徴とする請求項1記載の電子部品の実装構造。
- 前記電子部品チップの前記実装面の外周部に、該実装面の中心部に配置される前記突起状電極間の間隔よりも小さくなるように複数の前記突起状電極が配置されていることを特徴とする請求項1記載の電子部品の実装構造。
- 前記電子部品チップが半導体チップから成ることを特徴とする請求項1、2又は3記載の電子部品の実装構造。
- 前記半導体チップは前記突起状電極としてはんだバンプが配置されていることを特徴とする請求項4記載の電子部品の実装構造。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010123602A (ja) * | 2008-11-17 | 2010-06-03 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US9161438B2 (en) | 2010-03-31 | 2015-10-13 | Taiyo Yuden Co., Ltd. | Stress buffer layer and method for producing same |
CN108573885A (zh) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010047006A1 (ja) * | 2008-10-23 | 2010-04-29 | パナソニック株式会社 | 半導体装置およびその製造方法 |
DE112011103782B4 (de) * | 2010-11-16 | 2019-05-09 | Mitsubishi Electric Corporation | Halbleiterelement, Halbleitervorrichtung und Verfahren zum Herstellen eines Halbleiterelements |
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KR20180008379A (ko) * | 2015-03-11 | 2018-01-24 | 인텔 코포레이션 | 스트레인 재분배 층을 갖는 신장가능 전자 장치 제조 방법 |
US10622326B2 (en) * | 2017-08-18 | 2020-04-14 | Industrial Technology Research Institute | Chip package structure |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000124259A (ja) * | 1998-10-12 | 2000-04-28 | Sony Corp | Icチップ、半導体装置、及び、半導体装置の製造方法 |
JP2001176928A (ja) * | 1999-12-20 | 2001-06-29 | Nec Corp | 半導体装置 |
JP2004047758A (ja) * | 2002-07-12 | 2004-02-12 | Canon Inc | 半導体装置 |
JP2005012065A (ja) * | 2003-06-20 | 2005-01-13 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2006216942A (ja) * | 2006-01-20 | 2006-08-17 | Seiko Epson Corp | 回路基板、バンプ付き半導体素子の実装構造、及び電気光学装置、並びに電子機器 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2611480B2 (ja) | 1989-03-08 | 1997-05-21 | 日本電気株式会社 | 無線電話装置 |
JP3367826B2 (ja) | 1996-06-14 | 2003-01-20 | 東芝マイクロエレクトロニクス株式会社 | 半導体メモリ装置及びその製造方法 |
JP2002246404A (ja) | 2001-02-16 | 2002-08-30 | Matsushita Electric Ind Co Ltd | バンプ付き半導体素子 |
JP2002270723A (ja) | 2001-03-12 | 2002-09-20 | Hitachi Ltd | 半導体装置、半導体チップおよび実装基板 |
US7667236B2 (en) * | 2003-12-24 | 2010-02-23 | Lumination Llc | Optimized contact design for thermosonic bonding of flip-chip devices |
JP4913991B2 (ja) | 2004-02-26 | 2012-04-11 | セイコーエプソン株式会社 | 実装構造体、電気光学装置、および電子機器 |
JP4601365B2 (ja) * | 2004-09-21 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2007
- 2007-03-09 JP JP2007061018A patent/JP5056085B2/ja not_active Expired - Fee Related
-
2008
- 2008-03-06 US US12/043,468 patent/US8362610B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000124259A (ja) * | 1998-10-12 | 2000-04-28 | Sony Corp | Icチップ、半導体装置、及び、半導体装置の製造方法 |
JP2001176928A (ja) * | 1999-12-20 | 2001-06-29 | Nec Corp | 半導体装置 |
JP2004047758A (ja) * | 2002-07-12 | 2004-02-12 | Canon Inc | 半導体装置 |
JP2005012065A (ja) * | 2003-06-20 | 2005-01-13 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2006216942A (ja) * | 2006-01-20 | 2006-08-17 | Seiko Epson Corp | 回路基板、バンプ付き半導体素子の実装構造、及び電気光学装置、並びに電子機器 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010123602A (ja) * | 2008-11-17 | 2010-06-03 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US8405209B2 (en) | 2008-11-17 | 2013-03-26 | Renesas Electronics Corporation | Semiconductor device with varying bump density regions and method of manufacturing the same |
US9161438B2 (en) | 2010-03-31 | 2015-10-13 | Taiyo Yuden Co., Ltd. | Stress buffer layer and method for producing same |
CN108573885A (zh) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
CN108573885B (zh) * | 2017-03-07 | 2021-03-23 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
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