JP2008177531A - ダブルプラズマｕｔｂｏｘ - Google Patents

ダブルプラズマｕｔｂｏｘ Download PDF

Info

Publication number
JP2008177531A
JP2008177531A JP2007279271A JP2007279271A JP2008177531A JP 2008177531 A JP2008177531 A JP 2008177531A JP 2007279271 A JP2007279271 A JP 2007279271A JP 2007279271 A JP2007279271 A JP 2007279271A JP 2008177531 A JP2008177531 A JP 2008177531A
Authority
JP
Japan
Prior art keywords
substrate
plasma
substrates
bonded
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007279271A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008177531A5 (https=
Inventor
Ionut Radu
ラドゥ イオナット
Audrey Lambert
ランバート オードレイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2008177531A publication Critical patent/JP2008177531A/ja
Publication of JP2008177531A5 publication Critical patent/JP2008177531A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
    • Y10T428/264—Up to 3 mils
    • Y10T428/265—1 mil or less

Landscapes

  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Golf Clubs (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Lock And Its Accessories (AREA)
  • Compounds Of Alkaline-Earth Elements, Aluminum Or Rare-Earth Metals (AREA)
  • Oxygen, Ozone, And Oxides In General (AREA)
  • Solid-Sorbent Or Filter-Aiding Compositions (AREA)
JP2007279271A 2006-12-18 2007-10-26 ダブルプラズマｕｔｂｏｘ Pending JP2008177531A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0655608A FR2910177B1 (fr) 2006-12-18 2006-12-18 Couche tres fine enterree

Publications (2)

Publication Number Publication Date
JP2008177531A true JP2008177531A (ja) 2008-07-31
JP2008177531A5 JP2008177531A5 (https=) 2011-11-10

Family

ID=38057349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007279271A Pending JP2008177531A (ja) 2006-12-18 2007-10-26 ダブルプラズマｕｔｂｏｘ

Country Status (10)

Country Link
US (1) US20080145650A1 (https=)
EP (1) EP1936667B1 (https=)
JP (1) JP2008177531A (https=)
KR (1) KR100944235B1 (https=)
CN (1) CN100527357C (https=)
AT (1) ATE458270T1 (https=)
DE (1) DE602007004811D1 (https=)
FR (1) FR2910177B1 (https=)
SG (2) SG144023A1 (https=)
TW (1) TW200847240A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011523784A (ja) * 2008-05-26 2011-08-18 コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブ 直接接合方法における窒素プラズマ表面処理
JP2015176899A (ja) * 2014-03-13 2015-10-05 信越化学工業株式会社 複合基板の製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8481406B2 (en) 2010-07-15 2013-07-09 Soitec Methods of forming bonded semiconductor structures
SG177816A1 (en) * 2010-07-15 2012-02-28 Soitec Silicon On Insulator Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR2992772B1 (fr) * 2012-06-28 2014-07-04 Soitec Silicon On Insulator Procede de realisation de structure composite avec collage de type metal/metal

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391227A (ja) * 1989-09-01 1991-04-16 Nippon Soken Inc 半導体基板の接着方法
JPH07249749A (ja) * 1994-03-11 1995-09-26 Canon Inc Ｓｏｉ基板の作製方法
JPH09223781A (ja) * 1995-12-15 1997-08-26 Komatsu Electron Metals Co Ltd 貼り合わせｓｏｉウェーハの製造方法
JPH1145840A (ja) * 1997-03-27 1999-02-16 Canon Inc 複合部材の分離方法、分離された部材、分離装置、半導体基体の作製方法および半導体基体
JPH11186187A (ja) * 1997-12-22 1999-07-09 Mitsubishi Materials Silicon Corp Ｓｏｉ基板の製造方法
JP2002231692A (ja) * 2001-01-30 2002-08-16 Sony Corp 半導体製造装置
JP2006080314A (ja) * 2004-09-09 2006-03-23 Canon Inc 結合基板の製造方法
JP2006324530A (ja) * 2005-05-19 2006-11-30 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU9296098A (en) * 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
JPH11251207A (ja) * 1998-03-03 1999-09-17 Canon Inc Ｓｏｉ基板及びその製造方法並びにその製造設備
US6653209B1 (en) * 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
US6780759B2 (en) * 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
FR2874455B1 (fr) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
US6995075B1 (en) * 2002-07-12 2006-02-07 Silicon Wafer Technologies Process for forming a fragile layer inside of a single crystalline substrate
US20040137698A1 (en) * 2002-08-29 2004-07-15 Gianni Taraschi Fabrication system and method for monocrystaline semiconductor on a substrate
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
US6833195B1 (en) * 2003-08-13 2004-12-21 Intel Corporation Low temperature germanium transfer
JPWO2005022610A1 (ja) * 2003-09-01 2007-11-01 株式会社Sumco 貼り合わせウェーハの製造方法
US20050067377A1 (en) * 2003-09-25 2005-03-31 Ryan Lei Germanium-on-insulator fabrication utilizing wafer bonding
WO2005055293A1 (ja) * 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
US7105897B2 (en) * 2004-10-28 2006-09-12 Taiwan Semiconductor Manufacturing Company Semiconductor structure and method for integrating SOI devices and bulk devices
KR100634528B1 (ko) * 2004-12-03 2006-10-16 삼성전자주식회사 단결정 실리콘 필름의 제조방법
KR100601976B1 (ko) * 2004-12-08 2006-07-18 삼성전자주식회사 스트레인 실리콘 온 인슐레이터 구조체 및 그 제조방법
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
EP1911084A1 (en) * 2005-08-03 2008-04-16 MEMC Electronic Materials, Inc. Strained silicon on insulator (ssoi) structure with improved crystallinity in the strained silicon layer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0391227A (ja) * 1989-09-01 1991-04-16 Nippon Soken Inc 半導体基板の接着方法
JPH07249749A (ja) * 1994-03-11 1995-09-26 Canon Inc Ｓｏｉ基板の作製方法
JPH09223781A (ja) * 1995-12-15 1997-08-26 Komatsu Electron Metals Co Ltd 貼り合わせｓｏｉウェーハの製造方法
JPH1145840A (ja) * 1997-03-27 1999-02-16 Canon Inc 複合部材の分離方法、分離された部材、分離装置、半導体基体の作製方法および半導体基体
JPH11186187A (ja) * 1997-12-22 1999-07-09 Mitsubishi Materials Silicon Corp Ｓｏｉ基板の製造方法
JP2002231692A (ja) * 2001-01-30 2002-08-16 Sony Corp 半導体製造装置
JP2006080314A (ja) * 2004-09-09 2006-03-23 Canon Inc 結合基板の製造方法
JP2006324530A (ja) * 2005-05-19 2006-11-30 Shin Etsu Chem Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011523784A (ja) * 2008-05-26 2011-08-18 コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブ 直接接合方法における窒素プラズマ表面処理
JP2015176899A (ja) * 2014-03-13 2015-10-05 信越化学工業株式会社 複合基板の製造方法

Also Published As

Publication number Publication date
SG162813A1 (en) 2010-07-29
EP1936667A1 (fr) 2008-06-25
CN100527357C (zh) 2009-08-12
TW200847240A (en) 2008-12-01
FR2910177A1 (fr) 2008-06-20
DE602007004811D1 (de) 2010-04-01
ATE458270T1 (de) 2010-03-15
US20080145650A1 (en) 2008-06-19
CN101207021A (zh) 2008-06-25
KR20080056630A (ko) 2008-06-23
SG144023A1 (en) 2008-07-29
FR2910177B1 (fr) 2009-04-03
KR100944235B1 (ko) 2010-02-24
EP1936667B1 (fr) 2010-02-17

Similar Documents

Publication Publication Date Title
US7892951B2 (en) SOI substrates with a fine buried insulating layer
JP4927080B2 (ja) 厚い絶縁層の粗さを減少させるための方法
TWI492275B (zh) The method of manufacturing the bonded substrate
JP4379943B2 (ja) 半導体基板の製造方法および半導体基板製造装置
US6991995B2 (en) Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer
CN100446182C (zh) 具有改进电特性的复合基片的制造方法
US7575988B2 (en) Method of fabricating a hybrid substrate
JP4407127B2 (ja) Ｓｏｉウエーハの製造方法
JP2008021971A (ja) 電子工学、光学または光電子工学に使用される２つの基板を直接接合する方法
US8623740B2 (en) Method of detaching semi-conductor layers at low temperature
US20110189834A1 (en) Surface treatment for molecular bonding
US8461018B2 (en) Treatment for bonding interface stabilization
WO2007094233A1 (ja) Ｓｏｉ基板およびｓｏｉ基板の製造方法
WO2005124865A1 (ja) 貼り合わせウェーハの製造方法
JP2012507167A (ja) 半導体薄膜のスタックを製造する方法
JP2008177531A (ja) ダブルプラズマｕｔｂｏｘ
US8367519B2 (en) Method for the preparation of a multi-layered crystalline structure
JP2018085536A (ja) 多層半導体デバイス作製時の低温層転写方法
JP2009253184A (ja) 貼り合わせ基板の製造方法

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110711

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110802

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20110921

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120327