ATE458270T1 - Doppelplasmabehandlung zur herstellung einer struktur mit einem vergrabenen ultradünnen oxid - Google Patents

Doppelplasmabehandlung zur herstellung einer struktur mit einem vergrabenen ultradünnen oxid

Info

Publication number
ATE458270T1
ATE458270T1 AT07024512T AT07024512T ATE458270T1 AT E458270 T1 ATE458270 T1 AT E458270T1 AT 07024512 T AT07024512 T AT 07024512T AT 07024512 T AT07024512 T AT 07024512T AT E458270 T1 ATE458270 T1 AT E458270T1
Authority
AT
Austria
Prior art keywords
substrate
burned
produce
plasma treatment
ultrathin oxide
Prior art date
Application number
AT07024512T
Other languages
German (de)
English (en)
Inventor
Ionut Radu
Audrey Lambert
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE458270T1 publication Critical patent/ATE458270T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
    • Y10T428/264—Up to 3 mils
    • Y10T428/265—1 mil or less

Landscapes

  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Golf Clubs (AREA)
  • Slot Machines And Peripheral Devices (AREA)
  • Lock And Its Accessories (AREA)
  • Compounds Of Alkaline-Earth Elements, Aluminum Or Rare-Earth Metals (AREA)
  • Oxygen, Ozone, And Oxides In General (AREA)
  • Solid-Sorbent Or Filter-Aiding Compositions (AREA)
AT07024512T 2006-12-18 2007-12-18 Doppelplasmabehandlung zur herstellung einer struktur mit einem vergrabenen ultradünnen oxid ATE458270T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0655608A FR2910177B1 (fr) 2006-12-18 2006-12-18 Couche tres fine enterree

Publications (1)

Publication Number Publication Date
ATE458270T1 true ATE458270T1 (de) 2010-03-15

Family

ID=38057349

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07024512T ATE458270T1 (de) 2006-12-18 2007-12-18 Doppelplasmabehandlung zur herstellung einer struktur mit einem vergrabenen ultradünnen oxid

Country Status (10)

Country Link
US (1) US20080145650A1 (https=)
EP (1) EP1936667B1 (https=)
JP (1) JP2008177531A (https=)
KR (1) KR100944235B1 (https=)
CN (1) CN100527357C (https=)
AT (1) ATE458270T1 (https=)
DE (1) DE602007004811D1 (https=)
FR (1) FR2910177B1 (https=)
SG (2) SG144023A1 (https=)
TW (1) TW200847240A (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2931585B1 (fr) * 2008-05-26 2010-09-03 Commissariat Energie Atomique Traitement de surface par plasma d'azote dans un procede de collage direct
US8481406B2 (en) 2010-07-15 2013-07-09 Soitec Methods of forming bonded semiconductor structures
SG177816A1 (en) * 2010-07-15 2012-02-28 Soitec Silicon On Insulator Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
FR2987166B1 (fr) 2012-02-16 2017-05-12 Soitec Silicon On Insulator Procede de transfert d'une couche
FR2992772B1 (fr) * 2012-06-28 2014-07-04 Soitec Silicon On Insulator Procede de realisation de structure composite avec collage de type metal/metal
JP6117134B2 (ja) * 2014-03-13 2017-04-19 信越化学工業株式会社 複合基板の製造方法

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JPH0391227A (ja) * 1989-09-01 1991-04-16 Nippon Soken Inc 半導体基板の接着方法
JP3294934B2 (ja) * 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
JP3917219B2 (ja) * 1995-12-15 2007-05-23 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 貼り合わせｓｏｉウェーハの製造方法
JP2877800B2 (ja) * 1997-03-27 1999-03-31 キヤノン株式会社 複合部材の分離方法、分離された部材、分離装置、半導体基体の作製方法および半導体基体
AU9296098A (en) * 1997-08-29 1999-03-16 Sharon N. Farrens In situ plasma wafer bonding method
JP3582566B2 (ja) * 1997-12-22 2004-10-27 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
JPH11251207A (ja) * 1998-03-03 1999-09-17 Canon Inc Ｓｏｉ基板及びその製造方法並びにその製造設備
US6653209B1 (en) * 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
JP2002231692A (ja) * 2001-01-30 2002-08-16 Sony Corp 半導体製造装置
US6780759B2 (en) * 2001-05-09 2004-08-24 Silicon Genesis Corporation Method for multi-frequency bonding
FR2874455B1 (fr) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
US6995075B1 (en) * 2002-07-12 2006-02-07 Silicon Wafer Technologies Process for forming a fragile layer inside of a single crystalline substrate
US20040137698A1 (en) * 2002-08-29 2004-07-15 Gianni Taraschi Fabrication system and method for monocrystaline semiconductor on a substrate
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
US6833195B1 (en) * 2003-08-13 2004-12-21 Intel Corporation Low temperature germanium transfer
JPWO2005022610A1 (ja) * 2003-09-01 2007-11-01 株式会社Sumco 貼り合わせウェーハの製造方法
US20050067377A1 (en) * 2003-09-25 2005-03-31 Ryan Lei Germanium-on-insulator fabrication utilizing wafer bonding
WO2005055293A1 (ja) * 2003-12-02 2005-06-16 Bondtech Inc. 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置
JP2006080314A (ja) * 2004-09-09 2006-03-23 Canon Inc 結合基板の製造方法
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
US7105897B2 (en) * 2004-10-28 2006-09-12 Taiwan Semiconductor Manufacturing Company Semiconductor structure and method for integrating SOI devices and bulk devices
KR100634528B1 (ko) * 2004-12-03 2006-10-16 삼성전자주식회사 단결정 실리콘 필름의 제조방법
KR100601976B1 (ko) * 2004-12-08 2006-07-18 삼성전자주식회사 스트레인 실리콘 온 인슐레이터 구조체 및 그 제조방법
US8138061B2 (en) * 2005-01-07 2012-03-20 International Business Machines Corporation Quasi-hydrophobic Si-Si wafer bonding using hydrophilic Si surfaces and dissolution of interfacial bonding oxide
JP5128761B2 (ja) * 2005-05-19 2013-01-23 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
EP1911084A1 (en) * 2005-08-03 2008-04-16 MEMC Electronic Materials, Inc. Strained silicon on insulator (ssoi) structure with improved crystallinity in the strained silicon layer

Also Published As

Publication number Publication date
SG162813A1 (en) 2010-07-29
EP1936667A1 (fr) 2008-06-25
CN100527357C (zh) 2009-08-12
JP2008177531A (ja) 2008-07-31
TW200847240A (en) 2008-12-01
FR2910177A1 (fr) 2008-06-20
DE602007004811D1 (de) 2010-04-01
US20080145650A1 (en) 2008-06-19
CN101207021A (zh) 2008-06-25
KR20080056630A (ko) 2008-06-23
SG144023A1 (en) 2008-07-29
FR2910177B1 (fr) 2009-04-03
KR100944235B1 (ko) 2010-02-24
EP1936667B1 (fr) 2010-02-17

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