JP2011523784A - 直接接合方法における窒素プラズマ表面処理 - Google Patents
直接接合方法における窒素プラズマ表面処理 Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Abstract
Description
−酸化シリコン薄層2および2’が、基板1および1’の表面でウェットプロセスによって形成されるステップF1と、
−ステップF1にすでに形成された酸化シリコン薄層の少なくとも一部を、酸窒化シリコン表面薄層3および3’に変換する表面処理ステップF2と、
−2つの基板1および1’を接触させるステップF3と、
を連続して実行することによって接合される。
−ウェットプロセスによって得られたSiO2上にウェットプロセスによって得られたSiO2を接合。
−ウェットプロセスによって得られたSiO2上に自然SiO2を接合。
−自然SiO2上に自然SiO2を接合。
−ウェットプロセスによって得られたSiO2上に熱SiO2(例えば、約2.5nm〜約1マイクロメートルの厚さの薄層)を接合。
−自然SiO2上に接合される熱SiO2(例えば、約2.5nm〜約25nmの厚さの薄層)を接合。
−熱SiO2(例えば、約2.5nm〜約25nmの厚さの薄層)を熱SiO2(例えば、約2.5nm〜約25nmの厚さの薄層)を接合。
−数パーセント(例えば、5%)より高く、特に、15%より高く、好ましくは、30%より高く65%より低く、特に、50%より低い窒素原子濃度、
−
−0.1nmより大きく、有益には、1nm以上の厚さ、
−−OH結合の非常に低い表面および体積濃度、
−−NH結合の著しい表面および体積濃度、
を与える酸窒化シリコン薄膜が得られる場合、接合界面の品質はさらに高められる。
−1つまたは複数の基板が、ICPチャンバに配置される。
−表面処理前のチャンバ内の圧力は、10−3ミリトル(mT)、すなわち、約0.1333mPaより低いことが好ましい。
−非常に短い時間、40mT(すなわち、約5.33Pa)以下、有益には、約5mT(すなわち、約0.66Pa)の窒素分圧でプラズマ活性化が実行される。このようにして、表面処理中の窒素分圧は、好ましくは、6Pa以下、有益には、1Pa以下である。さらに、表面処理の時間は、有益には、5分未満、好ましくは、2分未満である。表面処理時間は、特に、30秒〜90秒である。
−処理される1つまたは複数の基板を支持するための基板ホルダの温度は、有益には、周囲温度より高い。このように、基板ホルダは、150℃〜350℃の範囲にある値の固定温度に維持されうる。
−誘導結合プラズマ源は、数百ワット、好ましくは、500W〜800Wでありうる出力を有する無線周波数出力の発生器を備える。
−基板ホルダおよび接地間の電位差:0
−プラズマ活性化ステップ前のチャンバ内の圧力:10−3mT
−プラズマ活性化ステップ中の窒素分圧:5mT
−プラズマ活性化ステップ中の窒素フラックス:100sccm
Claims (14)
- プレート表面に酸化シリコン薄層またはシリコン薄層を備える2つのプレートを直接接合するための方法において、前記2つのプレートのそれぞれの薄層を接触させるステップの前に、少なくとも1つのプレートの前記薄層が、誘導結合プラズマ源によって発生させた窒素系プラズマによって、プラズマと前記プレートを支持する支持ホルダとの間の50V未満の電位差の存在下において、5nm未満の厚さを有する酸窒化シリコン表面薄膜を形成する単一の表面処理ステップを受けることを特徴とする方法。
- 前記電位差が、15V未満であることを特徴とする、請求項1に記載の方法。
- 前記電位差がゼロであることを特徴とする、請求項2に記載の方法。
- 前記表面処理の時間が、5分未満であることを特徴とする、請求項1から3のいずれか一項に記載の方法。
- 前記表面処理の時間が、30秒〜90秒であることを特徴とする、請求項5に記載の方法。
- 前記基板ホルダが、前記表面処理中に150℃〜350℃の温度に維持されることを特徴とする、請求項1から5のいずれか一項に記載の方法。
- 前記表面処理中の窒素分圧が、6Pa以下であることを特徴とする、請求項1から6のいずれか一項に記載の方法。
- 前記表面処理中の窒素分圧が、1Pa以下であることを特徴とする、請求項7に記載の方法。
- 少なくとも1つのプレートの前記酸化シリコン薄膜が、自然酸化シリコン薄膜であることを特徴とする、請求項1から8のいずれか一項に記載の方法。
- 少なくとも1つのプレートの前記酸化シリコン薄層が、ウェットプロセスによって形成されることを特徴とする、請求項1から8のいずれか一項に記載の方法。
- 1つのプレートの前記酸化シリコン薄層が、熱酸化によって形成されることを特徴とする、請求項1から8のいずれか一項に記載の方法。
- 1つのプレートの前記酸化シリコン薄層が、堆積によって形成されることを特徴とする、請求項1から8のいずれか一項に記載の方法。
- 少なくとも1つのプレートが、プレート表面に酸化シリコン薄層またはシリコン薄層を備える半導体基板によって形成されることを特徴とする、請求項1から12のいずれか一項に記載の方法。
- 前記半導体基板が、ゲルマニウム系であることを特徴とする、請求項13に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0802833A FR2931585B1 (fr) | 2008-05-26 | 2008-05-26 | Traitement de surface par plasma d'azote dans un procede de collage direct |
FR0802833 | 2008-05-26 | ||
PCT/FR2009/000502 WO2009153422A1 (fr) | 2008-05-26 | 2009-04-28 | Traitement de surface par plasma d'azote dans un procédé de collage direct |
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JP2011523784A true JP2011523784A (ja) | 2011-08-18 |
JP2011523784A5 JP2011523784A5 (ja) | 2012-05-10 |
JP5661612B2 JP5661612B2 (ja) | 2015-01-28 |
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US (1) | US8318586B2 (ja) |
EP (1) | EP2304787B1 (ja) |
JP (1) | JP5661612B2 (ja) |
KR (1) | KR101453135B1 (ja) |
CN (1) | CN102047410B (ja) |
AT (1) | ATE529891T1 (ja) |
FR (1) | FR2931585B1 (ja) |
WO (1) | WO2009153422A1 (ja) |
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JP2009135430A (ja) * | 2007-10-10 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
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US9782772B2 (en) | 2014-10-31 | 2017-10-10 | Samsung Electronics Co., Ltd. | Method of bonding two surfaces and construct therefrom and microfluidic device containing the construct |
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CN102047410B (zh) | 2014-03-26 |
KR101453135B1 (ko) | 2014-10-27 |
US8318586B2 (en) | 2012-11-27 |
WO2009153422A1 (fr) | 2009-12-23 |
EP2304787A1 (fr) | 2011-04-06 |
ATE529891T1 (de) | 2011-11-15 |
EP2304787B1 (fr) | 2011-10-19 |
WO2009153422A8 (fr) | 2010-12-23 |
KR20110010740A (ko) | 2011-02-07 |
FR2931585A1 (fr) | 2009-11-27 |
US20110129986A1 (en) | 2011-06-02 |
FR2931585B1 (fr) | 2010-09-03 |
CN102047410A (zh) | 2011-05-04 |
JP5661612B2 (ja) | 2015-01-28 |
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