ATE529891T1 - Stickstoffplasma-oberflächenbehandlung in einem direktbindungsverfahren - Google Patents
Stickstoffplasma-oberflächenbehandlung in einem direktbindungsverfahrenInfo
- Publication number
- ATE529891T1 ATE529891T1 AT09765984T AT09765984T ATE529891T1 AT E529891 T1 ATE529891 T1 AT E529891T1 AT 09765984 T AT09765984 T AT 09765984T AT 09765984 T AT09765984 T AT 09765984T AT E529891 T1 ATE529891 T1 AT E529891T1
- Authority
- AT
- Austria
- Prior art keywords
- surface treatment
- plates
- less
- direct bond
- silicon
- Prior art date
Links
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 title abstract 4
- 238000004381 surface treatment Methods 0.000 title abstract 3
- 229910052757 nitrogen Inorganic materials 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000010409 thin film Substances 0.000 abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000009616 inductively coupled plasma Methods 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Sampling And Sample Adjustment (AREA)
- Treatments Of Macromolecular Shaped Articles (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0802833A FR2931585B1 (fr) | 2008-05-26 | 2008-05-26 | Traitement de surface par plasma d'azote dans un procede de collage direct |
| PCT/FR2009/000502 WO2009153422A1 (fr) | 2008-05-26 | 2009-04-28 | Traitement de surface par plasma d'azote dans un procédé de collage direct |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE529891T1 true ATE529891T1 (de) | 2011-11-15 |
Family
ID=40085439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT09765984T ATE529891T1 (de) | 2008-05-26 | 2009-04-28 | Stickstoffplasma-oberflächenbehandlung in einem direktbindungsverfahren |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8318586B2 (de) |
| EP (1) | EP2304787B1 (de) |
| JP (1) | JP5661612B2 (de) |
| KR (1) | KR101453135B1 (de) |
| CN (1) | CN102047410B (de) |
| AT (1) | ATE529891T1 (de) |
| FR (1) | FR2931585B1 (de) |
| WO (1) | WO2009153422A1 (de) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2964112B1 (fr) * | 2010-08-31 | 2013-07-19 | Commissariat Energie Atomique | Traitement avant collage d'une surface mixte cu-oxyde, par un plasma contenant de l'azote et de l'hydrogene |
| CN102222637A (zh) * | 2011-06-23 | 2011-10-19 | 北京大学 | 一种绝缘体上锗衬底的制备方法 |
| WO2013066977A1 (en) * | 2011-10-31 | 2013-05-10 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Methods for wafer bonding and for nucleating bonding nanophases using wet and steam pressurization |
| KR20130141985A (ko) * | 2012-06-18 | 2013-12-27 | 삼성전자주식회사 | 2개 표면을 결합시키는 방법 및 그에 의하여 제조된 구조물 |
| KR102023623B1 (ko) * | 2012-07-03 | 2019-09-23 | 삼성전자 주식회사 | 반도체 소자 형성 방법 |
| WO2014052476A2 (en) | 2012-09-25 | 2014-04-03 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On... | Methods for wafer bonding, and for nucleating bonding nanophases |
| WO2015043624A1 (de) | 2013-09-25 | 2015-04-02 | Ev Group E. Thallner Gmbh | Vorrichtung und verfahren zum bonden von substraten |
| KR102287811B1 (ko) | 2014-10-31 | 2021-08-09 | 삼성전자주식회사 | 2개 표면을 결합시키는 방법 및 그에 의하여 제조된 구조체, 및 상기 구조체를 포함하는 미세유동 장치 |
| TWI741988B (zh) * | 2015-07-31 | 2021-10-11 | 日商新力股份有限公司 | 堆疊式透鏡結構及其製造方法，以及電子裝置 |
| CN106409650B (zh) * | 2015-08-03 | 2019-01-29 | 沈阳硅基科技有限公司 | 一种硅片直接键合方法 |
| US9496239B1 (en) * | 2015-12-11 | 2016-11-15 | International Business Machines Corporation | Nitride-enriched oxide-to-oxide 3D wafer bonding |
| US10026716B2 (en) | 2016-04-15 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC formation with dies bonded to formed RDLs |
| US9716088B1 (en) | 2016-06-30 | 2017-07-25 | International Business Machines Corporation | 3D bonded semiconductor structure with an embedded capacitor |
| US9620479B1 (en) | 2016-06-30 | 2017-04-11 | International Business Machines Corporation | 3D bonded semiconductor structure with an embedded resistor |
| US9941241B2 (en) | 2016-06-30 | 2018-04-10 | International Business Machines Corporation | Method for wafer-wafer bonding |
| US9773741B1 (en) | 2016-08-17 | 2017-09-26 | Qualcomm Incorporated | Bondable device including a hydrophilic layer |
| US10269756B2 (en) | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
| FR3074959B1 (fr) * | 2017-12-08 | 2019-12-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de collage par adhesion directe |
| US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
| US10859981B1 (en) | 2019-10-21 | 2020-12-08 | Quantum Valley Ideas Laboratories | Vapor cells having one or more optical windows bonded to a dielectric body |
| US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
| US20220320035A1 (en) * | 2021-03-31 | 2022-10-06 | Invensas Bonding Technologies, Inc. | Direct bonding methods and structures |
| US11307233B1 (en) | 2021-04-13 | 2022-04-19 | Quantum Valley Ideas Laboratories | Vapor cells having stacks of layers defining target three-dimensional volumes for internal cavities |
| FR3131434B1 (fr) * | 2021-12-29 | 2023-12-15 | Commissariat Energie Atomique | Procédé d’activation d’une couche exposée |
| CN116022731B (zh) * | 2023-02-17 | 2023-07-07 | 西南应用磁学研究所(中国电子科技集团公司第九研究所) | 一种基于wlp工艺的mems磁通门传感器的制作方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
| US5503704A (en) * | 1993-01-06 | 1996-04-02 | The Regents Of The University Of California | Nitrogen based low temperature direct bonding |
| JP3294934B2 (ja) * | 1994-03-11 | 2002-06-24 | キヤノン株式会社 | 半導体基板の作製方法及び半導体基板 |
| US6902987B1 (en) * | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US7019339B2 (en) * | 2001-04-17 | 2006-03-28 | California Institute Of Technology | Method of using a germanium layer transfer to Si for photovoltaic applications and heterostructure made thereby |
| US6780788B2 (en) * | 2002-08-07 | 2004-08-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for improving within-wafer uniformity of gate oxide |
| JP3980539B2 (ja) * | 2003-08-29 | 2007-09-26 | 唯知 須賀 | 基板接合方法、照射方法、および基板接合装置 |
| JPWO2005022610A1 (ja) * | 2003-09-01 | 2007-11-01 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
| FR2867310B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
| US7361572B2 (en) * | 2005-02-17 | 2008-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | STI liner modification method |
| FR2888663B1 (fr) * | 2005-07-13 | 2008-04-18 | Soitec Silicon On Insulator | Procede de diminution de la rugosite d'une couche epaisse d'isolant |
| FR2910177B1 (fr) * | 2006-12-18 | 2009-04-03 | Soitec Silicon On Insulator | Couche tres fine enterree |
| JP2009135430A (ja) * | 2007-10-10 | 2009-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
-
2008
- 2008-05-26 FR FR0802833A patent/FR2931585B1/fr not_active Expired - Fee Related
-
2009
- 2009-04-28 WO PCT/FR2009/000502 patent/WO2009153422A1/fr active Application Filing
- 2009-04-28 KR KR1020107026487A patent/KR101453135B1/ko not_active IP Right Cessation
- 2009-04-28 EP EP09765984A patent/EP2304787B1/de active Active
- 2009-04-28 JP JP2011511049A patent/JP5661612B2/ja active Active
- 2009-04-28 AT AT09765984T patent/ATE529891T1/de not_active IP Right Cessation
- 2009-04-28 CN CN200980119383.1A patent/CN102047410B/zh not_active Expired - Fee Related
- 2009-04-28 US US12/994,792 patent/US8318586B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102047410B (zh) | 2014-03-26 |
| US20110129986A1 (en) | 2011-06-02 |
| KR101453135B1 (ko) | 2014-10-27 |
| EP2304787B1 (de) | 2011-10-19 |
| JP5661612B2 (ja) | 2015-01-28 |
| FR2931585B1 (fr) | 2010-09-03 |
| WO2009153422A8 (fr) | 2010-12-23 |
| JP2011523784A (ja) | 2011-08-18 |
| US8318586B2 (en) | 2012-11-27 |
| WO2009153422A1 (fr) | 2009-12-23 |
| FR2931585A1 (fr) | 2009-11-27 |
| CN102047410A (zh) | 2011-05-04 |
| KR20110010740A (ko) | 2011-02-07 |
| EP2304787A1 (de) | 2011-04-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |