JP2008147670A5 - - Google Patents

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Publication number
JP2008147670A5
JP2008147670A5 JP2007317313A JP2007317313A JP2008147670A5 JP 2008147670 A5 JP2008147670 A5 JP 2008147670A5 JP 2007317313 A JP2007317313 A JP 2007317313A JP 2007317313 A JP2007317313 A JP 2007317313A JP 2008147670 A5 JP2008147670 A5 JP 2008147670A5
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JP
Japan
Prior art keywords
terminal
equipment
package
integrated circuit
base portion
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JP2007317313A
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English (en)
Japanese (ja)
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JP2008147670A (ja
JP4900829B2 (ja
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Priority claimed from US11/608,829 external-priority patent/US7635913B2/en
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Publication of JP2008147670A5 publication Critical patent/JP2008147670A5/ja
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Publication of JP4900829B2 publication Critical patent/JP4900829B2/ja
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JP2007317313A 2006-12-09 2007-12-07 積重ねられた集積回路パッケージインパッケージの製造方法および積重ねられた集積回路パッケージインパッケージシステム Active JP4900829B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/608,829 2006-12-09
US11/608,829 US7635913B2 (en) 2006-12-09 2006-12-09 Stacked integrated circuit package-in-package system

Publications (3)

Publication Number Publication Date
JP2008147670A JP2008147670A (ja) 2008-06-26
JP2008147670A5 true JP2008147670A5 (enExample) 2011-01-27
JP4900829B2 JP4900829B2 (ja) 2012-03-21

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ID=39497001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007317313A Active JP4900829B2 (ja) 2006-12-09 2007-12-07 積重ねられた集積回路パッケージインパッケージの製造方法および積重ねられた集積回路パッケージインパッケージシステム

Country Status (4)

Country Link
US (2) US7635913B2 (enExample)
JP (1) JP4900829B2 (enExample)
KR (1) KR101454884B1 (enExample)
TW (1) TWI345299B (enExample)

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US8432026B2 (en) * 2006-08-04 2013-04-30 Stats Chippac Ltd. Stackable multi-chip package system
US8642383B2 (en) * 2006-09-28 2014-02-04 Stats Chippac Ltd. Dual-die package structure having dies externally and simultaneously connected via bump electrodes and bond wires
US7608921B2 (en) * 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package
US7759783B2 (en) * 2006-12-07 2010-07-20 Stats Chippac Ltd. Integrated circuit package system employing thin profile techniques
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US8487420B1 (en) * 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US9355962B2 (en) 2009-06-12 2016-05-31 Stats Chippac Ltd. Integrated circuit package stacking system with redistribution and method of manufacture thereof
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KR101686553B1 (ko) 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
KR20120110451A (ko) 2011-03-29 2012-10-10 삼성전자주식회사 반도체 패키지
CN103474421B (zh) * 2013-08-30 2016-10-12 晟碟信息科技（上海）有限公司 高产量半导体装置
TWI602267B (zh) * 2014-06-13 2017-10-11 矽品精密工業股份有限公司 封裝結構及其製法
KR20160116923A (ko) 2015-03-31 2016-10-10 동우 화인켐 주식회사 대전방지 하드코팅 조성물 및 이를 이용한 광학 시트
US9871007B2 (en) * 2015-09-25 2018-01-16 Intel Corporation Packaged integrated circuit device with cantilever structure
KR102649471B1 (ko) 2016-09-05 2024-03-21 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR102556518B1 (ko) * 2018-10-18 2023-07-18 에스케이하이닉스 주식회사 상부 칩 스택을 지지하는 서포팅 블록을 포함하는 반도체 패키지
KR102767617B1 (ko) * 2019-08-12 2025-02-17 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
TWI744869B (zh) * 2020-04-20 2021-11-01 力成科技股份有限公司 封裝結構及其製造方法
JP2022094390A (ja) * 2020-12-15 2022-06-27 Tdk株式会社 電子回路モジュール及びその製造方法

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US7622333B2 (en) 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7645638B2 (en) 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
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US8304874B2 (en) * 2006-12-09 2012-11-06 Stats Chippac Ltd. Stackable integrated circuit package system
US7772683B2 (en) * 2006-12-09 2010-08-10 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

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