JP2008091927A5 - - Google Patents
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- Publication number
- JP2008091927A5 JP2008091927A5 JP2007259038A JP2007259038A JP2008091927A5 JP 2008091927 A5 JP2008091927 A5 JP 2008091927A5 JP 2007259038 A JP2007259038 A JP 2007259038A JP 2007259038 A JP2007259038 A JP 2007259038A JP 2008091927 A5 JP2008091927 A5 JP 2008091927A5
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- JP
- Japan
- Prior art keywords
- cell array
- region
- distance
- array region
- conductive lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 12
- 238000001459 lithography Methods 0.000 claims 5
- 238000000034 method Methods 0.000 claims 5
- 239000000758 substrate Substances 0.000 claims 2
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060097266A KR100810616B1 (ko) | 2006-10-02 | 2006-10-02 | 미세 선폭의 도전성 라인들을 갖는 반도체소자 및 그제조방법 |
| KR10-2006-0097266 | 2006-10-02 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008091927A JP2008091927A (ja) | 2008-04-17 |
| JP2008091927A5 true JP2008091927A5 (enExample) | 2010-11-18 |
| JP5602986B2 JP5602986B2 (ja) | 2014-10-08 |
Family
ID=39375665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007259038A Active JP5602986B2 (ja) | 2006-10-02 | 2007-10-02 | 微細線幅の導電性ラインを有する半導体素子 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7888720B2 (enExample) |
| JP (1) | JP5602986B2 (enExample) |
| KR (1) | KR100810616B1 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7745876B2 (en) * | 2007-02-21 | 2010-06-29 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit devices including gate patterns having step difference therebetween and a connection line disposed between the gate patterns and methods of fabricating the same |
| US8222159B2 (en) * | 2008-08-25 | 2012-07-17 | Elpida Memory, Inc. | Manufacturing method of semiconductor device |
| KR101565798B1 (ko) * | 2009-03-31 | 2015-11-05 | 삼성전자주식회사 | 콘택 패드와 도전 라인과의 일체형 구조를 가지는 반도체 소자 |
| KR101645720B1 (ko) | 2009-09-15 | 2016-08-05 | 삼성전자주식회사 | 패턴 구조물 및 이의 형성 방법. |
| KR20120126433A (ko) | 2011-05-11 | 2012-11-21 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
| KR20130078210A (ko) * | 2011-12-30 | 2013-07-10 | 에스케이하이닉스 주식회사 | 반도체 소자 및 그 제조 방법 |
| KR101950350B1 (ko) * | 2012-07-19 | 2019-02-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그의 제조 방법 |
| US8921216B2 (en) * | 2012-07-19 | 2014-12-30 | SK Hynix Inc. | Semiconductor device and method of fabricating the same |
| US20160351573A1 (en) * | 2013-03-25 | 2016-12-01 | Hiroshi Yoshino | Semiconductor device and method for manufacturing the same |
| KR20230054562A (ko) | 2021-10-15 | 2023-04-25 | 삼성전자주식회사 | 반도체 장치 |
| CN116568024A (zh) * | 2022-01-27 | 2023-08-08 | 芯盟科技有限公司 | 半导体结构及其制造方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2862584B2 (ja) * | 1989-08-31 | 1999-03-03 | 株式会社東芝 | 不揮発性半導体メモリ装置 |
| JPH04274362A (ja) * | 1991-02-28 | 1992-09-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH04352469A (ja) * | 1991-05-30 | 1992-12-07 | Nec Corp | 半導体記憶装置 |
| KR960008572B1 (en) * | 1993-03-15 | 1996-06-28 | Hyundai Electronics Ind | Dram device |
| JP2006245625A (ja) | 1997-06-20 | 2006-09-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| JP3281304B2 (ja) * | 1997-11-28 | 2002-05-13 | 株式会社東芝 | 半導体集積回路装置 |
| JP2000019709A (ja) * | 1998-07-03 | 2000-01-21 | Hitachi Ltd | 半導体装置及びパターン形成方法 |
| JP3420089B2 (ja) * | 1998-11-04 | 2003-06-23 | Necエレクトロニクス株式会社 | 電子デバイス並びに半導体装置、及び電極形成方法 |
| JP2000307084A (ja) * | 1999-04-23 | 2000-11-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| JP4936582B2 (ja) * | 2000-07-28 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| JP4103497B2 (ja) | 2002-04-18 | 2008-06-18 | ソニー株式会社 | 記憶装置とその製造方法および使用方法、半導体装置とその製造方法 |
| KR100454131B1 (ko) * | 2002-06-05 | 2004-10-26 | 삼성전자주식회사 | 라인형 패턴을 갖는 반도체 소자 및 그 레이아웃 방법 |
| JP2004134702A (ja) | 2002-10-15 | 2004-04-30 | Renesas Technology Corp | 不揮発性半導体記憶装置 |
| DE10260185B4 (de) | 2002-12-20 | 2007-04-12 | Infineon Technologies Ag | Halbleiterspeicher mit vertikalen Charge-trapping-Speicherzellen und Verfahren zu seiner Herstellung |
| KR100539276B1 (ko) | 2003-04-02 | 2005-12-27 | 삼성전자주식회사 | 게이트 라인을 포함하는 반도체 장치 및 이의 제조 방법 |
| JP4498088B2 (ja) * | 2004-10-07 | 2010-07-07 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
| US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
-
2006
- 2006-10-02 KR KR1020060097266A patent/KR100810616B1/ko active Active
-
2007
- 2007-10-02 JP JP2007259038A patent/JP5602986B2/ja active Active
- 2007-10-02 US US11/865,738 patent/US7888720B2/en active Active
-
2011
- 2011-01-27 US US13/014,952 patent/US8164119B2/en active Active
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