JP2008060408A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2008060408A
JP2008060408A JP2006236740A JP2006236740A JP2008060408A JP 2008060408 A JP2008060408 A JP 2008060408A JP 2006236740 A JP2006236740 A JP 2006236740A JP 2006236740 A JP2006236740 A JP 2006236740A JP 2008060408 A JP2008060408 A JP 2008060408A
Authority
JP
Japan
Prior art keywords
region
transistor
film
silicon
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006236740A
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English (en)
Japanese (ja)
Inventor
Akira Sotozono
明 外園
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2006236740A priority Critical patent/JP2008060408A/ja
Priority to TW096129961A priority patent/TW200816385A/zh
Priority to US11/847,865 priority patent/US20080054364A1/en
Publication of JP2008060408A publication Critical patent/JP2008060408A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8312—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2006236740A 2006-08-31 2006-08-31 半導体装置 Pending JP2008060408A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006236740A JP2008060408A (ja) 2006-08-31 2006-08-31 半導体装置
TW096129961A TW200816385A (en) 2006-08-31 2007-08-14 Semiconductor device having CMOS elements
US11/847,865 US20080054364A1 (en) 2006-08-31 2007-08-30 Semiconductor device having cmos device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006236740A JP2008060408A (ja) 2006-08-31 2006-08-31 半導体装置

Publications (1)

Publication Number Publication Date
JP2008060408A true JP2008060408A (ja) 2008-03-13

Family

ID=39150294

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006236740A Pending JP2008060408A (ja) 2006-08-31 2006-08-31 半導体装置

Country Status (3)

Country Link
US (1) US20080054364A1 (enExample)
JP (1) JP2008060408A (enExample)
TW (1) TW200816385A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010111A (ja) * 2007-06-27 2009-01-15 Sony Corp 半導体装置および半導体装置の製造方法
WO2009122542A1 (ja) * 2008-03-31 2009-10-08 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP2010004016A (ja) * 2008-03-17 2010-01-07 Toshiba Corp Ｓｒａｍデバイスにおけるｈｏｔプロセスｓｔｉおよび製造方法
JP2011527102A (ja) * 2008-06-30 2011-10-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 凹状のドレイン及びソース区域並びに非共形的な金属シリサイド領域を有するｍｏｓトランジスタを備えたｃｍｏｓデバイス
JP2012510712A (ja) * 2008-08-29 2012-05-10 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 同一の能動領域内に形成されるトランジスタにおいて能動領域内に局所的に埋め込み歪誘起半導体材質を設けることによる駆動電流調節

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100890848B1 (ko) 2004-03-12 2009-03-27 니뽄 다바코 산교 가부시키가이샤 봉모양 끽연물품의 힌지 리드형 패키지
US20100109045A1 (en) * 2008-10-30 2010-05-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing stress-engineered layers
US8106456B2 (en) * 2009-07-29 2012-01-31 International Business Machines Corporation SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics
US9087687B2 (en) 2011-12-23 2015-07-21 International Business Machines Corporation Thin heterostructure channel device
CN103515435B (zh) * 2012-06-26 2016-12-21 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其形成方法、sram存储单元电路
US9679818B2 (en) * 2014-10-31 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188274A (ja) * 2001-12-19 2003-07-04 Toshiba Corp 半導体装置及びその製造方法
KR100450683B1 (ko) * 2002-09-04 2004-10-01 삼성전자주식회사 Ｓｏｉ 기판에 형성되는 에스램 디바이스
US6900502B2 (en) * 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
US7198995B2 (en) * 2003-12-12 2007-04-03 International Business Machines Corporation Strained finFETs and method of manufacture
US7098499B2 (en) * 2004-08-16 2006-08-29 Chih-Hsin Wang Electrically alterable non-volatile memory cell
EP1911086A2 (en) * 2005-07-26 2008-04-16 Amberwave Systems Corporation Solutions integrated circuit integration of alternative active area materials
US8441000B2 (en) * 2006-02-01 2013-05-14 International Business Machines Corporation Heterojunction tunneling field effect transistors, and methods for fabricating the same
US7342284B2 (en) * 2006-02-16 2008-03-11 United Microelectronics Corp. Semiconductor MOS transistor device and method for making the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010111A (ja) * 2007-06-27 2009-01-15 Sony Corp 半導体装置および半導体装置の製造方法
US8486793B2 (en) 2007-06-27 2013-07-16 Sony Corporation Method for manufacturing semiconductor device with semiconductor materials with different lattice constants
US9070704B2 (en) 2007-06-27 2015-06-30 Sony Corporation Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion
US9356146B2 (en) 2007-06-27 2016-05-31 Sony Corporation Semiconductor device with recess, epitaxial source/drain region and diffuson
US12295157B2 (en) 2007-06-27 2025-05-06 Sony Corporation Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion
JP2010004016A (ja) * 2008-03-17 2010-01-07 Toshiba Corp Ｓｒａｍデバイスにおけるｈｏｔプロセスｓｔｉおよび製造方法
WO2009122542A1 (ja) * 2008-03-31 2009-10-08 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US8288757B2 (en) 2008-03-31 2012-10-16 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method thereof
JP2011527102A (ja) * 2008-06-30 2011-10-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 凹状のドレイン及びソース区域並びに非共形的な金属シリサイド領域を有するｍｏｓトランジスタを備えたｃｍｏｓデバイス
US8673713B2 (en) 2008-06-30 2014-03-18 Advanced Micro Devices, Inc. Method for forming a transistor with recessed drain and source areas and non-conformal metal silicide regions
JP2012510712A (ja) * 2008-08-29 2012-05-10 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 同一の能動領域内に形成されるトランジスタにおいて能動領域内に局所的に埋め込み歪誘起半導体材質を設けることによる駆動電流調節

Also Published As

Publication number Publication date
US20080054364A1 (en) 2008-03-06
TW200816385A (en) 2008-04-01
TWI358792B (enExample) 2012-02-21

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