JP2008034865A - 半導体デバイスの製造方法。 - Google Patents
半導体デバイスの製造方法。 Download PDFInfo
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- JP2008034865A JP2008034865A JP2007237928A JP2007237928A JP2008034865A JP 2008034865 A JP2008034865 A JP 2008034865A JP 2007237928 A JP2007237928 A JP 2007237928A JP 2007237928 A JP2007237928 A JP 2007237928A JP 2008034865 A JP2008034865 A JP 2008034865A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 abstract description 5
- 230000015654 memory Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】半導体基板内に複数のトランジスタを形成し、この半導体基板を覆うように第1の誘電体層を形成する。第1のトランジスタ部分と第2のトランジスタ部分を露出するための第1開口を形成するために、第1の誘電体層を選択的にエッチングする。導電性材料が第1トランジスタ部分と第2トランジスタ部分の間の併合接点を規定する第1開口内に堆積される。この併合接点は、ゼロウィンドゥレベルで形成され、広いランディングパッド領域を提供することを特徴とする。
【選択図】図3
Description
22 トランジスタ
22A 第1トランジスタ
22B 第2トランジスタ
22C 第3トランジスタ
22D 第4トランジスタ
24 半導体基板
26 浅いトレンチ絶縁領域
28 ゲート誘電体層
30 チャネル領域
32 ゲート
34 共有ソース/ドレイン領域
36,38 スペーサー
40 第1誘電体層
42 併合接点
44 導電性材料
50 第2誘電体層
60 自己整合接点
62 第1貫通導体
64 第2貫通導体
72 第1接続
74 第3貫通導体
80 開始
82 基板内に複数のトランジスタを形成する
84 基板を覆うように第1誘電体層を形成する
86 第1と第2のトランジスタ領域を露出する第1開口を形成するために、第1誘電体層を選択的にエッチングする
88 併合接点を形成するために、第1開口内に導電性材料を堆積する
90 第1誘電体層を覆うように第2誘電体層を形成する
92 併合接点を露出する第2誘電体層を選択的にエッチングし、第3トランジスタのソース/ドレイン領域を露出する第1と第2の誘電体層を選択的にエッチングする
94 併合接点を具備する第1貫通導体を形成する導電性材料を堆積し、第3トランジスタのソース/ドレイン領域を具備する第2貫通導体を形成する
96 終了
Claims (1)
- (A) 複数のトランジスタを半導体基板内に形成するステップと、
(B) 前記半導体基板を覆うように第1誘電体層を形成するステップと、
(C) 第1トランジスタ部分と第2トランジスタ部分を露出する第1開口を形成するために、前記第1誘電体層を選択的にエッチングするステップと、
(D) 前記第1トランジスタ部分と第2トランジスタ部分の間に併合接点を形成するために、前記第1開口内に導電性材料を堆積するステップと、
(E) 前記第1誘電体層と併合接点を覆うように第2誘電体層を形成するステップと、
(F) 前記併合接点を露出する第2開口を形成するために、前記第2誘電体層を選択的にエッチングするステップと、
(G) 併合接点を具備した第1貫通導体を形成するために、前記第2開口に導電性材料を堆積するステップと、
を有することを特徴とする半導体デバイスの製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/484,759 US6274409B1 (en) | 2000-01-18 | 2000-01-18 | Method for making a semiconductor device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001009397A Division JP4718021B2 (ja) | 2000-01-18 | 2001-01-17 | 半導体デバイスの製造方法。 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008034865A true JP2008034865A (ja) | 2008-02-14 |
Family
ID=23925486
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001009397A Expired - Fee Related JP4718021B2 (ja) | 2000-01-18 | 2001-01-17 | 半導体デバイスの製造方法。 |
JP2007237928A Pending JP2008034865A (ja) | 2000-01-18 | 2007-09-13 | 半導体デバイスの製造方法。 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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JP2001009397A Expired - Fee Related JP4718021B2 (ja) | 2000-01-18 | 2001-01-17 | 半導体デバイスの製造方法。 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6274409B1 (ja) |
JP (2) | JP4718021B2 (ja) |
KR (1) | KR100676643B1 (ja) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100265772B1 (ko) * | 1998-07-22 | 2000-10-02 | 윤종용 | 반도체 장치의 배선구조 및 그 제조방법 |
US6479377B1 (en) | 2001-06-05 | 2002-11-12 | Micron Technology, Inc. | Method for making semiconductor devices having contact plugs and local interconnects |
KR100408414B1 (ko) * | 2001-06-20 | 2003-12-06 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
US7029963B2 (en) * | 2001-08-30 | 2006-04-18 | Micron Technology, Inc. | Semiconductor damascene trench and methods thereof |
US6730553B2 (en) * | 2001-08-30 | 2004-05-04 | Micron Technology, Inc. | Methods for making semiconductor structures having high-speed areas and high-density areas |
DE10305365B4 (de) * | 2003-02-10 | 2005-02-10 | Infineon Technologies Ag | Verfahren und Anordnung zum Kontaktieren von Anschlüssen eines Bipolartransistors |
US8405216B2 (en) * | 2005-06-29 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for integrated circuits |
JP5090671B2 (ja) * | 2005-08-01 | 2012-12-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
DE102005052000B3 (de) * | 2005-10-31 | 2007-07-05 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit einer Kontaktstruktur auf der Grundlage von Kupfer und Wolfram |
DE102005063092B3 (de) * | 2005-12-30 | 2007-07-19 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit einer Kontaktstruktur mit erhöhter Ätzselektivität |
US7968950B2 (en) * | 2007-06-27 | 2011-06-28 | Texas Instruments Incorporated | Semiconductor device having improved gate electrode placement and decreased area design |
JP5444694B2 (ja) * | 2008-11-12 | 2014-03-19 | ソニー株式会社 | 固体撮像装置、その製造方法および撮像装置 |
US8581348B2 (en) * | 2011-12-13 | 2013-11-12 | GlobalFoundries, Inc. | Semiconductor device with transistor local interconnects |
US8778789B2 (en) * | 2012-11-30 | 2014-07-15 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits having low resistance metal gate structures |
US9293414B2 (en) | 2013-06-26 | 2016-03-22 | Globalfoundries Inc. | Electronic fuse having a substantially uniform thermal profile |
US8981492B2 (en) * | 2013-06-26 | 2015-03-17 | Globalfoundries Inc. | Methods of forming an e-fuse for an integrated circuit product and the resulting integrated circuit product |
CN104752328B (zh) * | 2013-12-30 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | 导电插塞的形成方法 |
US9443851B2 (en) | 2014-01-03 | 2016-09-13 | Samsung Electronics Co., Ltd. | Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the same |
US9721956B2 (en) * | 2014-05-15 | 2017-08-01 | Taiwan Semiconductor Manufacturing Company Limited | Methods, structures and devices for intra-connection structures |
US9978755B2 (en) * | 2014-05-15 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company Limited | Methods and devices for intra-connection structures |
US9805935B2 (en) * | 2015-12-31 | 2017-10-31 | International Business Machines Corporation | Bottom source/drain silicidation for vertical field-effect transistor (FET) |
US10388654B2 (en) * | 2018-01-11 | 2019-08-20 | Globalfoundries Inc. | Methods of forming a gate-to-source/drain contact structure |
US10651178B2 (en) * | 2018-02-14 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Compact electrical connection that can be used to form an SRAM cell and method of making the same |
US11189566B2 (en) | 2018-04-12 | 2021-11-30 | International Business Machines Corporation | Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10209071A (ja) * | 1997-01-15 | 1998-08-07 | Internatl Business Mach Corp <Ibm> | 改善された半導体の接触部構造形成方法 |
JPH10242419A (ja) * | 1997-02-27 | 1998-09-11 | Mitsubishi Electric Corp | 半導体装置の製造方法及び半導体装置 |
JP2000003966A (ja) * | 1998-06-15 | 2000-01-07 | Nec Corp | 半導体記憶装置及びその製造方法 |
JP2000012802A (ja) * | 1998-06-17 | 2000-01-14 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63296243A (ja) * | 1987-05-27 | 1988-12-02 | Toshiba Corp | 半導体装置の製造方法 |
JPH0732159B2 (ja) * | 1987-05-27 | 1995-04-10 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH0226024A (ja) * | 1988-07-15 | 1990-01-29 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH0955440A (ja) * | 1995-08-17 | 1997-02-25 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
US5668065A (en) * | 1996-08-01 | 1997-09-16 | Winbond Electronics Corp. | Process for simultaneous formation of silicide-based self-aligned contacts and local interconnects |
US5759882A (en) | 1996-10-16 | 1998-06-02 | National Semiconductor Corporation | Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) |
TW346678B (en) * | 1997-03-25 | 1998-12-01 | Vanguard Int Semiconduct Corp | Method for producing memory cell array |
US5843816A (en) * | 1997-07-28 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell |
US5807779A (en) * | 1997-07-30 | 1998-09-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process |
JP3807836B2 (ja) * | 1997-11-28 | 2006-08-09 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
TW368731B (en) * | 1997-12-22 | 1999-09-01 | United Microelectronics Corp | Manufacturing method for self-aligned local-interconnect and contact |
JPH11345887A (ja) * | 1998-03-31 | 1999-12-14 | Seiko Epson Corp | 半導体装置およびその製造方法 |
US5915199A (en) * | 1998-06-04 | 1999-06-22 | Sharp Microelectronics Technology, Inc. | Method for manufacturing a CMOS self-aligned strapped interconnection |
-
2000
- 2000-01-18 US US09/484,759 patent/US6274409B1/en not_active Expired - Lifetime
-
2001
- 2001-01-17 JP JP2001009397A patent/JP4718021B2/ja not_active Expired - Fee Related
- 2001-01-18 KR KR1020010002872A patent/KR100676643B1/ko not_active IP Right Cessation
-
2007
- 2007-09-13 JP JP2007237928A patent/JP2008034865A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10209071A (ja) * | 1997-01-15 | 1998-08-07 | Internatl Business Mach Corp <Ibm> | 改善された半導体の接触部構造形成方法 |
JPH10242419A (ja) * | 1997-02-27 | 1998-09-11 | Mitsubishi Electric Corp | 半導体装置の製造方法及び半導体装置 |
JP2000003966A (ja) * | 1998-06-15 | 2000-01-07 | Nec Corp | 半導体記憶装置及びその製造方法 |
JP2000012802A (ja) * | 1998-06-17 | 2000-01-14 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
Also Published As
Publication number | Publication date |
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KR100676643B1 (ko) | 2007-02-01 |
KR20010076341A (ko) | 2001-08-11 |
JP4718021B2 (ja) | 2011-07-06 |
US6274409B1 (en) | 2001-08-14 |
JP2001244348A (ja) | 2001-09-07 |
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