JP2007523034A - アモルファスカーボン膜を含む構造およびその形成方法。 - Google Patents

アモルファスカーボン膜を含む構造およびその形成方法。 Download PDF

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Publication number
JP2007523034A
JP2007523034A JP2006551053A JP2006551053A JP2007523034A JP 2007523034 A JP2007523034 A JP 2007523034A JP 2006551053 A JP2006551053 A JP 2006551053A JP 2006551053 A JP2006551053 A JP 2006551053A JP 2007523034 A JP2007523034 A JP 2007523034A
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Prior art keywords
layer
amorphous carbon
pattern
hard mask
forming
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Japanese (ja)
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JP2007523034A5 (enExample
Inventor
ウェッツェル、ジェフレイ・ティー．
ワン、デイビッド・シー．
リー、エリック・エム．
トマ、ドレル・イオアン
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Publication of JP2007523034A publication Critical patent/JP2007523034A/ja
Publication of JP2007523034A5 publication Critical patent/JP2007523034A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Carbon And Carbon Compounds (AREA)
JP2006551053A 2004-01-30 2004-12-17 アモルファスカーボン膜を含む構造およびその形成方法。 Withdrawn JP2007523034A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/766,872 US7115993B2 (en) 2004-01-30 2004-01-30 Structure comprising amorphous carbon film and method of forming thereof
PCT/US2004/039771 WO2005074449A2 (en) 2004-01-30 2004-12-17 Structure comprising amorphous carbon film and method of forming thereof

Publications (2)

Publication Number Publication Date
JP2007523034A true JP2007523034A (ja) 2007-08-16
JP2007523034A5 JP2007523034A5 (enExample) 2008-01-31

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JP2006551053A Withdrawn JP2007523034A (ja) 2004-01-30 2004-12-17 アモルファスカーボン膜を含む構造およびその形成方法。

Country Status (4)

Country Link
US (1) US7115993B2 (enExample)
JP (1) JP2007523034A (enExample)
TW (1) TWI280987B (enExample)
WO (1) WO2005074449A2 (enExample)

Cited By (10)

* Cited by examiner, † Cited by third party
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JP2007128938A (ja) * 2005-11-01 2007-05-24 Elpida Memory Inc 半導体装置の製造方法
JP2009253246A (ja) * 2008-04-11 2009-10-29 Spansion Llc 半導体装置および半導体装置の製造方法
JP2009253245A (ja) * 2008-04-11 2009-10-29 Spansion Llc 半導体装置の製造方法
JP2010503218A (ja) * 2006-08-29 2010-01-28 マイクロン テクノロジー， インク． スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法
JP5113830B2 (ja) * 2007-02-28 2013-01-09 東京エレクトロン株式会社 アモルファスカーボン膜の形成方法、半導体装置の製造方法およびコンピュータ可読記憶媒体
KR20130046351A (ko) 2011-10-27 2013-05-07 도쿄엘렉트론가부시키가이샤 성막 장치 및 그 운용 방법
JP2013093526A (ja) * 2011-10-27 2013-05-16 Tokyo Electron Ltd 成膜装置及びその運用方法
US8592324B2 (en) 2010-02-05 2013-11-26 Tokyo Electron Limited Method for forming laminated structure including amorphous carbon film
JP2023524253A (ja) * 2020-05-05 2023-06-09 ラム リサーチ コーポレーション ハードマスクの選択性改善のための不活性ガス注入
KR20250022720A (ko) 2022-06-15 2025-02-17 가부시끼가이샤 레조낙 Cmp 연마액 및 연마 방법

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US7371461B2 (en) * 2005-01-13 2008-05-13 International Business Machines Corporation Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics
US7291553B2 (en) * 2005-03-08 2007-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming dual damascene with improved etch profiles
US7422775B2 (en) 2005-05-17 2008-09-09 Applied Materials, Inc. Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing
US7312162B2 (en) 2005-05-17 2007-12-25 Applied Materials, Inc. Low temperature plasma deposition process for carbon layer deposition
US7857982B2 (en) * 2005-07-19 2010-12-28 Micron Technology, Inc. Methods of etching features into substrates
US7335611B2 (en) 2005-08-08 2008-02-26 Applied Materials, Inc. Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer
US7312148B2 (en) 2005-08-08 2007-12-25 Applied Materials, Inc. Copper barrier reflow process employing high speed optical annealing
US7429532B2 (en) 2005-08-08 2008-09-30 Applied Materials, Inc. Semiconductor substrate process using an optically writable carbon-containing mask
US7323401B2 (en) * 2005-08-08 2008-01-29 Applied Materials, Inc. Semiconductor substrate process using a low temperature deposited carbon-containing hard mask
US7422975B2 (en) * 2005-08-18 2008-09-09 Sony Corporation Composite inter-level dielectric structure for an integrated circuit
US7602068B2 (en) 2006-01-19 2009-10-13 International Machines Corporation Dual-damascene process to fabricate thick wire structure
US7563688B2 (en) * 2006-02-24 2009-07-21 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US20070243714A1 (en) * 2006-04-18 2007-10-18 Applied Materials, Inc. Method of controlling silicon-containing polymer build up during etching by using a periodic cleaning step
US7867578B2 (en) * 2006-06-28 2011-01-11 Applied Materials, Inc. Method for depositing an amorphous carbon film with improved density and step coverage
US8129282B2 (en) 2006-07-19 2012-03-06 Tokyo Electron Limited Plasma etching method and computer-readable storage medium
JP2008028022A (ja) * 2006-07-19 2008-02-07 Tokyo Electron Ltd プラズマエッチング方法およびコンピュータ読取可能な記憶媒体
US20080124912A1 (en) * 2006-08-01 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor methods
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
JP4237216B2 (ja) * 2006-10-05 2009-03-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
EP2109880A4 (en) * 2007-02-05 2012-07-04 Bae Sys Inf & Elect Sys Integ SUBSEQUENTLY SUPPORTED MICROBOLOMETER PIXEL
US7763987B2 (en) 2007-02-27 2010-07-27 Qimonda Ag Integrated circuit and methods of manufacturing a contact arrangement and an interconnection arrangement
TWI455203B (zh) * 2007-05-03 2014-10-01 蘭姆研究公司 開孔之硬遮罩及藉由開孔之硬遮罩施行之蝕刻輪廓控制
US7858514B2 (en) 2007-06-29 2010-12-28 Qimonda Ag Integrated circuit, intermediate structure and a method of fabricating a semiconductor structure
US8021933B2 (en) 2007-08-29 2011-09-20 Qimonda Ag Integrated circuit including structures arranged at different densities and method of forming the same
US8084862B2 (en) * 2007-09-20 2011-12-27 International Business Machines Corporation Interconnect structures with patternable low-k dielectrics and method of fabricating same
US7709370B2 (en) * 2007-09-20 2010-05-04 International Business Machines Corporation Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures
US8618663B2 (en) * 2007-09-20 2013-12-31 International Business Machines Corporation Patternable dielectric film structure with improved lithography and method of fabricating same
US8298931B2 (en) * 2007-09-28 2012-10-30 Sandisk 3D Llc Dual damascene with amorphous carbon for 3D deep via/trench application
US9136463B2 (en) * 2007-11-20 2015-09-15 Qualcomm Incorporated Method of forming a magnetic tunnel junction structure
DE102008016425B4 (de) * 2008-03-31 2015-11-19 Advanced Micro Devices, Inc. Verfahren zur Strukturierung einer Metallisierungsschicht durch Verringerung der durch Lackentfernung hervorgerufenen Schäden des dielektrischen Materials
US20090266790A1 (en) * 2008-04-28 2009-10-29 Hamid Balamane Method of making a magnetoresistive reader structure
US9245792B2 (en) * 2008-07-25 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming interconnect structures
US8227339B2 (en) 2009-11-02 2012-07-24 International Business Machines Corporation Creation of vias and trenches with different depths
US8592321B2 (en) * 2011-06-08 2013-11-26 United Microelectronics Corp. Method for fabricating an aperture
US8759234B2 (en) 2011-10-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Deposited material and method of formation
US9230854B2 (en) 2013-04-08 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9502365B2 (en) * 2013-12-31 2016-11-22 Texas Instruments Incorporated Opening in a multilayer polymeric dielectric layer without delamination
FR3018951B1 (fr) * 2014-03-18 2017-06-09 Commissariat Energie Atomique Procede de gravure d'un materiau dielectrique poreux
CN105226049B (zh) * 2014-06-26 2019-02-26 中芯国际集成电路制造(上海)有限公司 用于互连层结构的掩膜组件及互连层的制作方法
US9437484B2 (en) 2014-10-17 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Etch stop layer in integrated circuits
US9859127B1 (en) * 2016-06-10 2018-01-02 Lam Research Corporation Line edge roughness improvement with photon-assisted plasma process
WO2018026412A1 (en) * 2016-08-02 2018-02-08 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Naval Research Laboratory Fabrication method for digital etching of nanometer-scale level structures
US11764062B2 (en) * 2017-11-13 2023-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor structure
US10529586B2 (en) * 2018-05-25 2020-01-07 Nanya Technology Corporation Method of manufacturing semiconductor device
JP7717721B2 (ja) * 2020-04-17 2025-08-04 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング 炭素材料、金属有機化合物および溶媒を含んでなるスピンコーティング組成物、および基板の上方への金属酸化物膜の製造方法
US11942371B2 (en) * 2020-09-29 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Etch profile control of via opening
CN119764256B (zh) * 2025-03-06 2025-07-22 合肥晶合集成电路股份有限公司 半导体器件及其制备方法

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128938A (ja) * 2005-11-01 2007-05-24 Elpida Memory Inc 半導体装置の製造方法
US7767569B2 (en) 2005-11-01 2010-08-03 Elpida Memory, Inc. Method of manufacturing semiconductor device
JP2010503218A (ja) * 2006-08-29 2010-01-28 マイクロン テクノロジー， インク． スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法
JP5113830B2 (ja) * 2007-02-28 2013-01-09 東京エレクトロン株式会社 アモルファスカーボン膜の形成方法、半導体装置の製造方法およびコンピュータ可読記憶媒体
JP2009253246A (ja) * 2008-04-11 2009-10-29 Spansion Llc 半導体装置および半導体装置の製造方法
JP2009253245A (ja) * 2008-04-11 2009-10-29 Spansion Llc 半導体装置の製造方法
US8592324B2 (en) 2010-02-05 2013-11-26 Tokyo Electron Limited Method for forming laminated structure including amorphous carbon film
JP2013093526A (ja) * 2011-10-27 2013-05-16 Tokyo Electron Ltd 成膜装置及びその運用方法
KR20130046351A (ko) 2011-10-27 2013-05-07 도쿄엘렉트론가부시키가이샤 성막 장치 및 그 운용 방법
US8993456B2 (en) 2011-10-27 2015-03-31 Tokyo Electron Limited Film forming apparatus and method of operating the same
US9279183B2 (en) 2011-10-27 2016-03-08 Tokyo Electron Limited Film forming apparatus and method of operating the same
JP2023524253A (ja) * 2020-05-05 2023-06-09 ラム リサーチ コーポレーション ハードマスクの選択性改善のための不活性ガス注入
JP7668292B2 (ja) 2020-05-05 2025-04-24 ラム リサーチ コーポレーション ハードマスクの選択性改善のための不活性ガス注入
US12456621B2 (en) 2020-05-05 2025-10-28 Lam Research Corporation Inert gas implantation for hard mask selectivity improvement
KR102915604B1 (ko) 2020-05-05 2026-01-21 램 리써치 코포레이션 하드 마스크 선택도 (selectivity) 개선을 위한 불활성 가스 주입
KR20250022720A (ko) 2022-06-15 2025-02-17 가부시끼가이샤 레조낙 Cmp 연마액 및 연마 방법

Also Published As

Publication number Publication date
WO2005074449A3 (en) 2007-03-29
TW200530422A (en) 2005-09-16
TWI280987B (en) 2007-05-11
US7115993B2 (en) 2006-10-03
WO2005074449A2 (en) 2005-08-18
US20050167839A1 (en) 2005-08-04

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