TWI280987B - Structure comprising amorphous carbon film and method of forming thereof - Google Patents

Structure comprising amorphous carbon film and method of forming thereof Download PDF

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Publication number
TWI280987B
TWI280987B TW094102320A TW94102320A TWI280987B TW I280987 B TWI280987 B TW I280987B TW 094102320 A TW094102320 A TW 094102320A TW 94102320 A TW94102320 A TW 94102320A TW I280987 B TWI280987 B TW I280987B
Authority
TW
Taiwan
Prior art keywords
layer
pattern
amorphous carbon
forming
metal
Prior art date
Application number
TW094102320A
Other languages
English (en)
Chinese (zh)
Other versions
TW200530422A (en
Inventor
Eric M Lee
Dorel I Toma
David C Wang
Jeffrey T Wetzel
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200530422A publication Critical patent/TW200530422A/zh
Application granted granted Critical
Publication of TWI280987B publication Critical patent/TWI280987B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/086—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving buried masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Carbon And Carbon Compounds (AREA)
TW094102320A 2004-01-30 2005-01-26 Structure comprising amorphous carbon film and method of forming thereof TWI280987B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/766,872 US7115993B2 (en) 2004-01-30 2004-01-30 Structure comprising amorphous carbon film and method of forming thereof

Publications (2)

Publication Number Publication Date
TW200530422A TW200530422A (en) 2005-09-16
TWI280987B true TWI280987B (en) 2007-05-11

Family

ID=34807608

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094102320A TWI280987B (en) 2004-01-30 2005-01-26 Structure comprising amorphous carbon film and method of forming thereof

Country Status (4)

Country Link
US (1) US7115993B2 (enExample)
JP (1) JP2007523034A (enExample)
TW (1) TWI280987B (enExample)
WO (1) WO2005074449A2 (enExample)

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US7291553B2 (en) * 2005-03-08 2007-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming dual damascene with improved etch profiles
US7422775B2 (en) 2005-05-17 2008-09-09 Applied Materials, Inc. Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing
US7312162B2 (en) 2005-05-17 2007-12-25 Applied Materials, Inc. Low temperature plasma deposition process for carbon layer deposition
US7857982B2 (en) * 2005-07-19 2010-12-28 Micron Technology, Inc. Methods of etching features into substrates
US7335611B2 (en) 2005-08-08 2008-02-26 Applied Materials, Inc. Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer
US7312148B2 (en) 2005-08-08 2007-12-25 Applied Materials, Inc. Copper barrier reflow process employing high speed optical annealing
US7429532B2 (en) 2005-08-08 2008-09-30 Applied Materials, Inc. Semiconductor substrate process using an optically writable carbon-containing mask
US7323401B2 (en) * 2005-08-08 2008-01-29 Applied Materials, Inc. Semiconductor substrate process using a low temperature deposited carbon-containing hard mask
US7422975B2 (en) * 2005-08-18 2008-09-09 Sony Corporation Composite inter-level dielectric structure for an integrated circuit
JP4543392B2 (ja) * 2005-11-01 2010-09-15 エルピーダメモリ株式会社 半導体装置の製造方法
US7602068B2 (en) 2006-01-19 2009-10-13 International Machines Corporation Dual-damascene process to fabricate thick wire structure
US7563688B2 (en) * 2006-02-24 2009-07-21 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US20070243714A1 (en) * 2006-04-18 2007-10-18 Applied Materials, Inc. Method of controlling silicon-containing polymer build up during etching by using a periodic cleaning step
US7867578B2 (en) * 2006-06-28 2011-01-11 Applied Materials, Inc. Method for depositing an amorphous carbon film with improved density and step coverage
US8129282B2 (en) 2006-07-19 2012-03-06 Tokyo Electron Limited Plasma etching method and computer-readable storage medium
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US7858514B2 (en) 2007-06-29 2010-12-28 Qimonda Ag Integrated circuit, intermediate structure and a method of fabricating a semiconductor structure
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US8084862B2 (en) * 2007-09-20 2011-12-27 International Business Machines Corporation Interconnect structures with patternable low-k dielectrics and method of fabricating same
US7709370B2 (en) * 2007-09-20 2010-05-04 International Business Machines Corporation Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures
US8618663B2 (en) * 2007-09-20 2013-12-31 International Business Machines Corporation Patternable dielectric film structure with improved lithography and method of fabricating same
US8298931B2 (en) * 2007-09-28 2012-10-30 Sandisk 3D Llc Dual damascene with amorphous carbon for 3D deep via/trench application
US9136463B2 (en) * 2007-11-20 2015-09-15 Qualcomm Incorporated Method of forming a magnetic tunnel junction structure
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US9859127B1 (en) * 2016-06-10 2018-01-02 Lam Research Corporation Line edge roughness improvement with photon-assisted plasma process
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JP7717721B2 (ja) * 2020-04-17 2025-08-04 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング 炭素材料、金属有機化合物および溶媒を含んでなるスピンコーティング組成物、および基板の上方への金属酸化物膜の製造方法
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Also Published As

Publication number Publication date
WO2005074449A3 (en) 2007-03-29
TW200530422A (en) 2005-09-16
JP2007523034A (ja) 2007-08-16
US7115993B2 (en) 2006-10-03
WO2005074449A2 (en) 2005-08-18
US20050167839A1 (en) 2005-08-04

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