US20080124912A1 - Semiconductor methods - Google Patents
Semiconductor methods Download PDFInfo
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- US20080124912A1 US20080124912A1 US11/461,673 US46167306A US2008124912A1 US 20080124912 A1 US20080124912 A1 US 20080124912A1 US 46167306 A US46167306 A US 46167306A US 2008124912 A1 US2008124912 A1 US 2008124912A1
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- 238000000034 method Methods 0.000 title claims abstract description 368
- 239000004065 semiconductor Substances 0.000 title description 43
- 239000000463 material Substances 0.000 claims abstract description 226
- 239000000758 substrate Substances 0.000 claims abstract description 87
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 47
- 239000001301 oxygen Substances 0.000 claims abstract description 47
- 125000006850 spacer group Chemical group 0.000 claims description 91
- 238000000231 atomic layer deposition Methods 0.000 claims description 44
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 36
- 238000005229 chemical vapour deposition Methods 0.000 claims description 36
- 238000005240 physical vapour deposition Methods 0.000 claims description 32
- 229910052739 hydrogen Inorganic materials 0.000 claims description 13
- 239000001257 hydrogen Substances 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000003989 dielectric material Substances 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 3
- 239000010410 layer Substances 0.000 description 708
- 229920002120 photoresistant polymer Polymers 0.000 description 42
- 238000005516 engineering process Methods 0.000 description 30
- 239000012212 insulator Substances 0.000 description 30
- 239000003990 capacitor Substances 0.000 description 27
- 150000004767 nitrides Chemical class 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 24
- 238000000151 deposition Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 12
- 239000000126 substance Substances 0.000 description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 150000002431 hydrogen Chemical class 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 238000007747 plating Methods 0.000 description 7
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000007667 floating Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 238000005401 electroluminescence Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 244000208734 Pisonia aculeata Species 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 238000000149 argon plasma sintering Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Definitions
- the present invention relates to semiconductor methods, and more particularly to semiconductor methods related to amorphous carbon layers.
- CPUs central processing units
- LCDs liquid crystal displays
- LEDs light emitting diodes
- laser diodes other devices or chip sets.
- CPUs central processing units
- LCDs liquid crystal displays
- LEDs light emitting diodes
- laser diodes other devices or chip sets.
- materials such as amorphous carbon, have been proposed along with techniques for overcoming manufacturing obstacles associated with these materials.
- Amorphous carbon is a new material used in semiconductor technology.
- An amorphous carbon layer can be formed substantially conformally over a semiconductor structure over a substrate by a chemical vapor deposition (CVD) process.
- the amorphous carbon layer has a desired thermal stability even between about 400° C. and about 550° C.
- the amorphous carbon layer will not crack in this temperature range. (The temperature range would result in cracking of organic material, such as photoresist.)
- the amorphous carbon layer can be removed by an oxygen plasma that is used to remove a photoresist layer as well.
- an amorphous carbon layer can serve as a hard mask and/or anti-reflection coating (ARC) layer under a photoresist layer to form a via/contact plug in nanometer level semiconductor technology.
- ARC anti-reflection coating
- FIGS. 1A-1C are schematic cross-sectional views illustrating a process for formation of a via/contact plug.
- an oxide layer 110 , an amorphous carbon layer 120 , an oxynitride layer 130 and photoresist layer 135 are sequentially formed over a substrate 100 .
- the photoresist layer 135 includes an opening 137 therein for forming a via/contact hole in FIG. 1B .
- a portion of the amorphous carbon layer 120 and a portion of the oxynitride layer 130 are removed by an etch process to form an opening 140 within the amorphous carbon layer 120 a as shown in FIG. 1B .
- the photoresist layer 135 is then removed by a photoresist removal process.
- the removal of the photoresist layer 135 and the partial removals of the amorphous carbon layer and oxynitride layer for forming the opening 140 are performed by the same etch process.
- the oxynitride layer 130 a and the amorphous carbon layer 120 a are removed.
- the amorphous carbon layer 120 a can be removed by oxygen plasma.
- a metal layer 150 is then formed within the opening 140 .
- a method includes the steps of: (a) forming a conductive layer within a dielectric layer formed over a substrate; (b) forming a material layer over the conductive layer and the dielectric layer; (c) forming an opening within the material layer by an etch process to expose a portion of the dielectric layer and a top surface of the conductive layer; (d) forming a first metal-containing layer within the opening substantially covering sidewalls of the material layer and the exposed portion of the second dielectric layer; and (e) removing the material layer by an oxygen-containing plasma process to expose a portion of outer sidewalls of the first metal-containing layer.
- FIGS. 1A-1C are schematic cross-sectional views illustrating a process for formation of a via/contact plug.
- FIGS. 2A-2E are schematic cross-sectional views illustrating a process for formation of a shallow trench isolation (STI) structure.
- STI shallow trench isolation
- FIG. 3A is a schematic top view of a crown metal capacitor.
- FIGS. 3B-3G are schematic cross-sectional views illustrating a process for formation of the crown metal capacitor of FIG. 3A .
- FIGS. 4A-4E are schematic cross-sectional views illustrating a process for formation of a select gate of a flash transistor.
- FIGS. 5A-5D are schematic cross-sectional views illustrating a process for formation of a source/drain region of a transistor.
- FIGS. 6A-6E are schematic cross-sectional views illustrating a process for formation of air gaps over a pixel.
- FIGS. 7A-7E are schematic cross-sectional views illustrating a process for formation of air gaps next to a conductive layer.
- FIGS. 8A-8F are schematic cross-sectional views illustrating a process for formation of a self-aligned contact plug.
- FIGS. 9A-9E are schematic cross-sectional views illustrating a process for formation of a via/contact plug or a conductive line.
- FIGS. 2A-2E are schematic cross-sectional views illustrating a process for formation of a shallow trench isolation (STI) structure.
- STI shallow trench isolation
- a dielectric layer 210 including an opening 220 therein is formed over a substrate 200 .
- the opening 220 exposes a portion of a top surface 200 a of the substrate 200 .
- the substrate 200 can be a semiconductor substrate, display substrate such as a liquid crystal display (LCD), plasma display, cathode ray tube display or electro luminescence (EL) lamp display, or light emitting diode (LED) substrate (collectively referred to as, substrate 200 ), for example.
- the dielectric layer 210 can be, for example, an oxide layer, nitride layer, oxynitride layer or other dielectric layer that is adapted to be a hard mask layer.
- the dielectric layer 210 can be formed, for example, by a chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, spin-on method or other method that is adapted to form a dielectric material over the substrate 200 .
- the dielectric layer 210 can be a silicon nitride layer, for example.
- the dielectric layer 210 from the top surface 200 a of the substrate 200 to the top surface of the dielectric layer 210 has a thickness of about 800 ⁇ to about 1,200 ⁇ .
- the opening 220 between the sidewalls of the dielectric layer 210 has a width of about 800 ⁇ to about 1,500 ⁇ .
- a substantially conformal material 230 is formed over the dielectric layer 210 and the opening 220 .
- the material layer 230 can be removed by an oxygen-containing plasma process.
- the material layer 230 can be, for example, an amorphous carbon layer.
- the material layer 230 has a thickness of about 150 ⁇ to about 250 ⁇ from the top surface of the dielectric layer 210 to the top surface of the material layer 230 .
- a material layer 230 can be formed by a low deposition rate process to obtain a substantially conformal layer over the dielectric layer 210 and the opening 220 .
- An exemplary low deposition rate process includes: a flow of C 3 H 6 between about 1,000 standard cubic centimeters per minute (sccm) and about 1,500 sccm; a flow of He between about 400 sccm and about 500 sccm; a radio-frequency (RF) power between about 800 watts and about 1,200 watts; and a pressure between about 3.5 Torr and about 4.5 Torr.
- the material layer 230 can be formed by a high deposition rate process as long as the conformity of the material layer 230 is desired.
- An exemplary high deposition rate process includes: a flow of C 3 H 6 between about 1,500 standard cubic centimeters per minute (sccm) and about 2,500 sccm; a flow of He between about 500 sccm and about 900 sccm; a radio-frequency (RF) power between about 1,200 watts and about 1,800 watts; and a pressure between about 4.5 Torr and about 5.5 Torr.
- a portion of the material layer 230 is removed by an etch process to form material spacers 230 a on sidewalls of the dielectric layer 210 .
- the material spacers 230 a are not substantially laterally etched by the etch process, so that a desired profile of the material spacers 230 a is achieved.
- the etch process may include: a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 flow of hydrogen
- N 2 nitrogen
- RF radio-frequency
- a trench 240 is formed within the substrate 200 by using the first dielectric layer 210 and the material spacers 230 a as a hard mask.
- the trench 240 can be formed, for example, by an etch process that has a desired etch selectivity for the material of the substrate, such as silicon, to the first dielectric layer 210 , such as silicon nitride, and the material spacers 230 a , such as amorphous carbon, so that the etch process does not substantially laterally etch the material spacers 230 a .
- the trench 240 has a depth of about 2,800 ⁇ to about 3,800 ⁇ .
- the material spacers 230 a are removed by an oxygen-containing plasma process.
- the opening is increased by a pull-back distance “d” from the sidewall of the dielectric layer 210 to the top edge of the trench 240 .
- d a pull-back distance
- the oxygen-containing plasma process removes the material spacers 230 a .
- the material spacers 230 a can be removed by an ash process that has a high etch rate, if the ash process does not substantially damage the profile of the trench 240 .
- the ash process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- the etch process for the formation of the material spacers 230 a as shown in FIG. 2B can be used to remove the material spacers 230 a , if the desired removal rate of the material spacers 230 a can be achieved and the profile of the trench 240 is not substantially damaged.
- the oxygen-containing plasma process for the removal of the material spacers 230 a can be used for the formation of the material spacers 230 a , if the desired profile of the material spacers 230 a can be formed.
- One of ordinary skill in the art can readily use the etch process and oxygen-containing plasma process to obtain a desired profile of the material spacers 230 a and/or to remove the material spacers 230 a.
- a dielectric layer 250 is filled within the trench 240 .
- the steps of forming of the dielectric layer 250 within the trench include: forming a dielectric material layer 250 within the trench 240 ; and removing the dielectric layer 210 and a portion of the dielectric material layer 250 over the top surface of the substrate 200 .
- the dielectric layer 250 can be, for example, a high density plasma (HDP) dielectric layer or other dielectric layer that can isolate two active regions of the substrate 200 .
- the HDP dielectric layer can be formed, for example, by a HDP CVD.
- the dielectric layer 210 and the portion of the dielectric material layer over the top surface of the substrate 200 can be removed, for example, by an etch-back process or chemical mechanical polishing (CMF) process.
- CMF chemical mechanical polishing
- the pull-back distance “d” allows the dielectric material layer 250 be properly filled within the trench 240 and the opening between the dielectric layers 210 . Accordingly, a desired STI structure is formed.
- the dimensions of the dielectric layers, material layer and trench set forth above are illustrated by 90-nm or 65-nm semiconductor technology.
- the present invention is not limited thereto.
- One of ordinary skill in the art can understand that these physical characteristics vary with the applied semiconductor process and readily form a desired STI structure.
- FIG. 3A is a schematic top view of a crown metal capacitor.
- FIGS. 3B-3G are schematic cross-sectional views illustrating a process for formation of the crown metal capacitor of FIG. 3A .
- the metal-insulator-metal (MIM) capacitor 395 can have, for example, a circle shape, oval shape, square shape, or rectangular shape.
- an oval shape MIM capacitor 395 includes a long-axis “a” of about 0.15 Jim to about 0.25 ⁇ m and a short-axis “b” of about 0.07 ⁇ m to about 0.15 ⁇ m.
- dielectric layers 310 and 320 are sequentially formed over a substrate 300 .
- a conductive layer 330 is formed within the dielectric layers 310 and 320 .
- the substrate 300 is similar to the substrate 200 as set forth above.
- the substrate 300 can include at least one transistor or device (now shown) thereon in contact with the conductive layer 330 .
- the dielectric layer 310 can be, for example, an oxide layer, low-k dielectric layer or other dielectric layer that can isolate two conductive structures, such as metal lines or via/contact plugs.
- the dielectric layer 310 can be formed, for example, by a CVD process, PVD process, spin-on process or other method that can form a dielectric layer over the substrate 300 .
- the dielectric layer 320 can be, for example, a nitride layer, oxynitride layer or other material layer that can protect the dielectric layer 310 from exposure to a subsequent dry or wet etch process or photolithographic process.
- the dielectric layer 320 can be formed, for example, by a CVD process, PVD process, spin-on process or other method that can form a dielectric layer over the substrate 300 .
- the dielectric layer 310 is an oxide layer and the dielectric layer 320 is an oxynitride layer, for example.
- the dielectric layer 320 has a thickness of about 200 ⁇ to about 300 ⁇ .
- the conductive layer 330 is formed within the dielectric layers 310 and 320 to electrically connect a transistor or device (not shown) over the substrate 300 and a bottom electrode of a capacitor, i.e., the metal-containing layer 370 a (shown in FIG. 3F ).
- the conductive layer 330 can be, for example, a tungsten plug, aluminum/copper plug, copper plug or other conductive layer that can connect a transistor and a bottom electrode of a capacitor.
- the conductive layer 330 can be formed, for example, by CVD, PVD, chemical electrical plating, chemical electroless plating method or other method that can form the conductive layer 330 .
- an etch-back or CMP process is applied to remove the material of the conductive layer 330 , which is formed over the top surface of the dielectric layer 320 by a CVD method or PVD method.
- the etch-back or CMP process is not used, if the conductive layer 330 is formed beginning from the top surface of the substrate 300 and stopping at the region proximate to the top surface of the dielectric layer 320 by a chemical electrical plating method or chemical electroless plating method.
- a material layer 340 is formed over the conductive layer 330 and the dielectric layer 320 .
- the material layer 340 can be removed by an oxygen-containing plasma process.
- the material layer 340 can be, for example, an amorphous carbon layer.
- the material layer 340 has a thickness of about 2,500 ⁇ to about 6,000 ⁇ .
- the material layer 340 can be formed by a high deposition rate process to obtain a material layer over the dielectric layer 320 and the conductive layer 330 .
- a high deposition rate process can reduce the processing time for the formation of the MIM capacitor.
- the high deposition rate process includes: a flow of C 3 H 6 between about 1,500 standard cubic centimeters per minute (sccm) and about 2,500 sccm; a flow of He between about 500 sccm and about 900 sccm; a radio-frequency (RF) power between about 1,200 watts and about 1,800 watts; and a pressure between about 4.5 Torr and about 5.5 Torr.
- sccm standard cubic centimeters per minute
- RF radio-frequency
- the material layer 340 can be formed by a low deposition rate process as long as the deposition rate of the material layer 340 is desired.
- the low deposition rate process includes: a flow of C 3 H 6 between about 1,000 standard cubic centimeters per minute (sccm) and about 1,500 sccm; a flow of He between about 400 sccm and about 500 sccm; a radio-frequency (RF) power between about 800 watts and about 1,200 watts; and a pressure between about 3.5 Torr and about 4.5 Torr.
- a dielectric layer 350 is formed over the material layer 340 .
- the dielectric layer 350 can be, for example, a nitride layer, oxynitride layer or other material layer that is adapted to be a hard mask for an etch process or CMP process.
- the dielectric layer 350 can be an oxynitride layer, for example, and has a thickness of about 600 ⁇ to about 1,000 ⁇ .
- a photoresist layer 355 including an opening 357 therein is formed over the dielectric layer 350 .
- the opening 357 exposes a portion of the top surface of the dielectric layer 350 .
- the opening 357 can be defined by a photolithographic process.
- the opening 357 defines dimensions of the metal capacitor 395 .
- the dielectric layer 350 protects the material layer 340 from being removed if the process for removing the photoresist layer 355 also substantially removes the material layer 340 .
- an opening 360 is formed within the material layer 340 and the dielectric layer 350 to expose a portion of the top surface of the dielectric layer 320 and a top surface of the conductive layer 330 .
- the opening 360 is defined based on the opening 357 shown in FIG. 3B .
- the steps for forming opening 360 include, for example, removing a portion of the dielectric layer 350 and a portion of the material layer 340 .
- the process for removing the portion of the dielectric layer 350 for example, can have a desired etch selectivity for the dielectric layer 350 to the material layer 340 .
- the etch process for removing the portion of the material layer 340 for example, can have a desired etch selectivity for the material layer 340 to the dielectric layers 320 and/or 350 , e.g., oxynitride layer.
- the etch process has a desired selectivity for the material layer 340 to the dielectric layers 320 and/or 350 so that the etch process does not substantially damage the dielectric layers 320 and/or 350 .
- the remaining material 340 a are not substantially laterally etched by the etch process, so that a desired profile of the opening 360 is achieved.
- the etch process includes a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process includes a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 oxygen
- RF radio-frequency
- the photoresist layer 355 is removed.
- the removal process of the photoresist layer 355 can be, for example, a traditional photoresist removal process.
- the photoresist layer 355 is removed while the dielectric layer 350 and material layer 340 are partially removed. In other words, the opening 360 is formed within the dielectric layer 350 a and remaining material layer 340 a while the photoresist layer 355 is substantially removed.
- a substantially conformal metal-containing layer 370 is formed over the dielectric layer 350 and the opening 360 .
- a photoresist layer 375 is then formed over the metal-containing layer 370 and within the opening 360 .
- the metal-containing layer 370 can be, for example, a titanium nitride (TiN) layer or other metal-containing layer that can be a bottom electrode of a metal-insulator-metal (MIM) capacitor.
- the metal-containing layer 370 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the metal-containing layer 370 .
- the metal-containing layer 370 has a thickness of about 150 ⁇ to about 300 ⁇ .
- the photoresist layer 375 can be formed, for example, by a traditional photolithographic process.
- a top portion of the photoresist layer 375 , a portion of the metal-containing layer 370 and the dielectric layer 350 a are removed.
- the photoresist layer 375 within the opening 360 is then removed.
- the top portion of the photoresist layer 375 , the portion of the metal-containing layer 370 and the dielectric layer 350 a can be removed by a sequence of etch processes.
- the top portion of the photoresist layer 375 , the portion of the metal-containing layer 370 and the dielectric layer 350 can be removed by a CMP process.
- the remaining photoresist layer 375 within the opening 360 is removed by a photoresist removal process, which may be a traditional process, for example.
- a photoresist removal process which may be a traditional process, for example.
- the metal-containing layer 370 a is formed within the opening 360 , substantially covering sidewalls of the material layer 340 and the portion of the top surface of the dielectric layer 320 thereunder.
- the material layer 340 a is removed by an oxygen-containing plasma process to expose a portion of outer sidewalls 370 b of the metal-containing layer 370 a .
- the dielectric layer 320 can be an etch-stop layer to protect the dielectric layer 310 from being damaged.
- the plasma process has a desired etch selectivity for the material layer 340 a to the dielectric layer 320 so that the plasma process can remove the material layer 340 a without substantially damaging the dielectric layer 320 .
- the plasma process does not substantially damage the metal-containing layer 370 a , i.e., the bottom electrode of the capacitor 395 (shown in FIG. 3A ).
- the ash process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 flow of oxygen
- sccm standard cubic centimeters per minute
- RF radio-frequency
- the surface area of the capacitor 395 is thus increased.
- the capacitance of the capacitor 395 is also enhanced.
- a portion of the material layer 340 a remains on the outer sidewalls 370 b of the metal-containing layer 370 a , if the remaining material layer 340 a does not adversely affect electrical performance of the transistor (not shown) over the substrate 300 and the capacitor 395 , and/or subsequent process, such as wafer contamination or film cracking when the material layer 340 a is subjected to thermal treatments. Also, the remaining portion of the material layer 340 a reduces the area of the outer sidewalls 370 b of the metal-containing layer 370 a . The area and capacitance of the capacitor 395 are thus reduced.
- FIG. 3G is a schematic cross-sectional view of the capacitor 395 shown in FIG. 3A taken along section line 3 G- 3 G.
- a capacitor insulator 380 and a metal-containing layer 370 i.e., a top electrode of the capacitor 395 , are formed over the metal-containing layer 370 a , i.e., the bottom electrode of the capacitor 395 , and the dielectric layer 320 .
- the capacitor insulator 380 substantially covers the exposed outer sidewalls 370 b , top regions and inner sidewalls of the metal-containing layer 370 .
- the metal-containing layer 390 substantially covers the capacitor insulator layer 380 .
- the capacitor insulator 380 can be, for example, an aluminum oxide layer, tantalum oxide layer, zinc oxide layer or other material layer that has a high dielectric constant and is adapted for the MIM capacitor 395 .
- the capacitor insulator 380 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the capacitor insulator 380 .
- the metal-containing layer 390 can be, for example, a TiN layer which can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a metal top electrode.
- dielectric layers, material layer and metal-containing layers set forth above are illustrated for examples using 90-nm or 65-nm semiconductor technology.
- the present invention is not limited thereto.
- One of ordinary skill in the art can understand that these physical characteristics vary with the applied semiconductor process and can readily form a desired MIM capacitor.
- FIGS. 4A-4E are schematic cross-sectional views illustrating a process for formation of a select gate of a flash transistor.
- a pair of flash transistor gates 410 are formed over a substrate 400 .
- the substrate 400 may be similar to the substrate 200 described above.
- the flash transistor gate 410 includes a gate insulator 411 , a floating gate 413 , an inter-gate insulator 415 , a coupling gate 417 , a cap layer 419 and spacers 412 .
- the gate insulator 411 can be, for example, an oxide layer, nitride layer, oxynitride layer or other insulator layer.
- the gate insulator 411 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the insulator 411 .
- the floating gate 413 can be, for example, a polysilicon layer which can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the floating gate 413 .
- the inter-gate insulator 415 can be, for example, an oxide layer, nitride layer, oxynitride layer, nitride/ oxide (NO) layer, oxide/nitride/oxide (ONO) layer or other insulator layer.
- the inter-gate insulator 415 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the inter-gate insulator layer 415 .
- the coupling gate 417 can be, for example, a polysilicon layer which can be formed, for example, by a CVD process, r-VD process, atomic layer deposition (ALD) process or other process that can form the coupling gate 417 .
- the cap layer 419 and the spacers 412 can be, for example, an oxide layer, nitride layer, oxynitride layer or other insulator layer.
- the cap layer 419 and the spacers 412 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the cap layer 419 and the spacers 412 .
- the gate insulator 411 such as an oxide layer, has a thickness of about 90 ⁇ to about 150 ⁇ ;
- the floating gate 413 such as a polysilicon layer, has a thickness of about 500 ⁇ to about 800 ⁇ ;
- the inter-gate insulator 415 such as an ONO layer, has a thickness of about 35/35/45 ⁇ to about 65/65/85 ⁇ , respectively;
- the coupling gate 417 such as a polysilicon layer, has a thickness of about 500 ⁇ to about 1,000 ⁇ ;
- the cap layer 419 such as an oxide layer, has the a thickness of about 700 ⁇ to about 1,200 ⁇ ;
- the thickest portion of the spacer 412 such as a nitride spacer, has a width of about 200 ⁇ to about 500 ⁇ ;
- the gap 405 between the sidewalls of the floating gates 413 has a width of about 1,000 ⁇ to about 2,000 ⁇ .
- a sacrificial layer 420 is formed, covering the flash transistor gates 410 and filling within the gap 405 between the flash transistor gates 410 .
- the sacrificial layer 420 can be, for example, a material layer that can be removed by an oxygen-containing plasma process, or a dielectric layer, such as an oxide layer or nitride layer.
- the material layer comprises an amorphous carbon layer.
- the sacrificial layer 420 has a thickness of about 2,000 ⁇ to about 3,000 ⁇ .
- the sacrificial layer 420 is an amorphous carbon layer.
- the sacrificial layer 420 is similar to the material layer 340 described above. Detailed descriptions are not repeated.
- the sacrificial layer 420 a includes a top surface, lower than or substantially equal to a top region of the flash transistor gate 410 , such as the top surface 410 a of the flash transistor gate 410 .
- the sacrificial layer 420 a Due to the large thickness of the sacrificial layer 420 between the flash transistor gates 410 and/or the aspect ratio, i.e., depth/width, of the gap 405 , the sacrificial layer 420 a remains within the gap 405 between the flash transistor gates 410 , when the sacrificial layer 420 outside of the gap 405 between the flash transistor gates 410 is completely removed.
- the highest portion of the sacrificial layer 420 a has a dimension of about 1,000 ⁇ to about 2,500 ⁇ .
- the sacrificial layer 420 can be removed by an etch process that has a desired etch rate, if the etch process does not substantially damage the substrate 400 .
- the etch process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- the etch process has a desired selectivity of about 80:1 to about 120:1 for the sacrificial layer 420 , such as an amorphous carbon layer, to the spacers 412 , such as nitride spacers.
- the etch process includes a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- sccm standard cubic centimeters per minute
- N 2 nitrogen
- RF radio-frequency
- a conductive layer 430 is formed, covering the flash transistor gates 410 , the sacrificial layer 420 a and the substrate 400 .
- the conductive layer 430 can be, for example, a polysilicon layer, aluminum layer, copper layer, aluminum/copper layer or other conductive material layer.
- the conductive layer 430 can be formed, for example, by a CVD process, PVD process, chemical plating process or other process that can form the conductive layer 430 .
- the conductive layer 430 such as a polysilicon layer, has a thickness of about 1,500 ⁇ to about 2,000 ⁇ from the top surface 410 a of the flash gate transistor 410 to the top surface of the conductive layer 430 .
- a photoresist layer 435 including an opening 437 therein is formed over the conductive layer 430 .
- the photoresist layer 435 including the opening 437 therein can be formed by a photolithographic process.
- a portion of the conductive layer 430 is removed by an etch process to expose the top surface of the sacrificial layer 420 a .
- the remaining conductive layer 430 a is the select gate of the flash transistor.
- the etch process has a desired etch selectivity for the conductive layer 430 to the top surface 410 a of the flash transistor gate 410 , e.g., the cap layer 419 , so that the etch process does not substantially damage the flash transistor gate 410 , e.g., the coupling gate 417 .
- the photoresist layer 435 is then removed by a photoresist removal process.
- the sacrificial layer 420 a within the gap 405 between the flash transistor gates 410 is removed by an oxygen-containing plasma process.
- the sacrificial layer 420 a can be removed by an oxygen-containing plasma process that has a desired etch rate, if the plasma process does not substantially damage the exposed surface of the substrate 400 , the conductive layer 430 a and/or the flash transistor gates 410 as shown in FIG. 4E .
- the plasma process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- the photoresist layer 435 and sacrificial layer 420 a are removed by the same etch process. For these embodiments, at least one removal process, either the removal process of the sacrificial layer 420 a or the removal process of the photoresist layer 435 , can be omitted.
- a conductive layer is completely filled within the gap 405 .
- the conductive layer in the gap 405 from the top surface of the substrate 400 to the top surface of the conductive layer must be removed. Due to the large height of the conductive layer within the gap 405 , an over-etch, such as a polysilicon over-etch, is used to remove the conductive layer within the gap 405 .
- the over-etch may damage the exposed substrate or transistor gates.
- the conductive layer 430 within the gap 405 can be properly and completely removed without an undesired over-etch. After the removal of the conductive layer 430 within the gap 405 , the sacrificial layer 420 a is exposed. The sacrificial layer 420 can be properly removed by the etch process, such as the oxygen-containing plasma process. Accordingly, the window to form the conductive layer 430 a , i.e., the select gate of the flash transistor, is increased.
- dielectric layers, material layer and conductive layers set forth above are illustrated for examples using 90-nm or 65-nm semiconductor technology.
- the present invention is not limited thereto.
- One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired flash transistor.
- FIGS. 5A-5D are schematic cross-sectional views illustrating a process for formation of a source/drain region of a transistor.
- a transistor gate 510 is formed over a substrate 500 .
- the transistor gate 510 includes a conductive layer 511 and a gate insulator 513 .
- a dielectric layer 515 is formed over the transistor gate 510 and the substrate 500 .
- a substantially conformal material layer 520 is formed over the dielectric layer 515 .
- the substrate 500 may be similar to the substrate 200 as set forth above.
- the conductive layer 511 can be, for example, a polysilicon layer, amorphous silicon layer, silicon/silicon germanium (SiGe), a metal-containing layer, such as a TiN layer, or other conductive layer that can be a gate of a transistor.
- the conductive layer 511 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate of a transistor. In some embodiments, the process is applied in 90-nm or 65-nm semiconductor technology. In some embodiments, the conductive layer 511 has a thickness of about 1,200 ⁇ to about 1,700 ⁇ .
- the gate insulator 513 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can insulate the conductive layer 511 from the substrate 500 .
- the gate insulator 513 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate insulator of a transistor.
- the conductive layer 511 such as a polysilicon layer
- the gate insulator 513 such as an oxide layer, has a thickness of about 20 ⁇ to about 40 ⁇ .
- the dielectric layer 515 can be, for example, an oxide layer, nitride layer, oxynitride layer or other dielectric layer that has an etch selectivity different from that of the material layer 520 and that of the substrate 500 .
- the dielectric layer 515 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the dielectric layer 515 .
- the dielectric layer 515 such as a nitride layer, has a thickness of about 250 ⁇ to about 350 ⁇ .
- the material layer 520 is similar to the material layer 230 as set forth above.
- a portion of the material layer 520 is removed by an etch process to form material spacers 520 a on sidewalls of the transistor gate 510 and to expose a top region of the dielectric layer 515 and the other regions not covered by the material spacers 520 a .
- the material spacers 520 are not substantially laterally etched by the etch process to obtain a desired profile thereof.
- the desired profile of the spacers 520 a is used to define source/drain regions 530 at desired locations as shown in FIG. 5D .
- the desired locations of the source/drain regions 530 can prevent or reduce short-channel effect and/or punch-through effect between the source/drain regions 530 .
- the etch process has a desired etch selectivity for the material layer 520 , such as an amorphous carbon, to the dielectric layer 515 , such as a nitride layer.
- the etch selectivity is of about 80:1 to about 120:1.
- the etch process may include a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process may include: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- a flow of oxygen O 2
- sccm standard cubic centimeters per minute
- RF radio-frequency
- a portion of the dielectric layer 515 and a portion of the material spacers 520 a are removed and the source/drain regions 530 are formed within the substrate 500 adjacent to the transistor gate 510 .
- the remaining dielectric layer 515 a has an L-shape structure.
- the portion of the dielectric layer 515 and portion of the material spacers 520 a can be removed by a dry etch process that has substantially equal, or higher, etch selectivity for the dielectric layer 515 to the material spacers 520 a .
- the process to remove the dielectric layer 515 does not substantially damage the substrate 500 so as to cause undesired current leakage at the source/drain regions 530 .
- the source/drain regions 530 can be formed by an ion implantation process.
- the material spacers 520 a are used as a hard mask to prevent ions implanted substantially into the substrate 500 under the transistor gate 510 and the material spacers 520 a .
- the source/drain regions 530 can be N or P type source/drain regions.
- the material spacers 520 a are removed by an oxygen-containing plasma process.
- the material spacers 520 a can be removed by an ash process that has a desired etch rate for the material spacers 520 a , if the ash process does not substantially damage the substrate 500 , the conductive layers 511 and/or the source/ drain regions 530 .
- the plasma process includes: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. Accordingly, the plasma process will not substantially damage the substrate 500 , the conductive layers 511 and/or the source/ drain regions 530 .
- a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm
- RF radio-frequency
- lightly-doped drain (LDD) regions are formed within the substrate 500 under the L-shaped dielectric layers 515 .
- the LDD regions can be formed by an ion implantation process, for example.
- dielectric layers, material layer and conductive layer set forth above are illustrated for examples using 90-nm or 65-nm semiconductor technology.
- the present invention is not limited thereto.
- One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired source/drain structure.
- FIGS. 6A-6E are schematic cross-sectional views illustrating a process for formation of air gaps over a pixel.
- a pixel 610 is formed within a dielectric layer 615 over a substrate 600 .
- the substrate 600 may be similar to the substrate 200 .
- the substrate 600 include at least one transistor, device or circuit (not shown) coupled to the pixel 610 .
- the pixel 610 can be, for example, a CMOS image sensor (CIS), charge coupled device (CCD), liquid crystal display (LCD) pixel, plasma display pixel, electro luminescence (EL) lamp display pixel, or light emitting diode (LED) pixel (collectively referred to as, pixel 610 ).
- CIS CMOS image sensor
- CCD charge coupled device
- LCD liquid crystal display
- EL electro luminescence
- LED light emitting diode
- the dielectric layer 615 can be, for example, an oxide layer, nitride layer, oxynitride layer or other dielectric layer that can isolate two pixels 610 .
- the dielectric layer 615 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the dielectric layer 615 .
- a dielectric layer 620 having an opening 625 is formed over the pixel 610 and the dielectric layer 615 .
- the opening 625 exposes a substantial top surface of the pixel 610 .
- the dielectric layer 615 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer.
- the opening 625 has a width of about 2.5 ⁇ m to about 3.5 ⁇ m; and the dielectric layer 615 , such as an oxide layer, has a thickness from 2.8 ⁇ m to about 3.8 ⁇ m.
- a substantially conformal material layer 630 is formed over the dielectric layer 620 and the exposed top surface of the pixel 610 .
- the material layer 630 is similar to the material layer 230 as set forth above.
- the material layer 630 such as an amorphous carbon layer, has a thickness of about 1,000 ⁇ to about 1,500 ⁇ .
- a portion of the material layer 630 is removed by an etch process to form material spacers 630 a on sidewalls of the dielectric layer 615 .
- the etch process also removes a portion of the material layer 630 , which covers the pixel 610 to substantially expose the top surface of the pixel 610 .
- the material spacers 630 a are not substantially laterally etched by the etch process so as to obtain a desired profile thereof.
- the desired profile of the material layer 630 is then removed to obtain a desired width of gaps 650 as shown in FIG. 6D .
- the width of the gaps 650 is used to form desired air gaps 670 as shown in FIG. 6E .
- the air gaps 670 can effectively reduce or prevent light scattering resulting from lights emitted from neighboring pixels 610 .
- the etch process includes a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process may include: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- a flow of oxygen O 2
- sccm standard cubic centimeters per minute
- RF radio-frequency
- a dielectric layer 640 is substantially filled within the opening 625 shown in FIG. 6B .
- the dielectric layer 640 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer.
- the dielectric layer 640 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the dielectric layer 640 .
- a portion (not shown) of the dielectric layer 640 over the top surface of the dielectric layer 620 is removed, for example, by an etch-back process or CMP process.
- the dielectric layer 640 may be slightly recessed within the opening 625 or extrude over the top surface of the dielectric layer 620 , if the recess or the extrusion of the dielectric layer 640 does not adversely affect of illumination performance of the pixel 610 and/or the subsequent process to seal the gaps 650 shown in FIG. 6E .
- the material spacers 630 a are substantially removed by an oxygen-containing plasma process to form the gaps 650 between the dielectric layers 620 and 640 .
- the width of the gap 650 is substantially equal to the width of the material spacer 630 a , i.e., about 1,000 ⁇ to about 1,500 ⁇ .
- the material spacers 630 a can be removed by a plasma process that has a desired etch rate for the material spacers 630 a , if the plasma process does not substantially damage the dielectric layers 620 and 640 .
- the ash process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 flow of oxygen
- RF radio-frequency
- the oxygen-containing plasma process can substantially remove the material spacers 630 a within the gaps 650 without substantially damaging the dielectric layers 620 and 630 .
- the material spacers 630 a between the dielectric layers 620 and 640 are substantially completely removed to expose portions of the top surface of the pixel 610 and/or the dielectric layer 615 within the gaps 650 . In other embodiments, a portion of the material spacers 630 a remains within the gap 650 as long as a desired air gap 670 as shown in FIG. 6E can be obtained.
- a dielectric layer 660 is formed over the dielectric layers 620 and 640 to seal the gaps 650 (shown in FIG. 6D ) to form the air gaps 670 .
- the dielectric layer 660 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer.
- the dielectric layer 660 has poor deposition conformity so that the dielectric layer 660 can be formed thicker at the top and bottom regions of the gap 650 and thinner at the central region of the gaps 650 .
- the dielectric layer 660 such as a plasma enhanced (PE) oxide, has a thickness of about 2,000 ⁇ to about 3,000 ⁇ from the top surface of the dielectric layer 620 to the top surface of the dielectric layer 660 .
- the dielectric layer 660 is formed by a plasma enhanced chemical vapor deposition (PECVD) process to seal top regions of the gaps 650 to form the air gaps 670 . With the air gaps 670 , the scattering effect resulting from lights emitted from neighboring pixels 610 can be substantially reduced or prevented.
- PECVD plasma enhanced chemical vapor deposition
- dielectric layers and material layer set forth above are illustrated by embodiments using 0.18- ⁇ m semiconductor technology.
- the present invention is not limited thereto.
- One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired air gap structure over a pixel.
- FIGS. 7A-7E are schematic cross-sectional views illustrating a process for formation of air gaps next to a conductive layer.
- a conductive line 710 is formed over a substrate 700 .
- the substrate 700 may be similar to the substrate 200 .
- the substrate 700 includes transistors, devices or circuits (not shown) thereon coupled to the conductive line 710 .
- the conductive line 710 comprises a barrier layer 711 , a conductive layer 713 and a cap layer 715 .
- the barrier layer 711 and cap layer 715 can be, for example, a titanium (Ti) layer, titanium nitride (TiN) layer, Ti/TiN layer or a material layer that can protect the conductive layer 713 or enhance adhesion between the conductive line 710 and a dielectric layer (not shown) over the substrate 700 or a dielectric layer 750 over the conductive line 710 as shown in FIG. 7E .
- the barrier layer 711 and cap layer 715 can be formed, for example, by a CVD process, PVD process, chemical plating process or other process that can form the barrier layer 711 and the cap layer 715 .
- the conductive layer 713 can be, for example, an aluminum/copper layer, aluminum layer, copper layer or other metal-containing layer.
- the conductive layer 713 can be formed, for example, by a CVD process, PVD process, chemical plating process or other process that can form the metal-containing layer.
- each of the barrier layers 711 , such a TiN layer, and cap layer 715 , such as a TiN layer has a thickness of about 200 ⁇ to about 500 ⁇ ; and the conductive layer 713 , such as an aluminum copper layer, has a thickness of about 4,000 ⁇ to about 10,000 ⁇ .
- the thicknesses of the layers vary with layer level of the conductive line 710 . For example, if the conductive line 710 is formed within an inter-layer dielectric (ILD) layer, the conductive line 710 has a small thickness. If the conductive line 710 is formed as a top metal layer over the substrate, the conductive line 710 has a large thickness.
- ILD inter-layer dielectric
- a substantially conformal material layer 720 is formed over the conductive line 710 and the substrate 700 .
- the material layer 720 is similar to the material layer 230 as set forth above.
- the material layer 720 such as an amorphous carbon layer, has a thickness of about 250 ⁇ to about 450 ⁇ .
- a portion of the material layer 720 is removed by an etch process to form material spacers 720 a on sidewalls of the conductive line 710 and to expose a top region of the conductive line 710 , such as the top surface of the cap layer 715 , and the other regions of the substrate 700 not covered by the material spacers 720 a .
- the material spacers 720 a are not substantially laterally etched by the etch process so as to form a desired profile thereof.
- the material spacers 720 a is then removed to obtain a desired width of gaps 740 as shown in FIG. 7D .
- the width of the gaps 740 is used to form desired air gaps 760 as shown in FIG. 7E .
- the air gaps 760 can efficiently reduce the dielectric constant of the dielectric material between two neighboring conductive lines 710 .
- the etch process has an etch selectivity for the material layer 720 to a dielectric layer (not shown) over the substrate 700 and under the conductive line 710 .
- the etch process does not substantially damage the dielectric layer over the substrate 700 and the substrate 500 can be effectively protected by the dielectric layer.
- the etch process may include a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process may include: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- a flow of oxygen O 2
- sccm standard cubic centimeters per minute
- RF radio-frequency
- a dielectric layer 730 is formed adjacent to the sidewalls of the material spacers 730 to expose a top surface of the conductive line 710 and top surfaces of the material spacers 720 a .
- the dielectric layer 730 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer that can isolate neighboring conductive lines 710 .
- the dielectric layer 730 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a dielectric layer.
- the dielectric 730 such as a low-k dielectric layer, has a thickness of about 4,000 ⁇ to about 1 ⁇ m.
- the material spacers 720 a are substantially removed by an oxygen-containing plasma process to form the gaps 740 between the dielectric layer 730 and the conductive line 710 .
- the material spacers 720 a can be removed by a plasma process that has a desired etch rate for the material spacers 720 a , if the plasma process does not substantially damage the dielectric layer 730 and/or the conductive line 710 .
- the plasma process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 flow of oxygen
- RF radio-frequency
- the oxygen-containing plasma process can substantially remove the material spacers 720 a within the gaps 740 without substantially damaging the dielectric layer 730 and/or the conductive line 710 .
- the material spacers 720 a between the dielectric layer 730 and/or the conductive line 710 are substantially completely removed to expose portions of the top surface of the substrate 700 within the gaps 740 . In other embodiments, a portion of the material spacer 720 a remains within the gap 740 as long as a desired air gap 760 as shown in FIG. 7E can be obtained.
- a dielectric layer 750 is formed over the dielectric layer 730 and the conductive line 710 to seal the gaps 740 (shown in FIG. 7D ) to form the air gaps 760 .
- the dielectric layer 750 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer.
- the dielectric layer 750 has poor deposition conformity so that the dielectric layer 750 can be formed thicker at the top and bottom regions of the gap 740 and thinner at the central region of the gaps 740 .
- the dielectric layer 750 such as a plasma enhanced (PE) oxide, has a thickness of about 2,000 ⁇ to about 3,000 ⁇ from the top surface of the dielectric layer 730 to the top surface of the dielectric layer 750 .
- the dielectric layer 750 is formed by a plasma enhanced chemical vapor deposition (PECVD) process to seal top regions of the gaps 740 to form the air gaps 760 . With the air gaps 760 , the dielectric constant between neighboring conductive lines 710 is reduced. Thus, resistance-capacitance (RC) time delay resulting from parasitic capacitance between two neighboring conductive lines 710 can be reduced.
- PECVD plasma enhanced chemical vapor deposition
- FIGS. 8A-8F are schematic cross-sectional views illustrating a process for formation of a self-aligned contact plug.
- a pair of transistor gates 810 are formed over a substrate 800 .
- the transistor gate 810 includes, for example, a conductive layer 811 , a gate insulator 813 and spacers 815 .
- the substrate 800 can be similar to the substrate 200 as set forth above.
- the conductive layer 811 can be, for example, a polysilicon layer, amorphous silicon layer, silicon/silicon germanium (SiGe), a metal-containing layer, such as a TiN layer, or other conductive layer that can be a gate of a transistor.
- the conductive layer 811 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate of a transistor.
- the gate insulator 813 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can insulate the conductive layer 811 from the substrate 800 .
- the gate insulator 813 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate insulator of a transistor.
- the spacers 815 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can protect the conductive layer 811 from damages caused by subsequent process.
- the spacers 815 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate insulator of a transistor.
- the conductive layer 811 such as a polysilicon layer, has a thickness of about 1,200 ⁇ to about 1,700 ⁇ ;
- the gate insulator 813 such as an oxide layer, has a thickness of about 20 ⁇ to about 40 ⁇ ;
- a thickest portion of the spacer 815 such as nitride spacers, has a thickness of about 400 ⁇ to about 700 ⁇ ; and
- a distance “d” between the sidewalls of the conductive layers 811 is of about 0.2 ⁇ m to about 0.3 ⁇ m.
- a material layer 820 is formed over the transistor gates 810 and the substrate 800 .
- the material layer 820 is similar to the material layer 340 as described above. Detailed descriptions are not repeated.
- the material layer 820 has a thickness from the top surface of the substrate 800 to the top surface of the material layer 820 of about 3,800 ⁇ to about 4,300 ⁇ .
- a dielectric layer 823 is formed over the material layer 820 .
- the dielectric layer 823 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can be a hard mask for a subsequent etch process to form an opening within the material layer as shown in FIG. 8B .
- the dielectric layer 823 can be formed, for example, by a CVD process, PFD process, atomic layer deposition (ALD) process or other process that can form a dielectric hard mask.
- the dielectric layer 823 such as an oxynitride layer, has a thickness of about 600 ⁇ to about 1,000 ⁇ .
- a photoresist layer 825 including an opening 827 is formed over the dielectric layer 823 .
- the photoresist layer 825 can be formed by a photolithographic process.
- the opening 827 has a width of about 0.13 ⁇ m to about 0.15 ⁇ m.
- the opening 827 is defined at a location under which a contact plug 840 a as shown in FIG. 8D is to be formed.
- a portion of the dielectric layer 823 and a portion of the material layer 820 are removed to form an opening 830 within the material layer 820 a and between the transistor gates 810 to expose a partial top surface of the substrate 800 .
- the etch process has a desired selectivity for the material layer 820 a to the dielectric layers 823 a so that the etch process does not substantially damage the exposed top surface of the substrate 800 within the opening 830 .
- the remaining material 820 a are not substantially laterally etched by the etch process, so that a desired profile of the opening 830 is achieved.
- the etch process in order to obtain the desired profile of the opening 830 , includes a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process includes a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 oxygen
- RF radio-frequency
- the spacers 815 such as nitride spacers, serve as a hard mask when the portion of the material layer 820 is removed to form the opening 830 .
- the etch process has a desired etch selectivity, such as about 80:1 to about 120:1, for the material layer 820 a to the spacer 815 .
- the spacers 815 are not substantially damaged by the etch process and thus are able to protect the conductive layer 811 from being damaged.
- a conductive layer 840 is formed within the opening 830 , covering the dielectric layer 823 a .
- the conductive layer 840 can be, for example, an aluminum/ copper layer, aluminum layer, copper layer, tungsten layer or other conductive material layer.
- the conductive layer 840 can be formed, for example, by a CVD process, PVD process, chemical plating process, chemical electroless plating or other process that can form the conductive layer 840 .
- a barrier layer such as TiN (not shown), is formed within the opening 830 and over the dielectric layer 823 a.
- an etch-back process or CMN process removes the dielectric layer 823 a and a portion of the conductive layer 840 over the top surface of the material layer 820 a to form the conductive layer 840 a , i.e., a via/conduct plug, within the opening 830 .
- the etch-back or CMP process also removes a portion of the barrier layer over the top surface of the material layer 820 a.
- the remaining material layer 820 a is removed by an oxygen-containing plasma process to expose a top region of the conductive layer 840 a over a top surface of the transistor gate 810 .
- the material layer 820 a can be removed by a plasma process that has a desired etch rate for the material layer 820 a , if the plasma process does not substantially damage the substrate 800 , the conductive layer 840 a and/or the transistor gates 810 .
- the ash process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. Because the plasma process does not substantially damage the substrate 800 , the conductive layer 840 a and/or the transistor gates 810 , a desired profile of the conductive plug 840 a can be obtained as shown in FIG. 8E .
- O 2 flow of oxygen
- RF radio-frequency
- a dielectric layer 850 is formed, covering the transistor gates 810 and the conductive layer 840 a to expose a top surface of the conductive layer 840 a .
- the dielectric layer 850 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other material layer that can insulate the transistor gates 810 from other transistor gate or circuit (not shown).
- the dielectric layer 850 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process, spin-on process or other process that can form a dielectric layer.
- the dielectric layer 850 has a thickness of about 3,800 ⁇ to about 4,300 ⁇ from the top surface of the substrate 800 to the top surface of the dielectric layer 850 .
- the material layer 820 has a low thermal stability when the material layer 820 is subjected to a subsequent thermal process, such as a thermal curing process. The material layer 820 is thus removed and the dielectric layer 850 is formed to cover the transistor gates 810 so that subsequent thermal processes can be properly performed for the substrate 800 .
- the dimensions of the dielectric layers, material layer and gate transistor set forth above are illustrated by 90-nm or 65-nm semiconductor technology.
- the present invention is not limited thereto.
- One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired via/contact plug.
- FIGS. 9A-9E are schematic cross-sectional views illustrating a process for formation of a via/contact plug or a conductive line.
- a dielectric layer 910 is formed over a substrate 900 .
- the substrate 900 is similar to the substrate 200 . Detailed descriptions are not repeated.
- the substrate 900 includes, for example, at least one transistor, device or circuit (not shown) thereon coupled to a conductive layer 970 (shown in FIG. 9E ).
- the dielectric layer 910 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other material layer that can insulate the conductive layer 970 (shown in FIG. 9E ) from other conductive layer (not shown).
- the dielectric layer 910 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process, spin-on process or other process that can form a dielectric layer.
- the dielectric layer 910 such as an oxide layer, has a thickness of about 3,000 ⁇ to about 1.5 ⁇ m.
- a material layer 920 is formed over the dielectric layer 910 .
- the material layer 920 is similar to the material layer 340 described above. Detailed descriptions are not repeated.
- the material layer 920 has a thickness of about 2,500 ⁇ to about 8,000 ⁇ .
- a dielectric layer 930 is formed over the material layer 920 .
- the dielectric layer 930 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can serve as an etch stop layer.
- the dielectric layer 920 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process, spin-on process or other process that can form a dielectric layer.
- the dielectric layer 930 has a thickness of about 600 ⁇ to about 1,000 ⁇ .
- the photoresist layer 935 including an opening 937 therein is formed over the dielectric layer 930 .
- the photoresist layer 935 including the opening 937 therein can be formed by a photolithographic process.
- a portion of the dielectric layer 930 and a portion of the material layer 920 are removed to form an opening 940 within the remaining material layer 920 a to expose a portion of the top surface of the dielectric layer 910 .
- An etch process having a desired etch selectivity for the dielectric layer 930 to the material layer 920 removes the portion of the dielectric layer 930 defined by the opening 937 (shown in FIG. 9A ).
- the photoresist layer 935 is then removed by a photoresist removal process, and the remaining dielectric layer 930 a is used as a hard mask to protect the material layer 920 a from being damaged by the photoresist removal process.
- the dielectric layer 930 a is used as a hard mask layer for removal of the portion of the material layer 920 by an etch process.
- the photoresist layer 935 is removed while the material layer 920 is partially removed by a hydrogen-containing process.
- the opening 940 is formed within the material layer 920 a while the photoresist layer 935 is substantially removed.
- the sidewalls of the material layer 920 a are not substantially laterally etched by the etch process to obtain a desired profile of the opening 940 .
- a substantially conformal material layer 950 is formed over the opening 940 and the dielectric layer 930 a .
- the material layer 950 is similar to the material layer 230 as described above. In some embodiments, the material layer 950 has a thickness of about 200 ⁇ to about 400 ⁇ .
- the etch process includes a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process includes a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 oxygen
- RF radio-frequency
- a portion of the material layer 950 is removed by an etch process to expose a top surface of the dielectric layer 930 a and a portion of the top surface of the dielectric layer 910 and to form material spacers 950 a on sidewalls of the material layer 920 a .
- the material spacers 950 are not substantially laterally etched by the etch process so as to obtain a desired profile thereof.
- the material spacers 950 a is achieved so that an opening 960 (shown in FIG. 9D ) can be formed by a subsequent etch process.
- a via/contact hole or a trench of a conductive line with a small width i.e., the width of the opening 960 (shown in FIG. 9D ) is achieved.
- the ash process includes a flow of hydrogen (H 2 ) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N 2 ) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
- H 2 hydrogen
- N 2 nitrogen
- RF radio-frequency
- the etch process includes a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
- O 2 oxygen
- RF radio-frequency
- a portion of the dielectric layer 910 is removed to form the opening 960 within the dielectric layer 910 a by using the material spacers 950 a as a hard mask.
- the dielectric layer 930 a and portions of the material spacers 950 a over the top surface of the 920 a are removed by an etch process.
- the material spacers 950 a and the material layers 920 a are used as a hard mask for etching the dielectric layer 910 to form the opening 960 .
- the material spacers 950 a and the dielectric layer 930 a are used as a hard mask for etching the dielectric layer 910 to form the opening 960 .
- the etch process has a desired etch selectivity for the dielectric layer 930 a to the material spacers 950 a so that the material spacers 950 a are not substantially removed.
- the material spacers 950 a and the material layer 920 a are removed by an oxygen-containing plasma process, and the conductive layer 970 is formed within the opening 960 .
- the material spacers 950 a and the material layer 920 a can be removed by a plasma process that has a desired etch rate for the material layer 920 a and spacers 950 a , if the plasma process does not substantially damage the exposed portion of the top surface of the substrate 900 and/or the dielectric layer 910 a .
- the plasma process comprises: a flow of oxygen (O 2 ) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. Because the plasma process does not substantially damage the exposed top surface of the substrate 900 and/or the dielectric layer 910 a (as shown in FIG. 9E ), the conductive layer 970 can be properly formed within the opening 960 .
- O 2 flow of oxygen
- RF radio-frequency
- the conductive layer 970 can be, for example, an aluminum/copper layer, aluminum layer, copper layer, tungsten layer or other conductive material layer.
- the conductive layer 970 can be formed, for example, by a CVD process, PVD process, chemical plating process, chemical electroless plating or other process that can form the conductive layer 970 .
- the dimensions of the dielectric layers, material layers and openings vary with the metal level where the conductive layer 970 is formed. For example, if the conductive layer 970 is formed within an inter-layer dielectric (ILD) layer, the conductive line 910 has small physical dimensions. If the conductive layer 970 is formed as a top metal layer over the substrate, the conductive layer 970 has large physical dimensions.
- ILD inter-layer dielectric
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- Semiconductor Memories (AREA)
Abstract
A method includes the steps of: (a) forming a conductive layer within a dielectric layer formed over a substrate; (b) forming a material layer over the conductive layer and the dielectric layer; (c) forming an opening within the material layer by an etch process to expose a portion of the dielectric layer and a top surface of the conductive layer; (d) forming a first metal-containing layer within the opening substantially covering sidewalls of the material layer and the exposed portion of the second dielectric layer; and (e) removing the material layer by an oxygen-containing plasma process to expose a portion of outer sidewalls of the first metal-containing layer.
Description
- 1. Field of the Invention
- The present invention relates to semiconductor methods, and more particularly to semiconductor methods related to amorphous carbon layers.
- 2. Description of the Related Art
- With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high integration and speed targets, dimensions of semiconductor integrated circuits have been reduced and various materials, such as amorphous carbon, have been proposed along with techniques for overcoming manufacturing obstacles associated with these materials.
- Amorphous carbon is a new material used in semiconductor technology. An amorphous carbon layer can be formed substantially conformally over a semiconductor structure over a substrate by a chemical vapor deposition (CVD) process. In addition, the amorphous carbon layer has a desired thermal stability even between about 400° C. and about 550° C. The amorphous carbon layer will not crack in this temperature range. (The temperature range would result in cracking of organic material, such as photoresist.) Further, the amorphous carbon layer can be removed by an oxygen plasma that is used to remove a photoresist layer as well. Thus, an amorphous carbon layer can serve as a hard mask and/or anti-reflection coating (ARC) layer under a photoresist layer to form a via/contact plug in nanometer level semiconductor technology.
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FIGS. 1A-1C are schematic cross-sectional views illustrating a process for formation of a via/contact plug. - Referring to
FIG. 1A , anoxide layer 110, anamorphous carbon layer 120, anoxynitride layer 130 andphotoresist layer 135 are sequentially formed over asubstrate 100. Thephotoresist layer 135 includes anopening 137 therein for forming a via/contact hole inFIG. 1B . - A portion of the
amorphous carbon layer 120 and a portion of theoxynitride layer 130 are removed by an etch process to form anopening 140 within theamorphous carbon layer 120 a as shown inFIG. 1B . Thephotoresist layer 135 is then removed by a photoresist removal process. For some semiconductor processes, the removal of thephotoresist layer 135 and the partial removals of the amorphous carbon layer and oxynitride layer for forming theopening 140 are performed by the same etch process. - Referring to
FIG. 1C , theoxynitride layer 130 a and theamorphous carbon layer 120 a are removed. Theamorphous carbon layer 120 a can be removed by oxygen plasma. Ametal layer 150 is then formed within theopening 140. - In accordance with some exemplary embodiments, a method includes the steps of: (a) forming a conductive layer within a dielectric layer formed over a substrate; (b) forming a material layer over the conductive layer and the dielectric layer; (c) forming an opening within the material layer by an etch process to expose a portion of the dielectric layer and a top surface of the conductive layer; (d) forming a first metal-containing layer within the opening substantially covering sidewalls of the material layer and the exposed portion of the second dielectric layer; and (e) removing the material layer by an oxygen-containing plasma process to expose a portion of outer sidewalls of the first metal-containing layer.
- The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings.
- Following are brief descriptions of exemplary drawings. They are mere exemplary embodiments and the scope of the present invention should not be limited thereto.
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FIGS. 1A-1C are schematic cross-sectional views illustrating a process for formation of a via/contact plug. -
FIGS. 2A-2E are schematic cross-sectional views illustrating a process for formation of a shallow trench isolation (STI) structure. -
FIG. 3A is a schematic top view of a crown metal capacitor.FIGS. 3B-3G are schematic cross-sectional views illustrating a process for formation of the crown metal capacitor ofFIG. 3A . -
FIGS. 4A-4E are schematic cross-sectional views illustrating a process for formation of a select gate of a flash transistor. -
FIGS. 5A-5D are schematic cross-sectional views illustrating a process for formation of a source/drain region of a transistor. -
FIGS. 6A-6E are schematic cross-sectional views illustrating a process for formation of air gaps over a pixel. -
FIGS. 7A-7E are schematic cross-sectional views illustrating a process for formation of air gaps next to a conductive layer. -
FIGS. 8A-8F are schematic cross-sectional views illustrating a process for formation of a self-aligned contact plug. -
FIGS. 9A-9E are schematic cross-sectional views illustrating a process for formation of a via/contact plug or a conductive line. - This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.
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FIGS. 2A-2E are schematic cross-sectional views illustrating a process for formation of a shallow trench isolation (STI) structure. - Referring to
FIG. 2A , adielectric layer 210 including an opening 220 therein is formed over asubstrate 200. Theopening 220 exposes a portion of atop surface 200 a of thesubstrate 200. Thesubstrate 200 can be a semiconductor substrate, display substrate such as a liquid crystal display (LCD), plasma display, cathode ray tube display or electro luminescence (EL) lamp display, or light emitting diode (LED) substrate (collectively referred to as, substrate 200), for example. Thedielectric layer 210 can be, for example, an oxide layer, nitride layer, oxynitride layer or other dielectric layer that is adapted to be a hard mask layer. Thedielectric layer 210 can be formed, for example, by a chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, spin-on method or other method that is adapted to form a dielectric material over thesubstrate 200. In some embodiments of 90-nm or 65-nm semiconductor technology, thedielectric layer 210 can be a silicon nitride layer, for example. In such embodiments, thedielectric layer 210 from thetop surface 200 a of thesubstrate 200 to the top surface of thedielectric layer 210 has a thickness of about 800 Å to about 1,200 Å. In addition, theopening 220 between the sidewalls of thedielectric layer 210 has a width of about 800 Å to about 1,500 Å. - A substantially
conformal material 230 is formed over thedielectric layer 210 and theopening 220. Thematerial layer 230 can be removed by an oxygen-containing plasma process. Thematerial layer 230 can be, for example, an amorphous carbon layer. In some embodiments of 90-nm or 65-nm semiconductor technology, thematerial layer 230 has a thickness of about 150 Å to about 250 Å from the top surface of thedielectric layer 210 to the top surface of thematerial layer 230. - In some embodiments, a
material layer 230, such as an amorphous carbon layer, can be formed by a low deposition rate process to obtain a substantially conformal layer over thedielectric layer 210 and theopening 220. An exemplary low deposition rate process includes: a flow of C3H6 between about 1,000 standard cubic centimeters per minute (sccm) and about 1,500 sccm; a flow of He between about 400 sccm and about 500 sccm; a radio-frequency (RF) power between about 800 watts and about 1,200 watts; and a pressure between about 3.5 Torr and about 4.5 Torr. In other embodiments, thematerial layer 230 can be formed by a high deposition rate process as long as the conformity of thematerial layer 230 is desired. An exemplary high deposition rate process includes: a flow of C3H6 between about 1,500 standard cubic centimeters per minute (sccm) and about 2,500 sccm; a flow of He between about 500 sccm and about 900 sccm; a radio-frequency (RF) power between about 1,200 watts and about 1,800 watts; and a pressure between about 4.5 Torr and about 5.5 Torr. - Referring to
FIG. 2B , a portion of thematerial layer 230 is removed by an etch process to formmaterial spacers 230 a on sidewalls of thedielectric layer 210. In some embodiments, thematerial spacers 230 a are not substantially laterally etched by the etch process, so that a desired profile of thematerial spacers 230 a is achieved. In order to obtain the desired profile of thematerial spacers 230 a, the etch process may include: a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. - Referring to
FIG. 2C , atrench 240 is formed within thesubstrate 200 by using thefirst dielectric layer 210 and thematerial spacers 230 a as a hard mask. Thetrench 240 can be formed, for example, by an etch process that has a desired etch selectivity for the material of the substrate, such as silicon, to thefirst dielectric layer 210, such as silicon nitride, and thematerial spacers 230 a, such as amorphous carbon, so that the etch process does not substantially laterally etch thematerial spacers 230 a. In some embodiments of 90-nm or 65-nm semiconductor technology, thetrench 240 has a depth of about 2,800 Å to about 3,800 Å. With the desired profile of thematerial spacers 230 a as described above, a desired trench profile can be obtained. - Referring to
FIG. 2D , thematerial spacers 230 a are removed by an oxygen-containing plasma process. After the removal of thematerial spacers 230 a, the opening is increased by a pull-back distance “d” from the sidewall of thedielectric layer 210 to the top edge of thetrench 240. By increasing the opening size by the distance “d”, i.e., extending the opening between thedielectric layer 210 over thetrench 240, a dielectric layer (not shown) can be properly filled within thetrench 240 and the opening between thedielectric layer 210 in a subsequent process. The oxygen-containing plasma process removes thematerial spacers 230 a. In some embodiments, thematerial spacers 230 a can be removed by an ash process that has a high etch rate, if the ash process does not substantially damage the profile of thetrench 240. In some embodiments, in which thematerial spacers 230 a include amorphous carbon, the ash process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - In some embodiments, the etch process for the formation of the
material spacers 230 a as shown inFIG. 2B can be used to remove thematerial spacers 230 a, if the desired removal rate of thematerial spacers 230 a can be achieved and the profile of thetrench 240 is not substantially damaged. Further, the oxygen-containing plasma process for the removal of thematerial spacers 230 a can be used for the formation of thematerial spacers 230 a, if the desired profile of thematerial spacers 230 a can be formed. One of ordinary skill in the art can readily use the etch process and oxygen-containing plasma process to obtain a desired profile of thematerial spacers 230 a and/or to remove thematerial spacers 230 a. - Referring to
FIG. 2E , a dielectric layer 250 is filled within thetrench 240. The steps of forming of the dielectric layer 250 within the trench include: forming a dielectric material layer 250 within thetrench 240; and removing thedielectric layer 210 and a portion of the dielectric material layer 250 over the top surface of thesubstrate 200. In some embodiments, the dielectric layer 250 can be, for example, a high density plasma (HDP) dielectric layer or other dielectric layer that can isolate two active regions of thesubstrate 200. The HDP dielectric layer can be formed, for example, by a HDP CVD. Thedielectric layer 210 and the portion of the dielectric material layer over the top surface of thesubstrate 200 can be removed, for example, by an etch-back process or chemical mechanical polishing (CMF) process. As described above, the pull-back distance “d” allows the dielectric material layer 250 be properly filled within thetrench 240 and the opening between the dielectric layers 210. Accordingly, a desired STI structure is formed. - The dimensions of the dielectric layers, material layer and trench set forth above are illustrated by 90-nm or 65-nm semiconductor technology. The present invention is not limited thereto. One of ordinary skill in the art can understand that these physical characteristics vary with the applied semiconductor process and readily form a desired STI structure.
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FIG. 3A is a schematic top view of a crown metal capacitor.FIGS. 3B-3G are schematic cross-sectional views illustrating a process for formation of the crown metal capacitor ofFIG. 3A . - Referring to
FIG. 3A , the metal-insulator-metal (MIM)capacitor 395 can have, for example, a circle shape, oval shape, square shape, or rectangular shape. In some embodiments, an ovalshape MIM capacitor 395 includes a long-axis “a” of about 0.15 Jim to about 0.25 μm and a short-axis “b” of about 0.07 μm to about 0.15 μm. - Referring to
FIG. 3B ,dielectric layers substrate 300. Aconductive layer 330 is formed within thedielectric layers substrate 300 is similar to thesubstrate 200 as set forth above. In some embodiments, thesubstrate 300 can include at least one transistor or device (now shown) thereon in contact with theconductive layer 330. Thedielectric layer 310 can be, for example, an oxide layer, low-k dielectric layer or other dielectric layer that can isolate two conductive structures, such as metal lines or via/contact plugs. Thedielectric layer 310 can be formed, for example, by a CVD process, PVD process, spin-on process or other method that can form a dielectric layer over thesubstrate 300. Thedielectric layer 320 can be, for example, a nitride layer, oxynitride layer or other material layer that can protect thedielectric layer 310 from exposure to a subsequent dry or wet etch process or photolithographic process. Thedielectric layer 320 can be formed, for example, by a CVD process, PVD process, spin-on process or other method that can form a dielectric layer over thesubstrate 300. In some embodiments of 90-nm or 65-nm semiconductor technology, thedielectric layer 310 is an oxide layer and thedielectric layer 320 is an oxynitride layer, for example. In the example ofFIG. 3B , thedielectric layer 320 has a thickness of about 200 Å to about 300 Å. - The
conductive layer 330 is formed within thedielectric layers substrate 300 and a bottom electrode of a capacitor, i.e., the metal-containinglayer 370 a (shown inFIG. 3F ). Theconductive layer 330 can be, for example, a tungsten plug, aluminum/copper plug, copper plug or other conductive layer that can connect a transistor and a bottom electrode of a capacitor. Theconductive layer 330 can be formed, for example, by CVD, PVD, chemical electrical plating, chemical electroless plating method or other method that can form theconductive layer 330. In some embodiments, an etch-back or CMP process is applied to remove the material of theconductive layer 330, which is formed over the top surface of thedielectric layer 320 by a CVD method or PVD method. In other embodiments, the etch-back or CMP process is not used, if theconductive layer 330 is formed beginning from the top surface of thesubstrate 300 and stopping at the region proximate to the top surface of thedielectric layer 320 by a chemical electrical plating method or chemical electroless plating method. - A
material layer 340 is formed over theconductive layer 330 and thedielectric layer 320. Thematerial layer 340 can be removed by an oxygen-containing plasma process. Thematerial layer 340 can be, for example, an amorphous carbon layer. In some embodiments of 90-nm or 65-nm semiconductor technology, thematerial layer 340 has a thickness of about 2,500 Å to about 6,000 Å. - In some embodiments, the
material layer 340, such as an amorphous carbon layer, can be formed by a high deposition rate process to obtain a material layer over thedielectric layer 320 and theconductive layer 330. A high deposition rate process can reduce the processing time for the formation of the MIM capacitor. In some embodiments, the high deposition rate process includes: a flow of C3H6 between about 1,500 standard cubic centimeters per minute (sccm) and about 2,500 sccm; a flow of He between about 500 sccm and about 900 sccm; a radio-frequency (RF) power between about 1,200 watts and about 1,800 watts; and a pressure between about 4.5 Torr and about 5.5 Torr. In other embodiments, thematerial layer 340 can be formed by a low deposition rate process as long as the deposition rate of thematerial layer 340 is desired. In some embodiments, the low deposition rate process includes: a flow of C3H6 between about 1,000 standard cubic centimeters per minute (sccm) and about 1,500 sccm; a flow of He between about 400 sccm and about 500 sccm; a radio-frequency (RF) power between about 800 watts and about 1,200 watts; and a pressure between about 3.5 Torr and about 4.5 Torr. - A
dielectric layer 350 is formed over thematerial layer 340. Thedielectric layer 350 can be, for example, a nitride layer, oxynitride layer or other material layer that is adapted to be a hard mask for an etch process or CMP process. In some embodiments of 90-nm or 65-nm semiconductor technology, thedielectric layer 350 can be an oxynitride layer, for example, and has a thickness of about 600 Å to about 1,000 Å. - A
photoresist layer 355 including anopening 357 therein is formed over thedielectric layer 350. Theopening 357 exposes a portion of the top surface of thedielectric layer 350. Theopening 357 can be defined by a photolithographic process. Theopening 357 defines dimensions of themetal capacitor 395. - The
dielectric layer 350 protects thematerial layer 340 from being removed if the process for removing thephotoresist layer 355 also substantially removes thematerial layer 340. - Referring to
FIG. 3C , anopening 360 is formed within thematerial layer 340 and thedielectric layer 350 to expose a portion of the top surface of thedielectric layer 320 and a top surface of theconductive layer 330. Theopening 360 is defined based on theopening 357 shown inFIG. 3B . The steps for formingopening 360 include, for example, removing a portion of thedielectric layer 350 and a portion of thematerial layer 340. The process for removing the portion of thedielectric layer 350, for example, can have a desired etch selectivity for thedielectric layer 350 to thematerial layer 340. The etch process for removing the portion of thematerial layer 340, for example, can have a desired etch selectivity for thematerial layer 340 to thedielectric layers 320 and/or 350, e.g., oxynitride layer. - In some embodiments, the etch process has a desired selectivity for the
material layer 340 to thedielectric layers 320 and/or 350 so that the etch process does not substantially damage thedielectric layers 320 and/or 350. In some embodiments, the remainingmaterial 340 a are not substantially laterally etched by the etch process, so that a desired profile of theopening 360 is achieved. In order to obtain the desired profile of theopening 360, in some embodiments, the etch process includes a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. In other embodiments, in which the profile of theopening 360 is not a concern, the etch process includes a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. After the formation of theopening 360, thephotoresist layer 355 is removed. The removal process of thephotoresist layer 355 can be, for example, a traditional photoresist removal process. In other embodiments, thephotoresist layer 355 is removed while thedielectric layer 350 andmaterial layer 340 are partially removed. In other words, theopening 360 is formed within thedielectric layer 350 a and remainingmaterial layer 340 a while thephotoresist layer 355 is substantially removed. - Referring to
FIG. 3D , a substantially conformal metal-containinglayer 370 is formed over thedielectric layer 350 and theopening 360. A photoresist layer 375 is then formed over the metal-containinglayer 370 and within theopening 360. The metal-containinglayer 370 can be, for example, a titanium nitride (TiN) layer or other metal-containing layer that can be a bottom electrode of a metal-insulator-metal (MIM) capacitor. The metal-containinglayer 370 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the metal-containinglayer 370. In some embodiments of 90-nm or 65-nm semiconductor technology, the metal-containinglayer 370 has a thickness of about 150 Å to about 300 Å. The photoresist layer 375 can be formed, for example, by a traditional photolithographic process. - Referring to
FIG. 3E , a top portion of the photoresist layer 375, a portion of the metal-containinglayer 370 and thedielectric layer 350 a are removed. The photoresist layer 375 within theopening 360 is then removed. In some embodiments, the top portion of the photoresist layer 375, the portion of the metal-containinglayer 370 and thedielectric layer 350 a can be removed by a sequence of etch processes. In other embodiments, the top portion of the photoresist layer 375, the portion of the metal-containinglayer 370 and thedielectric layer 350 can be removed by a CMP process. Then, the remaining photoresist layer 375 within theopening 360 is removed by a photoresist removal process, which may be a traditional process, for example. After the removal of the remaining photoresist layer 375, the metal-containinglayer 370 a is formed within theopening 360, substantially covering sidewalls of thematerial layer 340 and the portion of the top surface of thedielectric layer 320 thereunder. - Referring to
FIG. 3F , thematerial layer 340 a is removed by an oxygen-containing plasma process to expose a portion ofouter sidewalls 370 b of the metal-containinglayer 370 a. During the plasma process, thedielectric layer 320 can be an etch-stop layer to protect thedielectric layer 310 from being damaged. For example, the plasma process has a desired etch selectivity for thematerial layer 340 a to thedielectric layer 320 so that the plasma process can remove thematerial layer 340 a without substantially damaging thedielectric layer 320. Further, the plasma process does not substantially damage the metal-containinglayer 370 a, i.e., the bottom electrode of the capacitor 395 (shown inFIG. 3A ). In some embodiments, the ash process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Due to the exposed
outer sidewalls 370 b of the metal-containinglayer 370, the surface area of thecapacitor 395 is thus increased. The capacitance of thecapacitor 395 is also enhanced. - In some embodiments, a portion of the
material layer 340 a remains on theouter sidewalls 370 b of the metal-containinglayer 370 a, if the remainingmaterial layer 340 a does not adversely affect electrical performance of the transistor (not shown) over thesubstrate 300 and thecapacitor 395, and/or subsequent process, such as wafer contamination or film cracking when thematerial layer 340 a is subjected to thermal treatments. Also, the remaining portion of thematerial layer 340 a reduces the area of theouter sidewalls 370 b of the metal-containinglayer 370 a. The area and capacitance of thecapacitor 395 are thus reduced. -
FIG. 3G is a schematic cross-sectional view of thecapacitor 395 shown inFIG. 3A taken alongsection line 3G-3G. Referring toFIG. 3G , acapacitor insulator 380 and a metal-containinglayer 370, i.e., a top electrode of thecapacitor 395, are formed over the metal-containinglayer 370 a, i.e., the bottom electrode of thecapacitor 395, and thedielectric layer 320. Thecapacitor insulator 380 substantially covers the exposedouter sidewalls 370 b, top regions and inner sidewalls of the metal-containinglayer 370. The metal-containinglayer 390 substantially covers thecapacitor insulator layer 380. Thecapacitor insulator 380 can be, for example, an aluminum oxide layer, tantalum oxide layer, zinc oxide layer or other material layer that has a high dielectric constant and is adapted for theMIM capacitor 395. Thecapacitor insulator 380 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form thecapacitor insulator 380. The metal-containinglayer 390 can be, for example, a TiN layer which can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a metal top electrode. - The dimensions of the dielectric layers, material layer and metal-containing layers set forth above are illustrated for examples using 90-nm or 65-nm semiconductor technology. The present invention is not limited thereto. One of ordinary skill in the art can understand that these physical characteristics vary with the applied semiconductor process and can readily form a desired MIM capacitor.
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FIGS. 4A-4E are schematic cross-sectional views illustrating a process for formation of a select gate of a flash transistor. - Referring to
FIG. 4A , a pair offlash transistor gates 410 are formed over asubstrate 400. Thesubstrate 400 may be similar to thesubstrate 200 described above. Theflash transistor gate 410 includes agate insulator 411, a floatinggate 413, aninter-gate insulator 415, acoupling gate 417, acap layer 419 andspacers 412. Thegate insulator 411 can be, for example, an oxide layer, nitride layer, oxynitride layer or other insulator layer. Thegate insulator 411 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form theinsulator 411. The floatinggate 413 can be, for example, a polysilicon layer which can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form the floatinggate 413. Theinter-gate insulator 415 can be, for example, an oxide layer, nitride layer, oxynitride layer, nitride/ oxide (NO) layer, oxide/nitride/oxide (ONO) layer or other insulator layer. Theinter-gate insulator 415 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form theinter-gate insulator layer 415. Thecoupling gate 417 can be, for example, a polysilicon layer which can be formed, for example, by a CVD process, r-VD process, atomic layer deposition (ALD) process or other process that can form thecoupling gate 417. Thecap layer 419 and thespacers 412 can be, for example, an oxide layer, nitride layer, oxynitride layer or other insulator layer. Thecap layer 419 and thespacers 412 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form thecap layer 419 and thespacers 412. - In some embodiments of 90-nm or 65-nm semiconductor technology, the
gate insulator 411, such as an oxide layer, has a thickness of about 90 Å to about 150 Å; the floatinggate 413, such as a polysilicon layer, has a thickness of about 500 Å to about 800 Å; theinter-gate insulator 415, such as an ONO layer, has a thickness of about 35/35/45 Å to about 65/65/85 Å, respectively; thecoupling gate 417, such as a polysilicon layer, has a thickness of about 500 Å to about 1,000 Å; thecap layer 419, such as an oxide layer, has the a thickness of about 700 Å to about 1,200 Å; the thickest portion of thespacer 412, such as a nitride spacer, has a width of about 200 Å to about 500 Å; and thegap 405 between the sidewalls of the floatinggates 413 has a width of about 1,000 Å to about 2,000 Å. - A
sacrificial layer 420 is formed, covering theflash transistor gates 410 and filling within thegap 405 between theflash transistor gates 410. Thesacrificial layer 420 can be, for example, a material layer that can be removed by an oxygen-containing plasma process, or a dielectric layer, such as an oxide layer or nitride layer. In some embodiments, the material layer comprises an amorphous carbon layer. In some embodiments of 90-nm or 65-nm semiconductor technology, thesacrificial layer 420 has a thickness of about 2,000 Å to about 3,000 Å. - In some embodiments, the
sacrificial layer 420 is an amorphous carbon layer. Thesacrificial layer 420 is similar to thematerial layer 340 described above. Detailed descriptions are not repeated. - Referring to
FIG. 4B , a portion of thesacrificial layer 420 is removed by an etch process to form the remainingsacrificial layer 420 a within the gap. Thesacrificial layer 420 a includes a top surface, lower than or substantially equal to a top region of theflash transistor gate 410, such as thetop surface 410 a of theflash transistor gate 410. Due to the large thickness of thesacrificial layer 420 between theflash transistor gates 410 and/or the aspect ratio, i.e., depth/width, of thegap 405, thesacrificial layer 420 a remains within thegap 405 between theflash transistor gates 410, when thesacrificial layer 420 outside of thegap 405 between theflash transistor gates 410 is completely removed. In some embodiments of 90-nm or 65-nm semiconductor technology, the highest portion of thesacrificial layer 420 a has a dimension of about 1,000 Å to about 2,500 Å. - In some embodiments, the
sacrificial layer 420 can be removed by an etch process that has a desired etch rate, if the etch process does not substantially damage thesubstrate 400. In some embodiments in which thesacrificial layer 420 includes amorphous carbon, the etch process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. In other embodiments, the etch process has a desired selectivity of about 80:1 to about 120:1 for thesacrificial layer 420, such as an amorphous carbon layer, to thespacers 412, such as nitride spacers. The etch process includes a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. - Referring to
FIG. 4C , aconductive layer 430 is formed, covering theflash transistor gates 410, thesacrificial layer 420 a and thesubstrate 400. Theconductive layer 430 can be, for example, a polysilicon layer, aluminum layer, copper layer, aluminum/copper layer or other conductive material layer. Theconductive layer 430 can be formed, for example, by a CVD process, PVD process, chemical plating process or other process that can form theconductive layer 430. In some embodiments of 90-nm or 65-nm semiconductor technology, theconductive layer 430, such as a polysilicon layer, has a thickness of about 1,500 Å to about 2,000 Å from thetop surface 410 a of theflash gate transistor 410 to the top surface of theconductive layer 430. - A
photoresist layer 435 including anopening 437 therein is formed over theconductive layer 430. Thephotoresist layer 435 including theopening 437 therein can be formed by a photolithographic process. - Referring to
FIG. 4D , a portion of theconductive layer 430 is removed by an etch process to expose the top surface of thesacrificial layer 420 a. The remainingconductive layer 430 a is the select gate of the flash transistor. In some embodiments, the etch process has a desired etch selectivity for theconductive layer 430 to thetop surface 410 a of theflash transistor gate 410, e.g., thecap layer 419, so that the etch process does not substantially damage theflash transistor gate 410, e.g., thecoupling gate 417. Thephotoresist layer 435 is then removed by a photoresist removal process. - Referring to
FIG. 4E , thesacrificial layer 420 a within thegap 405 between theflash transistor gates 410 is removed by an oxygen-containing plasma process. In some embodiments, thesacrificial layer 420 a can be removed by an oxygen-containing plasma process that has a desired etch rate, if the plasma process does not substantially damage the exposed surface of thesubstrate 400, theconductive layer 430 a and/or theflash transistor gates 410 as shown inFIG. 4E . In some embodiments, in which thesacrificial layer 420 a includes amorphous carbon, the plasma process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. In other embodiments, thephotoresist layer 435 andsacrificial layer 420 a are removed by the same etch process. For these embodiments, at least one removal process, either the removal process of thesacrificial layer 420 a or the removal process of thephotoresist layer 435, can be omitted. - In a process without the
sacrificial layer 420 a within thegap 405, a conductive layer is completely filled within thegap 405. The conductive layer in thegap 405 from the top surface of thesubstrate 400 to the top surface of the conductive layer must be removed. Due to the large height of the conductive layer within thegap 405, an over-etch, such as a polysilicon over-etch, is used to remove the conductive layer within thegap 405. The over-etch may damage the exposed substrate or transistor gates. Compared with the above-described process, when asacrificial layer 420 a is used, the height of theconductive layer 430 within thegap 405 as shown inFIG. 4C is reduced due to the remainingsacrificial layer 420 a. Theconductive layer 430 within thegap 405 can be properly and completely removed without an undesired over-etch. After the removal of theconductive layer 430 within thegap 405, thesacrificial layer 420 a is exposed. Thesacrificial layer 420 can be properly removed by the etch process, such as the oxygen-containing plasma process. Accordingly, the window to form theconductive layer 430 a, i.e., the select gate of the flash transistor, is increased. - The dimensions of the dielectric layers, material layer and conductive layers set forth above are illustrated for examples using 90-nm or 65-nm semiconductor technology. The present invention is not limited thereto. One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired flash transistor.
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FIGS. 5A-5D are schematic cross-sectional views illustrating a process for formation of a source/drain region of a transistor. - Referring to
FIG. 5A , atransistor gate 510 is formed over asubstrate 500. Thetransistor gate 510 includes aconductive layer 511 and agate insulator 513. Adielectric layer 515 is formed over thetransistor gate 510 and thesubstrate 500. A substantiallyconformal material layer 520 is formed over thedielectric layer 515. Thesubstrate 500 may be similar to thesubstrate 200 as set forth above. Theconductive layer 511 can be, for example, a polysilicon layer, amorphous silicon layer, silicon/silicon germanium (SiGe), a metal-containing layer, such as a TiN layer, or other conductive layer that can be a gate of a transistor. Theconductive layer 511 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate of a transistor. In some embodiments, the process is applied in 90-nm or 65-nm semiconductor technology. In some embodiments, theconductive layer 511 has a thickness of about 1,200 Å to about 1,700 Å. Thegate insulator 513 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can insulate theconductive layer 511 from thesubstrate 500. Thegate insulator 513 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate insulator of a transistor. In some embodiments of 90-nm or 65-nm semiconductor technology, theconductive layer 511, such as a polysilicon layer, has a thickness of about 1,200 Å to about 1,700 Å; and thegate insulator 513, such as an oxide layer, has a thickness of about 20 Å to about 40 Å. - The
dielectric layer 515 can be, for example, an oxide layer, nitride layer, oxynitride layer or other dielectric layer that has an etch selectivity different from that of thematerial layer 520 and that of thesubstrate 500. Thedielectric layer 515 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form thedielectric layer 515. In some embodiments of 90-nm or 65-nm semiconductor technology, thedielectric layer 515, such as a nitride layer, has a thickness of about 250 Å to about 350 Å. Thematerial layer 520 is similar to thematerial layer 230 as set forth above. - Referring to
FIG. 5B , a portion of thematerial layer 520 is removed by an etch process to formmaterial spacers 520 a on sidewalls of thetransistor gate 510 and to expose a top region of thedielectric layer 515 and the other regions not covered by thematerial spacers 520 a. In some embodiments, thematerial spacers 520 are not substantially laterally etched by the etch process to obtain a desired profile thereof. The desired profile of thespacers 520 a is used to define source/drain regions 530 at desired locations as shown inFIG. 5D . The desired locations of the source/drain regions 530 can prevent or reduce short-channel effect and/or punch-through effect between the source/drain regions 530. - In some embodiments, the etch process has a desired etch selectivity for the
material layer 520, such as an amorphous carbon, to thedielectric layer 515, such as a nitride layer. In some embodiments, the etch selectivity is of about 80:1 to about 120:1. In order to achieve the desired selectivity and/or profile, the etch process may include a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. Thus, the etch process does not substantially damage thedielectric layer 515 and thesubstrate 500 can be effectively protected by thedielectric layer 515. In still other embodiments, the etch process may include: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Referring to
FIG. 5C , a portion of thedielectric layer 515 and a portion of thematerial spacers 520 a are removed and the source/drain regions 530 are formed within thesubstrate 500 adjacent to thetransistor gate 510. The remainingdielectric layer 515 a has an L-shape structure. The portion of thedielectric layer 515 and portion of thematerial spacers 520 a can be removed by a dry etch process that has substantially equal, or higher, etch selectivity for thedielectric layer 515 to thematerial spacers 520 a. In some embodiments, the process to remove thedielectric layer 515 does not substantially damage thesubstrate 500 so as to cause undesired current leakage at the source/drain regions 530. The source/drain regions 530 can be formed by an ion implantation process. For ion implantation, thematerial spacers 520 a are used as a hard mask to prevent ions implanted substantially into thesubstrate 500 under thetransistor gate 510 and thematerial spacers 520 a. The source/drain regions 530 can be N or P type source/drain regions. - Referring to
FIG. 5D , thematerial spacers 520 a are removed by an oxygen-containing plasma process. In some embodiments, thematerial spacers 520 a can be removed by an ash process that has a desired etch rate for thematerial spacers 520 a, if the ash process does not substantially damage thesubstrate 500, theconductive layers 511 and/or the source/drain regions 530. In some embodiments in which thematerial spacers 520 a include amorphous carbon spacers, the plasma process includes: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. Accordingly, the plasma process will not substantially damage thesubstrate 500, theconductive layers 511 and/or the source/drain regions 530. - In some embodiments, lightly-doped drain (LDD) regions (not shown) are formed within the
substrate 500 under the L-shaped dielectric layers 515. The LDD regions can be formed by an ion implantation process, for example. - The dimensions of the dielectric layers, material layer and conductive layer set forth above are illustrated for examples using 90-nm or 65-nm semiconductor technology. The present invention is not limited thereto. One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired source/drain structure.
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FIGS. 6A-6E are schematic cross-sectional views illustrating a process for formation of air gaps over a pixel. - Referring to
FIG. 6A , apixel 610 is formed within adielectric layer 615 over asubstrate 600. Thesubstrate 600 may be similar to thesubstrate 200. In some embodiments, thesubstrate 600 include at least one transistor, device or circuit (not shown) coupled to thepixel 610. Thepixel 610 can be, for example, a CMOS image sensor (CIS), charge coupled device (CCD), liquid crystal display (LCD) pixel, plasma display pixel, electro luminescence (EL) lamp display pixel, or light emitting diode (LED) pixel (collectively referred to as, pixel 610). Thedielectric layer 615 can be, for example, an oxide layer, nitride layer, oxynitride layer or other dielectric layer that can isolate twopixels 610. Thedielectric layer 615 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form thedielectric layer 615. - A
dielectric layer 620 having anopening 625 is formed over thepixel 610 and thedielectric layer 615. Theopening 625 exposes a substantial top surface of thepixel 610. Thedielectric layer 615 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer. In some embodiments for 0.18-μm semiconductor technology, theopening 625 has a width of about 2.5 μm to about 3.5 μm; and thedielectric layer 615, such as an oxide layer, has a thickness from 2.8 μm to about 3.8 μm. - A substantially
conformal material layer 630 is formed over thedielectric layer 620 and the exposed top surface of thepixel 610. Thematerial layer 630 is similar to thematerial layer 230 as set forth above. In some embodiments for 0.18-μm semiconductor technology, thematerial layer 630, such as an amorphous carbon layer, has a thickness of about 1,000 Å to about 1,500 Å. - Referring to
FIG. 6B , a portion of thematerial layer 630 is removed by an etch process to formmaterial spacers 630 a on sidewalls of thedielectric layer 615. The etch process also removes a portion of thematerial layer 630, which covers thepixel 610 to substantially expose the top surface of thepixel 610. In some embodiments, thematerial spacers 630 a are not substantially laterally etched by the etch process so as to obtain a desired profile thereof. The desired profile of thematerial layer 630 is then removed to obtain a desired width ofgaps 650 as shown inFIG. 6D . The width of thegaps 650 is used to form desiredair gaps 670 as shown inFIG. 6E . Theair gaps 670 can effectively reduce or prevent light scattering resulting from lights emitted from neighboringpixels 610. - In order to obtain the desired profile of the
material spacers 630 a, the etch process includes a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. In still other embodiments, the etch process may include: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Referring to
FIG. 6C , adielectric layer 640 is substantially filled within theopening 625 shown inFIG. 6B . Thedielectric layer 640 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer. Thedielectric layer 640 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form thedielectric layer 640. A portion (not shown) of thedielectric layer 640 over the top surface of thedielectric layer 620 is removed, for example, by an etch-back process or CMP process. In some embodiments, thedielectric layer 640 may be slightly recessed within theopening 625 or extrude over the top surface of thedielectric layer 620, if the recess or the extrusion of thedielectric layer 640 does not adversely affect of illumination performance of thepixel 610 and/or the subsequent process to seal thegaps 650 shown inFIG. 6E . - Referring to
FIG. 6D , thematerial spacers 630 a are substantially removed by an oxygen-containing plasma process to form thegaps 650 between thedielectric layers gap 650 is substantially equal to the width of thematerial spacer 630 a, i.e., about 1,000 Å to about 1,500 Å. In some embodiments, thematerial spacers 630 a can be removed by a plasma process that has a desired etch rate for thematerial spacers 630 a, if the plasma process does not substantially damage thedielectric layers material spacers 630 a include amorphous carbon, the ash process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Though the
gap 650 has an aspect ratio (depth/width) of about 18.7 to about 38, the oxygen-containing plasma process can substantially remove thematerial spacers 630 a within thegaps 650 without substantially damaging thedielectric layers - In some embodiments, the
material spacers 630 a between thedielectric layers pixel 610 and/or thedielectric layer 615 within thegaps 650. In other embodiments, a portion of thematerial spacers 630 a remains within thegap 650 as long as a desiredair gap 670 as shown inFIG. 6E can be obtained. - Referring to
FIG. 6E , adielectric layer 660 is formed over thedielectric layers FIG. 6D ) to form theair gaps 670. Thedielectric layer 660 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer. Thedielectric layer 660 has poor deposition conformity so that thedielectric layer 660 can be formed thicker at the top and bottom regions of thegap 650 and thinner at the central region of thegaps 650. In some embodiment for 0.18-μm semiconductor technology, thedielectric layer 660, such as a plasma enhanced (PE) oxide, has a thickness of about 2,000 Å to about 3,000 Å from the top surface of thedielectric layer 620 to the top surface of thedielectric layer 660. In some embodiments, thedielectric layer 660 is formed by a plasma enhanced chemical vapor deposition (PECVD) process to seal top regions of thegaps 650 to form theair gaps 670. With theair gaps 670, the scattering effect resulting from lights emitted from neighboringpixels 610 can be substantially reduced or prevented. - The dimensions of the dielectric layers and material layer set forth above are illustrated by embodiments using 0.18-μm semiconductor technology. The present invention is not limited thereto. One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired air gap structure over a pixel.
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FIGS. 7A-7E are schematic cross-sectional views illustrating a process for formation of air gaps next to a conductive layer. - Referring to
FIG. 7A , aconductive line 710 is formed over asubstrate 700. Thesubstrate 700 may be similar to thesubstrate 200. In some embodiments, thesubstrate 700 includes transistors, devices or circuits (not shown) thereon coupled to theconductive line 710. In some embodiments, theconductive line 710 comprises abarrier layer 711, aconductive layer 713 and acap layer 715. Thebarrier layer 711 andcap layer 715 can be, for example, a titanium (Ti) layer, titanium nitride (TiN) layer, Ti/TiN layer or a material layer that can protect theconductive layer 713 or enhance adhesion between theconductive line 710 and a dielectric layer (not shown) over thesubstrate 700 or adielectric layer 750 over theconductive line 710 as shown inFIG. 7E . Thebarrier layer 711 andcap layer 715 can be formed, for example, by a CVD process, PVD process, chemical plating process or other process that can form thebarrier layer 711 and thecap layer 715. Theconductive layer 713 can be, for example, an aluminum/copper layer, aluminum layer, copper layer or other metal-containing layer. Theconductive layer 713 can be formed, for example, by a CVD process, PVD process, chemical plating process or other process that can form the metal-containing layer. In some embodiments, each of the barrier layers 711, such a TiN layer, andcap layer 715, such as a TiN layer, has a thickness of about 200 Å to about 500 Å; and theconductive layer 713, such as an aluminum copper layer, has a thickness of about 4,000 Å to about 10,000 Å. The thicknesses of the layers vary with layer level of theconductive line 710. For example, if theconductive line 710 is formed within an inter-layer dielectric (ILD) layer, theconductive line 710 has a small thickness. If theconductive line 710 is formed as a top metal layer over the substrate, theconductive line 710 has a large thickness. - A substantially
conformal material layer 720 is formed over theconductive line 710 and thesubstrate 700. Thematerial layer 720 is similar to thematerial layer 230 as set forth above. In some embodiments, thematerial layer 720, such as an amorphous carbon layer, has a thickness of about 250 Å to about 450 Å. - Referring to
FIG. 7B , a portion of thematerial layer 720 is removed by an etch process to formmaterial spacers 720 a on sidewalls of theconductive line 710 and to expose a top region of theconductive line 710, such as the top surface of thecap layer 715, and the other regions of thesubstrate 700 not covered by thematerial spacers 720 a. In some embodiments, thematerial spacers 720 a are not substantially laterally etched by the etch process so as to form a desired profile thereof. The material spacers 720 a is then removed to obtain a desired width ofgaps 740 as shown inFIG. 7D . The width of thegaps 740 is used to form desiredair gaps 760 as shown inFIG. 7E . Theair gaps 760 can efficiently reduce the dielectric constant of the dielectric material between two neighboringconductive lines 710. In some embodiments, the etch process has an etch selectivity for thematerial layer 720 to a dielectric layer (not shown) over thesubstrate 700 and under theconductive line 710. Thus, the etch process does not substantially damage the dielectric layer over thesubstrate 700 and thesubstrate 500 can be effectively protected by the dielectric layer. - In order to obtain the desired profile of the
material spacers 720 a, the etch process may include a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. In still other embodiments, the etch process may include: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Referring to
FIG. 7C , adielectric layer 730 is formed adjacent to the sidewalls of thematerial spacers 730 to expose a top surface of theconductive line 710 and top surfaces of thematerial spacers 720 a. Thedielectric layer 730 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer that can isolate neighboringconductive lines 710. Thedielectric layer 730 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a dielectric layer. In some embodiments, the dielectric 730, such as a low-k dielectric layer, has a thickness of about 4,000 Å to about 1 μm. - Referring to
FIG. 7D , thematerial spacers 720 a are substantially removed by an oxygen-containing plasma process to form thegaps 740 between thedielectric layer 730 and theconductive line 710. In some embodiments, thematerial spacers 720 a can be removed by a plasma process that has a desired etch rate for thematerial spacers 720 a, if the plasma process does not substantially damage thedielectric layer 730 and/or theconductive line 710. In some embodiments in which thematerial spacers 720 a include amorphous carbon, the plasma process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Though the
gap 740 has an aspect ratio (depth/width) of about 9 to about 40, the oxygen-containing plasma process can substantially remove thematerial spacers 720 a within thegaps 740 without substantially damaging thedielectric layer 730 and/or theconductive line 710. - In some embodiments, the
material spacers 720 a between thedielectric layer 730 and/or theconductive line 710 are substantially completely removed to expose portions of the top surface of thesubstrate 700 within thegaps 740. In other embodiments, a portion of thematerial spacer 720 a remains within thegap 740 as long as a desiredair gap 760 as shown inFIG. 7E can be obtained. - Referring to
FIG. 7E , adielectric layer 750 is formed over thedielectric layer 730 and theconductive line 710 to seal the gaps 740 (shown inFIG. 7D ) to form theair gaps 760. Thedielectric layer 750 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other dielectric layer. Thedielectric layer 750 has poor deposition conformity so that thedielectric layer 750 can be formed thicker at the top and bottom regions of thegap 740 and thinner at the central region of thegaps 740. In some embodiment, thedielectric layer 750, such as a plasma enhanced (PE) oxide, has a thickness of about 2,000 Å to about 3,000 Å from the top surface of thedielectric layer 730 to the top surface of thedielectric layer 750. In some embodiments, thedielectric layer 750 is formed by a plasma enhanced chemical vapor deposition (PECVD) process to seal top regions of thegaps 740 to form theair gaps 760. With theair gaps 760, the dielectric constant between neighboringconductive lines 710 is reduced. Thus, resistance-capacitance (RC) time delay resulting from parasitic capacitance between two neighboringconductive lines 710 can be reduced. -
FIGS. 8A-8F are schematic cross-sectional views illustrating a process for formation of a self-aligned contact plug. - Referring to
FIG. 8A , a pair oftransistor gates 810 are formed over asubstrate 800. In some embodiments, thetransistor gate 810 includes, for example, aconductive layer 811, agate insulator 813 andspacers 815. Thesubstrate 800 can be similar to thesubstrate 200 as set forth above. Theconductive layer 811 can be, for example, a polysilicon layer, amorphous silicon layer, silicon/silicon germanium (SiGe), a metal-containing layer, such as a TiN layer, or other conductive layer that can be a gate of a transistor. Theconductive layer 811 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate of a transistor. Thegate insulator 813 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can insulate theconductive layer 811 from thesubstrate 800. Thegate insulator 813 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate insulator of a transistor. Thespacers 815 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can protect theconductive layer 811 from damages caused by subsequent process. Thespacers 815 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process or other process that can form a gate insulator of a transistor. In some embodiments using 90-nm or 65-nm semiconductor technology, theconductive layer 811, such as a polysilicon layer, has a thickness of about 1,200 Å to about 1,700 Å; thegate insulator 813, such as an oxide layer, has a thickness of about 20 Å to about 40 Å; a thickest portion of thespacer 815, such as nitride spacers, has a thickness of about 400 Å to about 700 Å; and a distance “d” between the sidewalls of theconductive layers 811 is of about 0.2 μm to about 0.3 μm. - A
material layer 820 is formed over thetransistor gates 810 and thesubstrate 800. Thematerial layer 820 is similar to thematerial layer 340 as described above. Detailed descriptions are not repeated. In some embodiments of 90-nm or 65-nm semiconductor technology, thematerial layer 820 has a thickness from the top surface of thesubstrate 800 to the top surface of thematerial layer 820 of about 3,800 Å to about 4,300 Å. - A
dielectric layer 823 is formed over thematerial layer 820. Thedielectric layer 823 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can be a hard mask for a subsequent etch process to form an opening within the material layer as shown inFIG. 8B . Thedielectric layer 823 can be formed, for example, by a CVD process, PFD process, atomic layer deposition (ALD) process or other process that can form a dielectric hard mask. In some embodiments of 90-nm or 65-nm semiconductor technology, thedielectric layer 823, such as an oxynitride layer, has a thickness of about 600 Å to about 1,000 Å. Aphotoresist layer 825 including anopening 827 is formed over thedielectric layer 823. Thephotoresist layer 825 can be formed by a photolithographic process. Theopening 827 has a width of about 0.13 μm to about 0.15 μm. Theopening 827 is defined at a location under which acontact plug 840 a as shown inFIG. 8D is to be formed. - Referring to
FIG. 8B , a portion of thedielectric layer 823 and a portion of thematerial layer 820 are removed to form anopening 830 within thematerial layer 820 a and between thetransistor gates 810 to expose a partial top surface of thesubstrate 800. - In some embodiments, the etch process has a desired selectivity for the
material layer 820 a to thedielectric layers 823 a so that the etch process does not substantially damage the exposed top surface of thesubstrate 800 within theopening 830. In some embodiments, the remainingmaterial 820 a are not substantially laterally etched by the etch process, so that a desired profile of theopening 830 is achieved. In some embodiments, in order to obtain the desired profile of theopening 830, the etch process includes a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. In other embodiments in which the profile of theopening 830 is not a concern, the etch process includes a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. After the formation of theopening 830, thephotoresist layer 825 is removed. The removal process of thephotoresist layer 825 can be any photoresist removal process. - In some embodiments, the
spacers 815, such as nitride spacers, serve as a hard mask when the portion of thematerial layer 820 is removed to form theopening 830. As set forth above, the etch process has a desired etch selectivity, such as about 80:1 to about 120:1, for thematerial layer 820 a to thespacer 815. Thespacers 815 are not substantially damaged by the etch process and thus are able to protect theconductive layer 811 from being damaged. - Referring to
FIG. 8C , aconductive layer 840 is formed within theopening 830, covering thedielectric layer 823 a. Theconductive layer 840 can be, for example, an aluminum/ copper layer, aluminum layer, copper layer, tungsten layer or other conductive material layer. Theconductive layer 840 can be formed, for example, by a CVD process, PVD process, chemical plating process, chemical electroless plating or other process that can form theconductive layer 840. In some embodiments, prior to the formation of theconductive layer 840, a barrier layer, such as TiN (not shown), is formed within theopening 830 and over thedielectric layer 823 a. - Referring to
FIG. 8D , an etch-back process or CMN process removes thedielectric layer 823 a and a portion of theconductive layer 840 over the top surface of thematerial layer 820 a to form theconductive layer 840 a, i.e., a via/conduct plug, within theopening 830. In some embodiments which include the TiN barrier layer (not shown) as described above, the etch-back or CMP process also removes a portion of the barrier layer over the top surface of thematerial layer 820 a. - Referring to
FIG. 8E , the remainingmaterial layer 820 a is removed by an oxygen-containing plasma process to expose a top region of theconductive layer 840 a over a top surface of thetransistor gate 810. In some embodiments, thematerial layer 820 a can be removed by a plasma process that has a desired etch rate for thematerial layer 820 a, if the plasma process does not substantially damage thesubstrate 800, theconductive layer 840 a and/or thetransistor gates 810. In some embodiments in which thematerial layer 820 include amorphous carbon, the ash process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. Because the plasma process does not substantially damage thesubstrate 800, theconductive layer 840 a and/or thetransistor gates 810, a desired profile of theconductive plug 840 a can be obtained as shown inFIG. 8E . - Referring to
FIG. 8F , adielectric layer 850 is formed, covering thetransistor gates 810 and theconductive layer 840 a to expose a top surface of theconductive layer 840 a. Thedielectric layer 850 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other material layer that can insulate thetransistor gates 810 from other transistor gate or circuit (not shown). Thedielectric layer 850 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process, spin-on process or other process that can form a dielectric layer. A portion of thedielectric layer 850 over the top surface of theconductive layer 840 a (not shown) is then removed by an etch-back process or CMP process. In some embodiments of 90-nm or 65-nm semiconductor technology, thedielectric layer 850 has a thickness of about 3,800 Å to about 4,300 Å from the top surface of thesubstrate 800 to the top surface of thedielectric layer 850. Compared with a dielectric material, such as oxide or nitride, thematerial layer 820 has a low thermal stability when thematerial layer 820 is subjected to a subsequent thermal process, such as a thermal curing process. Thematerial layer 820 is thus removed and thedielectric layer 850 is formed to cover thetransistor gates 810 so that subsequent thermal processes can be properly performed for thesubstrate 800. - The dimensions of the dielectric layers, material layer and gate transistor set forth above are illustrated by 90-nm or 65-nm semiconductor technology. The present invention is not limited thereto. One of ordinary skill in the art can understand that these physical characteristics vary with applied semiconductor process and readily form a desired via/contact plug.
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FIGS. 9A-9E are schematic cross-sectional views illustrating a process for formation of a via/contact plug or a conductive line. - Referring to
FIG. 9A , adielectric layer 910 is formed over asubstrate 900. Thesubstrate 900 is similar to thesubstrate 200. Detailed descriptions are not repeated. In some embodiments, thesubstrate 900 includes, for example, at least one transistor, device or circuit (not shown) thereon coupled to a conductive layer 970 (shown inFIG. 9E ). Thedielectric layer 910 can be, for example, an oxide layer, nitride layer, oxynitride layer, low-k dielectric layer or other material layer that can insulate the conductive layer 970 (shown inFIG. 9E ) from other conductive layer (not shown). Thedielectric layer 910 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process, spin-on process or other process that can form a dielectric layer. In some embodiments, thedielectric layer 910, such as an oxide layer, has a thickness of about 3,000 Å to about 1.5 μm. - A
material layer 920 is formed over thedielectric layer 910. Thematerial layer 920 is similar to thematerial layer 340 described above. Detailed descriptions are not repeated. In some embodiments, thematerial layer 920 has a thickness of about 2,500 Å to about 8,000 Å. - A
dielectric layer 930 is formed over thematerial layer 920. Thedielectric layer 930 can be, for example, an oxide layer, nitride layer, oxynitride layer or other material layer that can serve as an etch stop layer. Thedielectric layer 920 can be formed, for example, by a CVD process, PVD process, atomic layer deposition (ALD) process, spin-on process or other process that can form a dielectric layer. In some embodiments, thedielectric layer 930 has a thickness of about 600 Å to about 1,000 Å. - The
photoresist layer 935 including anopening 937 therein is formed over thedielectric layer 930. Thephotoresist layer 935 including theopening 937 therein can be formed by a photolithographic process. - Referring to
FIG. 9B , a portion of thedielectric layer 930 and a portion of thematerial layer 920 are removed to form anopening 940 within the remainingmaterial layer 920 a to expose a portion of the top surface of thedielectric layer 910. An etch process having a desired etch selectivity for thedielectric layer 930 to thematerial layer 920 removes the portion of thedielectric layer 930 defined by the opening 937 (shown inFIG. 9A ). Thephotoresist layer 935 is then removed by a photoresist removal process, and the remainingdielectric layer 930 a is used as a hard mask to protect thematerial layer 920 a from being damaged by the photoresist removal process. Thedielectric layer 930 a is used as a hard mask layer for removal of the portion of thematerial layer 920 by an etch process. In other embodiments, thephotoresist layer 935 is removed while thematerial layer 920 is partially removed by a hydrogen-containing process. For these embodiments, theopening 940 is formed within thematerial layer 920 a while thephotoresist layer 935 is substantially removed. - The sidewalls of the
material layer 920 a are not substantially laterally etched by the etch process to obtain a desired profile of theopening 940. A substantiallyconformal material layer 950 is formed over theopening 940 and thedielectric layer 930 a. Thematerial layer 950 is similar to thematerial layer 230 as described above. In some embodiments, thematerial layer 950 has a thickness of about 200 Å to about 400 Å. In order to obtain the desired profile of theopening 940, the etch process includes a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. In other embodiments in which the profile of theopening 940 is not a concern, the etch process includes a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Referring to
FIG. 9C , a portion of thematerial layer 950 is removed by an etch process to expose a top surface of thedielectric layer 930 a and a portion of the top surface of thedielectric layer 910 and to formmaterial spacers 950 a on sidewalls of thematerial layer 920 a. In some embodiments, thematerial spacers 950 are not substantially laterally etched by the etch process so as to obtain a desired profile thereof. The material spacers 950 a is achieved so that an opening 960 (shown inFIG. 9D ) can be formed by a subsequent etch process. With the desired profile of thematerial spacers 950 a, a via/contact hole or a trench of a conductive line with a small width, i.e., the width of the opening 960 (shown inFIG. 9D ) is achieved. In order to achieve the desired profile of the material spacers 905 a, the ash process includes a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr. In other embodiments in which the profile of thematerial spacers 950 a is not a concern, the etch process includes a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. - Referring to
FIG. 9D , a portion of thedielectric layer 910 is removed to form theopening 960 within thedielectric layer 910 a by using thematerial spacers 950 a as a hard mask. In some embodiments, thedielectric layer 930 a and portions of thematerial spacers 950 a over the top surface of the 920 a are removed by an etch process. Then, thematerial spacers 950 a and the material layers 920 a are used as a hard mask for etching thedielectric layer 910 to form theopening 960. In other embodiments, thematerial spacers 950 a and thedielectric layer 930 a are used as a hard mask for etching thedielectric layer 910 to form theopening 960. For the removal of thedielectric layer 930 a, the etch process has a desired etch selectivity for thedielectric layer 930 a to thematerial spacers 950 a so that thematerial spacers 950 a are not substantially removed. - Referring to
FIG. 9E , thematerial spacers 950 a and thematerial layer 920 a are removed by an oxygen-containing plasma process, and theconductive layer 970 is formed within theopening 960. In some embodiments, thematerial spacers 950 a and thematerial layer 920 a can be removed by a plasma process that has a desired etch rate for thematerial layer 920 a and spacers 950 a, if the plasma process does not substantially damage the exposed portion of the top surface of thesubstrate 900 and/or thedielectric layer 910 a. In some embodiments in which thematerial layer 920 a andspacers 950 include amorphous carbon, the plasma process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr. Because the plasma process does not substantially damage the exposed top surface of thesubstrate 900 and/or thedielectric layer 910 a (as shown inFIG. 9E ), theconductive layer 970 can be properly formed within theopening 960. - The
conductive layer 970 can be, for example, an aluminum/copper layer, aluminum layer, copper layer, tungsten layer or other conductive material layer. Theconductive layer 970 can be formed, for example, by a CVD process, PVD process, chemical plating process, chemical electroless plating or other process that can form theconductive layer 970. - The dimensions of the dielectric layers, material layers and openings vary with the metal level where the
conductive layer 970 is formed. For example, if theconductive layer 970 is formed within an inter-layer dielectric (ILD) layer, theconductive line 910 has small physical dimensions. If theconductive layer 970 is formed as a top metal layer over the substrate, theconductive layer 970 has large physical dimensions. - Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be constructed broadly to include other variants and embodiments of the invention which may be made by those skilled in the field of this art without departing from the scope and range of equivalents of the invention.
Claims (18)
1. A method, comprising the steps of:
(a) forming a conductive layer within a dielectric layer formed over a substrate;
(b) forming a material layer over the conductive layer and the dielectric layer;
(c) forming an opening within the material layer by an etch process to expose a portion of the dielectric layer and a top surface of the conductive layer;
(d) forming a first metal-containing layer within the opening substantially covering sidewalls of the material layer and the exposed portion of the second dielectric layer; and
(e) removing the material layer by an oxygen-containing plasma process to expose a portion of outer sidewalls of the first metal-containing layer.
2. The method of claim 1 , wherein the material layer comprises an amorphous carbon layer.
3. The method of claim 2 , wherein the material layer is formed by a deposition process comprising: a flow of C3H6 between about 1,500 standard cubic centimeters per minute (sccm) and about 2,500 sccm; a flow of He between about 500 sccm and about 900 sccm; a radio-frequency (RF) power between about 1,200 watts and about 1,800 watts; and a pressure between about 4.5 Torr and about 5.5 Torr.
4. The method of claim 2 , wherein the etch process comprises: a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
5. The method of claim 2 , wherein the oxygen-containing plasma process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
6. The method of claim 1 , further comprising:
forming a high-k material layer substantially covering the exposed outer sidewalls, a top region and an inner sidewall of the first metal-containing layer; and
forming a second metal-containing layer substantially covering the high-k material layer.
7. A method, comprising the steps of:
(a) forming an opening within a first dielectric layer over a substrate, the opening exposing a substantial top surface of a pixel;
(b) forming a substantially conformal material layer over the first dielectric layer and the exposed top surface of the pixel;
(c) removing a portion of the material layer by an etch process to form spacers on sidewalls of the first dielectric layer;
(d) forming a second dielectric layer substantially filling within the opening;
(e) removing the spacers by an oxygen-containing plasma process to form gaps between the first and second dielectric layers; and
(f) forming a third dielectric material over the first and second dielectric layers to form air gaps.
8. The method of claim 7 , wherein the material layer comprises an amorphous carbon layer.
9. The method of claim 8 , wherein the material layer is formed by a deposition process comprising: a flow of C3H6 between about 1,000 standard cubic centimeters per minute (sccm) and about 1,500 sccm; a flow of He between about 400 sccm and about 500 sccm; a radio-frequency (RF) power between about 800 watts and about 1,200 watts; and a pressure between about 3.5 Torr and about 4.5 Torr.
10. The method of claim 7 , wherein the etch process comprises: a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
11. The method of claim 7 , wherein the oxygen-containing plasma process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
12. The method of claim 7 , wherein step (f) is performed by a plasma enhanced chemical vapor deposition (PECVD) process to seal top regions of the gaps to form the air gaps.
13. A method, comprising the steps of:
(a) forming a material layer covering a pair of transistor gates formed over a substrate;
(b) removing a portion of the material layer by an etch process to form an opening within the material layer and between the transistor gates to expose a partial top surface of the substrate;
(c) forming a conductive layer within the opening;
(d) removing the remaining material layer by an oxygen-containing plasma process to expose a top region of the conductive layer above top surfaces of the transistor gates; and
(e) forming a dielectric layer covering the transistor gates and the conductive layer to expose a top surface of the conductive layer.
14. The method of claim 13 , wherein the material layer comprises an amorphous carbon layer.
15. The method of claim 14 , wherein the material layer is formed by a deposition process comprising: a flow of C3H6 between about 1,500 standard cubic centimeters per minute (sccm) and about 2,500 sccm; a flow of He between about 500 sccm and about 900 sccm; a radio-frequency (RF) power between about 1,200 watts and about 1,800 watts; and a pressure between about 4.5 Torr and about 5.5 Torr.
16. The method of claim 13 , wherein the etch process comprises: a flow of hydrogen (H2) between about 80 standard cubic centimeters per minute (sccm) and about 150 sccm; a flow of nitrogen (N2) between about 150 sccm and about 300 sccm; a radio-frequency (RF) power between about 800 watts and about 1,500 watts; and a pressure between about 15 mTorr and about 50 mTorr.
17. The method of claim 13 , wherein the oxygen-containing plasma process comprises: a flow of oxygen (O2) between about 500 standard cubic centimeters per minute (sccm) and about 2,000 sccm; a radio-frequency (RF) power between about 200 watts and 2,000 watts; and a pressure between about 20 mTorr and 200 mTorr.
18. The method of claim 13 , wherein step (e) is performed by at least one process of a group consisting of a high density plasma chemical vapor deposition (HDP CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process and spin-on process.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/461,673 US20080124912A1 (en) | 2006-08-01 | 2006-08-01 | Semiconductor methods |
TW096104426A TW200809950A (en) | 2006-08-01 | 2007-02-07 | Method for fabricating semiconductor device |
TW099139911A TWI451490B (en) | 2006-08-01 | 2007-02-07 | Method for fabricating semiconductor device |
US12/357,661 US7824998B2 (en) | 2006-08-01 | 2009-01-22 | Method of forming a semiconductor capacitor using amorphous carbon |
Applications Claiming Priority (1)
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US11/461,673 US20080124912A1 (en) | 2006-08-01 | 2006-08-01 | Semiconductor methods |
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Publications (1)
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US20080124912A1 true US20080124912A1 (en) | 2008-05-29 |
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ID=39464225
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US11/461,673 Abandoned US20080124912A1 (en) | 2006-08-01 | 2006-08-01 | Semiconductor methods |
US12/357,661 Expired - Fee Related US7824998B2 (en) | 2006-08-01 | 2009-01-22 | Method of forming a semiconductor capacitor using amorphous carbon |
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TW (2) | TW200809950A (en) |
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Also Published As
Publication number | Publication date |
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US7824998B2 (en) | 2010-11-02 |
TW201123294A (en) | 2011-07-01 |
TW200809950A (en) | 2008-02-16 |
TWI451490B (en) | 2014-09-01 |
US20090130814A1 (en) | 2009-05-21 |
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